JPH0516776B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a bit string comparison circuit, and more particularly, the present invention relates to a bit string comparison circuit, and particularly to a bit string comparison circuit that compares two data signals each consisting of a plurality of bit strings and which are equal except for the difference in the arrangement order of each string. The present invention relates to a bit string comparison circuit for determining whether or not the arrangement order of bit strings matches each other.

[Conventional technology]

Such bit string comparison circuits are often required in electronic devices that handle data signals. A conventional bit string comparison circuit will be explained by taking as an example the case where it is used for line switching in a digital radio communication system that has a working line and a protection line and uses a 16-value orthogonal amplitude modulation method.

A data signal input as a bit string from a transmitting carrier terminal station is split into two in a hybrid system, and one is transmitted over the working line and the other through the protection line. 16
Since the value-orthogonal amplitude modulated wave is created from four columns of data signals, the two outputs of the hybrid are each serial-parallel converted from one column to four columns. The arrangement order of the four columns is not determined due to the phase uncertainty of frequency division. In other words, it is uncertain in which column of the four converted data signals a certain bit in one column of data signals is placed. Therefore, the arrangement order of the four columns of data signals input to the working transmitter and the standby transmitter is not necessarily the same. On the receiving side, the working receiver outputs the data signal input to the working transmitter, and the backup receiver outputs the data signal input to the backup receiver, so each of these two sets of 4-column data signals on the receiving side However, the order of the arrays does not necessarily match.

The propagation delay time in the wireless transmission path fluctuates due to fading, etc., and this fluctuation does not necessarily match between the working line and the protection line, so the two sets of data signals on the receiving side are not only different in the arrangement order mentioned above, but also due to timing differences. do not necessarily coincide within one time slot. These binary data signals are serial-parallel converted from 1 column to (for example) 4 columns for each column, and are converted from 4 columns to 16 columns, respectively. This conversion increases the time slot length by four times, so that the difference in propagation delay time between the working line and the protection line can be absorbed. However, the arrangement order of these two sets of 16 columns of data signals does not necessarily match.

By comparing two sets of 16 columns of data signals with a bit string comparison circuit, it is determined whether the arrangement order matches or not. For example, when switching from a working line to a protection line, if the arrangement order does not match, change the arrangement order of the 16 columns of data signals on the protection line to match the arrangement order of the 16 columns of data signals on the working line. . The arrangement order of 16 columns of data signals created by serial-parallel conversion of 1 column of data signals is:
Since the arrangement order is one of 16 ways that are cyclically different from each other, one arrangement order of each of the two sets of 16 column data signals is cyclically changed to a maximum of 15 If you rearrange it twice, it will always match the other arrangement order. By switching from one of the two sets of data signals arranged in the same order to the other at the timing when the respective bits match, line switching can be performed without code errors.

FIG. 2 is a block diagram showing one of the conventional examples of the above-mentioned bit string comparison circuit.

Exclusive OR (hereinafter referred to as EX-OR) circuit 1
-1 is the bit string D1-1, D2- which is the first column of the 16 column data signals D1, D2, respectively.
1 is input, and a signal S1 is output. Bit string D1
If the bits -1 and D2-1 match each other, the signal S1 becomes "0", and if they do not match, the signal S1 becomes "1".
become. EX-OR circuits 1-2 to 1 to 16 input the bit strings D1-2 to D1-16 and D2-2 to D2-16, and output similar signals S2 to S16.
The OR circuit 6 inputs the signals S1 to S16 and outputs the logical sum as a signal S17. data signal D1,
Signal S17 is output once for each time slot of D2.

If the data signals D1 and D2 are arranged in the same order and there is no transmission code error, the bits in the bit strings D1-j and D2.j (j is an integer from 1 to 16) always match each other. , all signals Sj are “0”
, and the signal S17 also becomes a series of "0"s. However, in reality, the signal S17 may become "1" due to a transmission code error, although the probability is small. If the arrangement order of data signals D1 and D2 does not match each other, there is usually a large probability that signal S1
7 becomes “1”. By counting the signal S17 for a predetermined period of time and finding the probability that the signal S17 becomes "1", it is determined whether the arrangement order of the data signals D1 and D2 matches or does not match.

However, when the data signal input from the transmitting carrier terminal station has a light load and has almost no bit change components, the data signal D is
It becomes very difficult to determine whether the arrangement order of 1 and D2 matches or does not match. This will be further explained below.

The data signal input from the transmitting carrier terminal station is
Suppose it is 140Mbps. For example, a 140Mbps data signal consists of 1 superframe with 2928 bits, and each superframe has 1.1.1.
Contains frame synchronization bits in a pattern of 1, 1, 0, 1, 0, 0, 0, 0, 0. Consider the case when all bits other than the frame synchronization bit become "0" (or "1"). At this time,
Frame synchronization bits are all data signals D1, D
If it is placed in the same time slot of 2,
If the arrangement order of the data signals D1 and D2 does not match each other, the conventional example shown in FIG.
Set 17 to “1”. If the frequency of occurrence of "1" is small in this way, it becomes impossible to distinguish it from the occurrence of "1" due to a transmission code error, and it is not possible to determine whether the arrangement order matches or mismatches in the conventional example shown in Fig. 2. .

[Problem that the invention seeks to solve]

As explained above, the conventional bit string comparison circuit outputs the comparison result only once for each time slot of two input data signals, and therefore has the disadvantage that the amount of information output is small.

SUMMARY OF THE INVENTION An object of the present invention is to provide a bit string comparison circuit which can solve the above-mentioned drawbacks and output a large amount of information.

[Means for solving problems]

The bit string comparison circuit of the present invention consists of two sets of bit string groups in which m×n bit strings (m and n are integers of 2 or more) are arranged in orders that are not necessarily equal to each other, each arranged in the same order. inputting the two said bit strings in each of said orders, respectively;
There are m×n coincidence determination means that determine whether each bit matches or mismatches and outputs the determination result as a first determination signal; or whether at least one of them shows a discrepancy;
n logical means for outputting a determination result as a second determination signal; and parallel-to-serial conversion means for inputting the n second determination signals, converting them from parallel to serial, and outputting them as a third determination signal. Prepared and configured.

〔Example〕

The present invention will be described in detail below with reference to drawings showing embodiments.

FIG. 1 is a block diagram showing an embodiment of a bit string comparison circuit of the present invention.

In the embodiment shown in FIG.
EX-OR circuits 1-1 to 1-16 that input signals 1-16 and bit strings D2-1 to D2-16 and output signals S1 to S16, and OR circuits 1-1 to 1-16 that input signals S1 to S4 and output signals S21. Circuit 2-1 and signal S5
~OR circuit 2 that inputs S8 and outputs signal S22
-2, an OR circuit 2-3 which inputs signals S9-S12 and outputs signal S23, and signals S13-S16.
OR circuit 2-4 which inputs and outputs signal S24
, the signals S21-S24, the clock signal and CL1
AND circuits 3-1 to 3-4 which input signals S31 to S34 and output signals S31 to S34;
an OR circuit 4 which inputs 34 and outputs a signal S0;
Input clock signal CLin and clock signal CL1~
The clock distribution section 5 outputs the clock signal CL4.

The clock distribution section 5 includes flip-flop circuits (hereinafter referred to as FF) 51 to 54 and a NAND circuit 5.
5. A clock signal CLin is input to the clock input terminal C of FFs 51-54. The outputs of the non-inverting output terminals Q of the FFs 51 to 53 are input to the data input terminals D of the FFs 52 to 54 and the NAND circuit 55. The output of NAND circuit 55
Input to data input terminal D of FF51. FF51
The output of the inverted output terminal of ~54 is the clock signal.
It becomes CL1 to CL4.

FIG. 3 is a time chart for explaining the operation of the embodiment shown in FIG.

The data signal D1 consisting of bit strings D1-1 to D1-16 is the same signal as the data signal D2 consisting of bit strings D2-1 to D2-16 except for the difference in the arrangement order of each column.

The EX-OR circuit 1-j inputs the bit string D1-j and the bit string D2-j and matches each bit.
It is the same as in the conventional example shown in FIG. 2 that a mismatch is determined and a signal Sj is output which becomes "0" if the bits match each other and becomes "1" if they do not match. The OR circuit 2-1 is the signal S1-S
Since the logical sum of 4 is output as the signal S21, the signal S21 becomes "0" only in a time slot where all of the signals S1 to S4 indicate a match, and becomes "1" if even one shows a mismatch. become. Similarly, OR circuit 2-2, 2-3, 2-
4 is the signal S5-S8, S9-S12, S13-
Signals S22, S23, and S24 are generated from S16.

The clock signal CLin is a clock for the data signals D1 and D2, and has a timing relationship with the bit string Di-j (i is 1 or 2), the signal Sj, and the signals S21 to S24 as shown in FIG.

The clock distribution section 5 generates clock signals CL1 to CL4 shown in FIG. 3 from the clock signal CLin. Clock signals CL1 to CL4 are clock signals
It is "1" for a period of 1/4 of the period T of CLin, "0" for a period of 3/4, and the phases are sequentially shifted by T/4.
The rising edge of any one of the clock signals CL1 to CL4 coincides with the rising edge of the clock signal CLin. The selection of one of these is determined by the initial conditions of FFs 51 to 54, and is shown as clock signal CL1 in FIG.

Signals S21 to S24 are AND circuits 3-1 to 3-
4, the pulse waveforms of the clock signals CL1 to CL4 are combined by the OR circuit 4, and the signal S
becomes 0. In other words, AND circuits 3-1 to 3
-4 and OR circuit 4 are clock signals CL1 to CL4.
The signals S21 to S24 are converted from parallel to serial using the converter to generate the signal S0.

As explained above, the embodiment shown in FIG. 1 has a large amount of information because the signal S0, which is the comparison result, is output four times for each time slot of the data signals D1 and D2. This will be further explained using, as an example, the case where the embodiment shown in FIG. 1 is applied to line switching in the digital wireless communication system described in the [Prior Art] section.

The bits of one row of data signals input from the transmitting carrier terminal station are 1, 1, 1, 1, 1, 01, 0, 0,
All data except the frame synchronization bit with a pattern of 0, 0, 0 becomes "0" (or "1"), and the arrangement order of the two data signals D1 and D2, each with 16 columns, is compared on the receiving side. Assume that they are cyclically shifted by one column from each other (this is the time when it is most difficult to compare the order of the arrays). At this time, the signal S0
is at least twice in the time slot (one or two consecutive) of the time slots of the data signals D1, D2 in which the frame synchronization bit is located, in other words at least twice in each superframe. "become. If there is a shift of two or more columns, the signal S0 is sent three or more times in each super frame.
becomes “1”.

The embodiment shown in FIG. 1 and its applications have been described above.

Number of columns m of two data signals whose arrangement order is compared
Even if ×n is given, there is generally a degree of freedom in setting m and n. For example, in the embodiment shown in FIG. 1, m=4 and n=4 for 16 columns, but n can also be set to 2 or 8. Increasing n increases the amount of information to be output, but at the cost of this it is necessary to increase the operating speed of the logic means and parallel-to-serial conversion means.

〔Effect of the invention〕

As explained in detail above, the bit string comparison circuit of the present invention outputs the comparison result n times (n is an integer of 2 or more) for each time slot of two input data signals, so the amount of information to be output is large. There is an effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of a bit string comparison circuit of the present invention, FIG. 2 is a block diagram showing an example of a conventional bit string comparison circuit, and FIG. 3 is a block diagram showing an example of a conventional bit string comparison circuit. This is a time chart for explaining the operation of the example. 1-1 to 1-16...EX-OR circuit, 2-1
~2-4...OR circuit, 3-1~3-4...AND
Circuit, 4...OR circuit, 5...Clock distribution section.

Claims (1)

[Claims] 1. Two sets of bit string groups in which m×n bit strings (m and n are integers of 2 or more) are arranged in mutually not necessarily equal orders, each of which is arranged in the same order. m×n coincidence determining means each inputting the bit string in each of the aforementioned orders, determining whether each bit matches or not, and outputting the determination result as a first determination signal; n logic means inputting m judgment signals each, determining whether all of them indicate a match or at least one indicating a mismatch, and outputting the judgment result as a second judgment signal; A bit string comparison circuit comprising: parallel-to-serial conversion means for inputting the second determination signal, converting it into parallel to serial, and outputting the resultant signal as a third determination signal.