JPS62279671A - Solid state image sensing device - Google Patents
Solid state image sensing deviceInfo
- Publication number
- JPS62279671A JPS62279671A JP61122716A JP12271686A JPS62279671A JP S62279671 A JPS62279671 A JP S62279671A JP 61122716 A JP61122716 A JP 61122716A JP 12271686 A JP12271686 A JP 12271686A JP S62279671 A JPS62279671 A JP S62279671A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor element
- base
- chip
- solid
- state imaging
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000007787 solid Substances 0.000 title 1
- 239000004065 semiconductor Substances 0.000 claims abstract description 40
- 238000003384 imaging method Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 abstract description 11
- 238000012360 testing method Methods 0.000 abstract description 5
- 230000000694 effects Effects 0.000 description 4
- 238000001444 catalytic combustion detection Methods 0.000 description 3
- 238000013100 final test Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 230000002950 deficient Effects 0.000 description 2
- 239000011521 glass Substances 0.000 description 2
- 230000003287 optical effect Effects 0.000 description 2
- 230000007423 decrease Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/14—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation
Landscapes
- Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Electromagnetism (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Solid State Image Pick-Up Elements (AREA)
- Facsimile Heads (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明は、ファクシミリ等に使用されるリニアの固体撮
像装置に関するものである。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a linear solid-state imaging device used in facsimiles and the like.
（従来の技術〕
ファクシミリ等の画像読取装置としては、例えば第３図
に示すものがある。この図において、■は半導体素子２
を載置するパッケージ基板、３はロッドレンズアレイ、
４は蛍光灯などの光源、５は原稿６の原稿面である。(Prior Art) An example of an image reading device such as a facsimile is shown in FIG. 3. In this figure, ■ indicates a semiconductor element 2.
3 is a rod lens array,
4 is a light source such as a fluorescent lamp, and 5 is the document surface of the document 6.
これらのうち、半導体素子２は、原稿６の送り方向であ
る矢印Ｆ１に対して垂直の方向に一次元状に配列されて
おり、情報を走査して読み出すことができるように電荷
結合素子（以下ｒｃｃＤＪという）も形成されている。Among these, the semiconductor elements 2 are arranged one-dimensionally in a direction perpendicular to the arrow F1, which is the feeding direction of the original 6, and are charge-coupled devices (hereinafter referred to as charge-coupled devices) so that information can be scanned and read out. rccDJ) has also been formed.
半導体素子２の配列方向が原稿面５の画像走査に対する
主走査方向であり、原稿６の矢印Ｆ１の送り方向が副走
査方向である。第４図には、パッケージ基板１上におけ
る半導体素子２の配列の様子が示されている。The arrangement direction of the semiconductor elements 2 is the main scanning direction with respect to image scanning of the document surface 5, and the feeding direction of the arrow F1 of the document 6 is the sub-scanning direction. FIG. 4 shows how the semiconductor elements 2 are arranged on the package substrate 1. As shown in FIG.
一般に、ファクシミリリーダとしては、縮小光学方式と
密着方式とがある。前者は、例えば、日本工業規格Ａ４
サイズの短辺（約２１０ｍｍ）に相当する長さの画像を
レンズ手段によってＣＣＤ１チツプの大きさく約１０ｍ
ｍ）まで縮小する方式であり、光路長が大きくなって装
置が大型になる。これに対し、後者の密着方式は、第３
図に示すように、ロッドレンズアレイ３の正立等倍結像
作用によって、原稿６．ロッドレンズアレイ３および半
導体素子２をコンパクトに配置できるという利点がある
。しかし反面、例えば上記Ａ４サイズの短辺と同じ大き
さのセンサが必要となり、ＣＯＤチップを使用する場合
には、必然的に多数のチップを並べることになる。この
ため、第４図に示す例では、４個の半導体素子２が配列
されている。Generally speaking, there are two types of facsimile readers: reduction optical type and contact type. The former is, for example, Japanese Industrial Standard A4
An image with a length corresponding to the short side (about 210 mm) of the size is captured by a lens device and is about 10 m long on one CCD chip.
m), which increases the optical path length and increases the size of the device. On the other hand, the latter contact method
As shown in the figure, the original 6. There is an advantage that the rod lens array 3 and the semiconductor element 2 can be arranged compactly. However, on the other hand, for example, a sensor of the same size as the short side of the above-mentioned A4 size paper is required, and when COD chips are used, a large number of chips are inevitably lined up. Therefore, in the example shown in FIG. 4, four semiconductor elements 2 are arranged.
第５図には、センサチップ２におけるフォトダイオード
とＣＣＤの配置例が示されており、この図において、７
はフォトダイオード部、８はトランスファゲート配線、
９はＣＣＤ部である。０００部９の電極は省略されてい
る。FIG. 5 shows an example of the arrangement of photodiodes and CCDs in the sensor chip 2. In this figure, 7
8 is the photodiode section, 8 is the transfer gate wiring,
9 is a CCD section. The electrode of 000 part 9 is omitted.
また、第６図には、半導体素子２の接続部分の１例が示
されている。フォトダイオード部７は、ｐ型半導体基板
１０の主表面上にｎ型半導体領域１１を設けることによ
って形成されている。このフォトダイオード部７が等間
隔に配列されるように、パフケージ基板１上における半
導体素子２の位置が定められる。Further, FIG. 6 shows an example of a connecting portion of the semiconductor element 2. As shown in FIG. Photodiode section 7 is formed by providing n-type semiconductor region 11 on the main surface of p-type semiconductor substrate 10 . The position of the semiconductor element 2 on the puff cage substrate 1 is determined so that the photodiode sections 7 are arranged at equal intervals.
次に、ロッドレンズアレイ３は、軸対策の屈折率分布を
持つ円柱状レンズを並べたものであり、王立等倍の結像
作用を奏するものである。各ロッドレンズ内の屈折率分
布は軸上が最も大きく周囲にいくほど低くなっている。Next, the rod lens array 3 is an array of cylindrical lenses having an axial refractive index distribution, and exhibits a royal life-size imaging function. The refractive index distribution within each rod lens is greatest on the axis and decreases toward the periphery.
次に上記従来例の動作について説明する。まず、第３図
に示すように、光−ａ４の光は矢印Ｆ２のように原稿面
５を照射する。原稿面５による反射光（矢印Ｆ３）は、
ロッドレンズアレイ３を通過し、半導体素子２上に結像
する。半導体素子２の像情報は、フォトダイオード部７
によって光量に対応する電荷量に変換され、蓄積された
電荷はトランスファゲート８によって０００部９に転送
され、順次読み出される。Next, the operation of the above conventional example will be explained. First, as shown in FIG. 3, light -a4 irradiates the document surface 5 in the direction of arrow F2. The light reflected by the document surface 5 (arrow F3) is
The light passes through the rod lens array 3 and is imaged onto the semiconductor element 2 . Image information of the semiconductor element 2 is transmitted to the photodiode section 7
The accumulated charges are transferred to the 000 unit 9 by the transfer gate 8 and sequentially read out.
従来の固体撮像装置は以上のように構成されていたので
、アセンブリの位置合わせが困難で、ファイナルテスト
時における不良チップが判明しても、不良チップ交換が
不可能であるため、歩留まりが低くなるという問題があ
った。Conventional solid-state imaging devices are configured as described above, making it difficult to align the assembly, and even if a defective chip is found during final testing, it is impossible to replace the defective chip, resulting in low yield. There was a problem.
本発明はこのような点に鑑みてなされたものであり、そ
の目的とするところは、アセンブリの位置合わせを単純
化でき容易に精度向上ができると共に、チップ分割後の
複数チップを固着する以前に前取って分割後のチップテ
ストを行なうことができ、ファイナルテストの歩留まり
向上とコストダウンが図れ、かつ、緒特性の均一性のよ
い固体撮像装置を得ることにある。The present invention has been made in view of these points, and its purpose is to simplify the alignment of the assembly and easily improve accuracy, as well as to simplify the alignment of the assembly before fixing multiple chips after dividing the chips. It is an object of the present invention to provide a solid-state imaging device that can perform a chip test after dividing in advance, improve the yield and reduce the cost of the final test, and has good uniformity of initial characteristics.
［問題点を解決するための手段］
このような目的を達成するために本発明は、半導体素子
と此の半導体素子に固着され長辺が半導体素子の長辺よ
り短かく短辺が半導体素子の短辺より長い基台とで構成
されたサブキットをパッケージ基板上の所定の位置に複
数個配列したものである。[Means for Solving the Problems] In order to achieve such an object, the present invention has a semiconductor element, a semiconductor element fixed to the semiconductor element, a long side of which is shorter than the long side of the semiconductor element, and a short side of the semiconductor element. A plurality of subkits each consisting of a base that is longer than its short side are arranged at predetermined positions on a package board.
本発明においては、パフケージ基板にアセンブリする以
前にチップテストが可能であり、チップの良、不良、均
一性のチェックを行なうことができ、所望のチップのみ
を基台状態でハンドリングしながら精度よく所定の位置
に接着することができる。In the present invention, it is possible to test the chip before assembling it on the puff cage substrate, and it is possible to check whether the chip is good, bad, or uniform, and it is possible to accurately place the desired chip while handling it in the base state. Can be glued in position.
本発明に係わる固体１最像装置の一実施例を第１図に示
す。第１図ｔａ）は第４図の１チツプ部に相当する部分
の平面拡大図、第１図（ｂ）は第１図（ａ）の側面図で
ある。An embodiment of the solid-state imaging device according to the present invention is shown in FIG. FIG. 1(a) is an enlarged plan view of a portion corresponding to one chip portion in FIG. 4, and FIG. 1(b) is a side view of FIG. 1(a).
第１図において、２１は半導体素子、２２は半導体素子
２１上の受光部領域、２３は半導体素子上に形成された
パッド、２４は半導体素子２１上のパッド２３と外部回
路とを電気的に接続するための金属配線、２５は基台、
２６はパッケージ基板、２７は内部バンド、２８は複数
個の半導体素子２１を保護するための成形ガラスフタで
ある。In FIG. 1, 21 is a semiconductor element, 22 is a light receiving area on the semiconductor element 21, 23 is a pad formed on the semiconductor element, and 24 is an electrical connection between the pad 23 on the semiconductor element 21 and an external circuit. 25 is the base,
26 is a package substrate, 27 is an internal band, and 28 is a molded glass lid for protecting the plurality of semiconductor elements 21.
基台２５の長辺は半導体素子２１の長辺より短く、基台
２５の短辺は半導体素子２１の短辺より長い。半導体素
子２１と基台２５とは固着されており、この固着された
半導体素子２１と基台２５とをサブキットと呼ぶ。The long sides of the base 25 are shorter than the long sides of the semiconductor element 21, and the short sides of the base 25 are longer than the short sides of the semiconductor element 21. The semiconductor element 21 and the base 25 are fixed to each other, and the fixed semiconductor element 21 and the base 25 are called a subkit.
パッケージ基板２６は複数のサブキットを固着するもの
であり、このパフケージ基板２６上には内部パッド２７
が形成されており、金属配線２４によりパッド２３と内
部パッド２７とが電気的に接続されている。The package substrate 26 is for fixing a plurality of subkits, and internal pads 27 are provided on the puff cage substrate 26.
is formed, and the pad 23 and the internal pad 27 are electrically connected by a metal wiring 24.
第１図に示す装置の電気的動作は、第５図に示す従来の
装置と同様の動作である。The electrical operation of the device shown in FIG. 1 is similar to the conventional device shown in FIG.
なお、上記実施例では、サブキットの基台２５上に内部
パッドがないが、第２の実施例としての第２図（ａｌ、
（ｂｌの装置に示すように、基台２５上に内部パッド
２９を形成し、金属配′１ａ２４で半導体素子２１上の
パッド２３と内部パッド２９．内部パッド２９と内部パ
ッド２７を各々電気的に接続してもよい。このようにす
れば、サブキット状態でのチップテスト時における位置
合わせが容易になる。In the above embodiment, there is no internal pad on the base 25 of the subkit, but as shown in FIG. 2 (al,
(As shown in the device of BL, an internal pad 29 is formed on the base 25, and the pad 23 and the internal pad 29 on the semiconductor element 21 are electrically connected to the internal pad 29 and the internal pad 27 using the metal wiring 1a24. They may also be connected. This will facilitate alignment during chip testing in a subkit state.
また、第１図、第２図に示す実施例は、半導体素子２１
を直線状に配列した例を示したが、特公昭５９−４２５
１１号公報に示すように、千鳥状に配列しても同様の効
果がある。Further, in the embodiment shown in FIGS. 1 and 2, the semiconductor element 21
I have shown an example of arranging them in a straight line.
As shown in Japanese Patent No. 11, a similar effect can be obtained even if the elements are arranged in a staggered manner.
さらに、本実施例では、半導体素子２１上で受光部領域
２２の両側にパッド２３が配置されているため、基台に
おいても２列の内部パッド部分に分かれているが、バン
ド、内部パッドの位置はこれに限定されるものではない
。Furthermore, in this embodiment, since the pads 23 are arranged on both sides of the light receiving area 22 on the semiconductor element 21, the base is also divided into two rows of internal pads, but the positions of the bands and internal pads are is not limited to this.
以上説明したように本発明は、基台と半導体素子を固着
したサブキットをパッケージ基板上の所定の位置に複数
個配列したことにより、ウェハより半導体素子を分離し
た後、容易にチップ選別テストを行なうことができ、フ
ァイナルテストの歩留まり向上、コストダウンおよび緒
特性の均一化が図れる効果がある。さらに、サブキット
の基台に直接触れながら各半導体素子間の位置決めが可
能であるので、位置精度が容易に向上するという効果も
ある。As explained above, in the present invention, by arranging a plurality of subkits in which a base and semiconductor elements are fixed at predetermined positions on a package substrate, a chip sorting test can be easily performed after separating semiconductor elements from a wafer. This has the effect of improving the final test yield, reducing costs, and making the characteristics uniform. Furthermore, since it is possible to position each semiconductor element while directly touching the base of the subkit, the positioning accuracy can be easily improved.
第１図（ａｌは本発明に係わる固体撮像装置の一実施例
を示す平面図、第１図（ｂｌはその側面図、第２図（ａ
ｌは第２の実施例を示す平面図、第２図（ｂｌはその側
面図、第３図はファクシミリ装置の読取装置の一例を示
す説明図、第４図〜第６図は従来の固体撮像装置の構成
を示す説明図である。
２１・・・半導体素子、２２・・・受光部領域、２３・
・・パッド、２４・・・金属配線、２５・・・基台、２
６・・・パッケージ基板、２７・・・内部パッド、２８
・・・成形ガラスフタ。FIG. 1 (al is a plan view showing one embodiment of the solid-state imaging device according to the present invention, FIG. 1 (bl is a side view thereof, FIG. 2 (a)
1 is a plan view showing the second embodiment; FIG. 2 is a side view thereof; FIG. 3 is an explanatory diagram showing an example of a reading device of a facsimile machine; It is an explanatory view showing the configuration of the device. 21... Semiconductor element, 22... Light receiving area, 23...
...Pad, 24...Metal wiring, 25...Base, 2
6...Package board, 27...Internal pad, 28
...Molded glass lid.
Claims (4)
記半導体素子の長辺より短かく短辺が前記半導体素子の
短辺より長い基台とで構成されたサブキットをパッケー
ジ基板上の所定の位置に複数個配列したことを特徴とす
る固体撮像装置。(1) A subkit consisting of a semiconductor element and a base which is fixed to the semiconductor element and whose long side is shorter than the long side of the semiconductor element and whose short side is longer than the short side of the semiconductor element is placed in a predetermined position on a package board. A solid-state imaging device characterized in that a plurality of solid-state imaging devices are arranged at positions.
許請求の範囲第１項記載の固体撮像装置。(2) The solid-state imaging device according to claim 1, wherein the base has an internal pad.
れたことを特徴とする特許請求の範囲第１項記載の固体
撮像装置。(3) The solid-state imaging device according to claim 1, wherein the subkits are arranged in a line on a straight line in the long side direction.
れたことを特徴とする特許請求の範囲第１項記載の固体
撮像装置。(4) The solid-state imaging device according to claim 1, wherein a plurality of subkits are arranged in a staggered manner in the long side direction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61122716A JPS62279671A (en) | 1986-05-28 | 1986-05-28 | Solid state image sensing device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61122716A JPS62279671A (en) | 1986-05-28 | 1986-05-28 | Solid state image sensing device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62279671A true JPS62279671A (en) | 1987-12-04 |
Family
ID=14842825
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61122716A Pending JPS62279671A (en) | 1986-05-28 | 1986-05-28 | Solid state image sensing device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62279671A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020096158A (en) * | 2018-12-12 | 2020-06-18 | 浜松ホトニクス株式会社 | Light detection device |
| WO2020121852A1 (en) * | 2018-12-12 | 2020-06-18 | 浜松ホトニクス株式会社 | Photodetector |
| US11513002B2 (en) | 2018-12-12 | 2022-11-29 | Hamamatsu Photonics K.K. | Light detection device having temperature compensated gain in avalanche photodiode |
-
1986
- 1986-05-28 JP JP61122716A patent/JPS62279671A/en active Pending
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2020096158A (en) * | 2018-12-12 | 2020-06-18 | 浜松ホトニクス株式会社 | Light detection device |
| WO2020121852A1 (en) * | 2018-12-12 | 2020-06-18 | 浜松ホトニクス株式会社 | Photodetector |
| CN113167638A (en) * | 2018-12-12 | 2021-07-23 | 浜松光子学株式会社 | Optical detection device |
| US11513002B2 (en) | 2018-12-12 | 2022-11-29 | Hamamatsu Photonics K.K. | Light detection device having temperature compensated gain in avalanche photodiode |
| US11561131B2 (en) | 2018-12-12 | 2023-01-24 | Hamamatsu Photonics K.K. | Determination method and light detection device |
| US11901379B2 (en) | 2018-12-12 | 2024-02-13 | Hamamatsu Photonics K.K. | Photodetector |
| US11927478B2 (en) | 2018-12-12 | 2024-03-12 | Hamamatsu Photonics K.K. | Light detection device |
| CN113167638B (en) * | 2018-12-12 | 2024-06-11 | 浜松光子学株式会社 | Light detection device |
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