JPS62277732A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62277732A JPS62277732A JP12068986A JP12068986A JPS62277732A JP S62277732 A JPS62277732 A JP S62277732A JP 12068986 A JP12068986 A JP 12068986A JP 12068986 A JP12068986 A JP 12068986A JP S62277732 A JPS62277732 A JP S62277732A
- Authority
- JP
- Japan
- Prior art keywords
- layer
- single crystal
- etching
- groove
- crystal semiconductor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 239000013078 crystal Substances 0.000 claims abstract description 26
- 238000005530 etching Methods 0.000 claims abstract description 21
- 239000000758 substrate Substances 0.000 claims description 30
- 238000000034 method Methods 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 11
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 19
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract description 13
- 229910052710 silicon Inorganic materials 0.000 abstract description 13
- 239000010703 silicon Substances 0.000 abstract description 13
- 238000001020 plasma etching Methods 0.000 abstract description 12
- 229910052681 coesite Inorganic materials 0.000 abstract description 10
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 10
- 229910052682 stishovite Inorganic materials 0.000 abstract description 10
- 229910052905 tridymite Inorganic materials 0.000 abstract description 10
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract description 9
- 239000000377 silicon dioxide Substances 0.000 abstract description 9
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 9
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 239000000126 substance Substances 0.000 abstract 3
- 229910003818 SiH2Cl2 Inorganic materials 0.000 abstract 1
- BLRPTPMANUNPDV-UHFFFAOYSA-N Silane Chemical compound [SiH4] BLRPTPMANUNPDV-UHFFFAOYSA-N 0.000 abstract 1
- 238000007493 shaping process Methods 0.000 abstract 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- 239000003990 capacitor Substances 0.000 description 3
- 230000007547 defect Effects 0.000 description 3
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000000059 patterning Methods 0.000 description 2
- 229910020472 SiO7 Inorganic materials 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
発明の詳細な説明
〔産業上の利用分野〕
本発明は、半導体装ヱの製造方法、特に半導体基体に所
要の溝部を形成する方法に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of forming a required groove in a semiconductor substrate.
〔発明の)既要]
本発明は、単結晶半導体基体の表面に所要の溝部を形成
するに当り、単結晶半導体基体上の溝部を形成する部分
に選択的に該単結晶半導体基体とはエツチング特性の異
なる物質層を形成して後、単結晶半導体基体が露出され
た部分に選択的に単結晶半導体層をエピタキシャル成長
させ、次いで物質層を選択的にエツチング除去すること
によって、単結晶半導体基体表面に形状の良い溝部を形
成するようにしたものである。[Summary of the Invention] The present invention provides a method for forming a desired groove on the surface of a single crystal semiconductor substrate by selectively etching a portion of the single crystal semiconductor substrate where the groove is to be formed. After forming material layers with different properties, a single crystal semiconductor layer is epitaxially grown selectively on the exposed portion of the single crystal semiconductor substrate, and then the material layer is selectively etched away to improve the surface of the single crystal semiconductor substrate. A well-shaped groove is formed in the groove.
近時、半導体集積回路においては、溝部を利用して素子
間分離すること或いは所謂I・レンチキャパシタを形成
すること等が行われている。従来、かかる溝部の形成は
反応性イオンエツチング(RI E)により行っていた
。即ち、第3図A及びBに示すように、単結晶半導体基
体例えば単結晶シリコン基体(1)の表面に選択的にエ
ソチンブレジスl−屓+21を形成して後、反応性イオ
ンエツチングにより基体表面に溝部(3)を形成してい
た。Recently, in semiconductor integrated circuits, trenches have been used to isolate elements or to form so-called I-wrench capacitors. Conventionally, such grooves have been formed by reactive ion etching (RIE). That is, as shown in FIGS. 3A and 3B, an etching layer 21 is selectively formed on the surface of a single crystal semiconductor substrate, such as a single crystal silicon substrate (1), and then the surface of the substrate is etched by reactive ion etching. A groove (3) was formed.
ところで、半導体集積回路の微細化に伴って溝部(3)
の深さを深くする必要があるが、反応性イオンエツチン
グ技術では深いm部を形成する場合に第3図A及びBに
示すように形状が悪くなる傾向がある。さらにイオンが
シリコン面を直接叩くため、溝部(3)の内面にダメー
ジが入る。シリコンを反応性イオンエツチングしたとき
のダメージは大きく、その後の軽い溶液エツチングでダ
メージによる結晶欠陥は除去できない。By the way, with the miniaturization of semiconductor integrated circuits, the groove (3)
However, when forming a deep m section using reactive ion etching technology, the shape tends to deteriorate as shown in FIGS. 3A and 3B. Furthermore, since the ions directly hit the silicon surface, the inner surface of the groove (3) is damaged. Reactive ion etching of silicon causes significant damage, and subsequent light solution etching cannot remove crystal defects caused by the damage.
本発明は、上述の点に鑑み、半導体基体に優れた形状の
溝部を形成できるようにした半導体装置の製造方法を提
供するものである。In view of the above-mentioned points, the present invention provides a method for manufacturing a semiconductor device, which enables formation of a groove portion of an excellent shape in a semiconductor substrate.
本発明は、単結晶半導体基体(1)上の溝部を形成する
部分に、選択的に単結晶半導体基体とはエツチング特性
の異なる物質層(5)を形成し、次に単結晶半導体基体
(1)が露出された部分に選択的に単結晶半導体層(6
)をエピタキシャル成長させて後、物質層(5)を選択
的にエツチング除去して単結晶半導体基体表面に溝部(
7)を形成する。In the present invention, a material layer (5) having etching characteristics different from that of the single crystal semiconductor substrate is selectively formed in a portion of the single crystal semiconductor substrate (1) where a groove is to be formed, and then a material layer (5) having etching characteristics different from that of the single crystal semiconductor substrate (1) is formed. ) is selectively applied to the exposed portion of the single crystal semiconductor layer (6).
) is epitaxially grown, the material layer (5) is selectively etched away to form a groove (5) on the surface of the single crystal semiconductor substrate.
7).
この製法では、半導体基体(11上に選択的に形成した
物質層(5)の形状がそのまま溝部(7)の形状となる
。物質層(5)はパターニングによって厚み方向に均一
な幅をもって形成することができるために、物質層(5
)を選択エツチングで除去した後に単結晶半導体基体表
面には、すぐれた形状の溝部(7)が形成される。また
、物質層(5)を溶液エツチングで除去して溝部(7)
を形成するので、溝部(7)の内面に前述の従来法のよ
うなダメージは入らない。In this manufacturing method, the shape of the material layer (5) selectively formed on the semiconductor substrate (11) becomes the shape of the groove (7).The material layer (5) is formed by patterning to have a uniform width in the thickness direction. In order to be able to
) is removed by selective etching, grooves (7) of excellent shape are formed on the surface of the single crystal semiconductor substrate. Also, the material layer (5) is removed by solution etching to form the groove (7).
Therefore, the inner surface of the groove (7) is not damaged as in the conventional method described above.
以下、図面を用いて本発明による半導体装置の製法の実
施例を説明しよう。Embodiments of the method for manufacturing a semiconductor device according to the present invention will be described below with reference to the drawings.
第1図Aに示すように、単結晶半導体基体例えば単結晶
シリコン基体filの一生面上にシリコンとエツチング
特性の異なる物質層例えば5i02層(5)をCVD
(化学気相成長)法で被着形成する。このときのSiO
2層(51WI後形成しようとする溝部の深さに相当す
る均一な厚みをもって形成する。As shown in FIG. 1A, a material layer (5) having etching properties different from that of silicon, such as a 5i02 layer (5), is formed by CVD on the entire surface of a single crystal semiconductor substrate, such as a single crystal silicon substrate fil.
(chemical vapor deposition) method. SiO at this time
Two layers (formed with a uniform thickness corresponding to the depth of the groove to be formed after 51WI).
次に、第1図Bに示すように5i02層価)を例えば反
応性イオンエツチング(RI E)等の異方法エツチン
グによりパターニングして溝部を形成する部分にのみ厚
み方向に均一な巾をもつSiO2層(5)を残す。ここ
でS io2’PI (5)に対する反応性イオンエツ
チングの場合はシリコン表面へのダメージは少なく、そ
の後の軽い溶液エツチングによりダメージによる結晶欠
陥は除去される。Next, as shown in FIG. 1B, the 5i02 layer is patterned by a different etching method such as reactive ion etching (RIE) to form a SiO2 layer with a uniform width in the thickness direction only in the portion where the groove is to be formed. Leave layer (5). Here, in the case of reactive ion etching for S io2'PI (5), there is little damage to the silicon surface, and crystal defects due to damage are removed by subsequent light solution etching.
次に、第1図Cに示すように、5IH4+ HCflの
混合ガス、またはSiH2σ2+HCl2の混合ガスを
用いて所謂選択エピタキシャル成長を行う。このとき、
HCnを用いるために5i02層(5)上にはシリコン
層が形成されず、従ってS 102Fi (s+のない
シリコン基体(1)上にのみ選択的にシリコン層(6)
がエピタキシャル成長する。Next, as shown in FIG. 1C, so-called selective epitaxial growth is performed using a mixed gas of 5IH4+HCfl or a mixed gas of SiH2σ2+HCl2. At this time,
Due to the use of HCn, no silicon layer is formed on the 5i02 layer (5), and therefore the silicon layer (6) is selectively formed only on the silicon substrate (1) without S102Fi (s+).
grows epitaxially.
次に、第1図りに示すように5i02層(5)を例えば
HFf6液によってエツチング除去し、単結晶シリコン
基体表面に溝部(7)を形成する。Next, as shown in the first diagram, the 5i02 layer (5) is removed by etching with, for example, HFf6 solution to form a groove (7) on the surface of the single crystal silicon substrate.
この製法では、5i02層(5)を反応性イオンエツチ
ングでパターニングするので、厚み方向に均一な幅をも
つ形状の良い5i02層(5)が残る。そして選択エピ
タキシャル成長において、5i02層(5)の側面に沿
ってシリコン層(6)が形成され、その後、5i02層
(5)がエツチング除去されて溝部(7)が形成される
ので、非常に形状の良い溝部(7)が形成できる。また
、5i02層(5)は溶液エンチングで除去されるので
、形成された溝部(7)の内面には、反応性イオンエツ
チングを用いた場合のようなダメージによる結晶欠陥が
発生しない。In this manufacturing method, the 5i02 layer (5) is patterned by reactive ion etching, so that a well-shaped 5i02 layer (5) with a uniform width in the thickness direction remains. Then, in selective epitaxial growth, a silicon layer (6) is formed along the side surfaces of the 5i02 layer (5), and then the 5i02 layer (5) is etched away to form a groove (7), resulting in a very shaped etching. Good grooves (7) can be formed. Further, since the 5i02 layer (5) is removed by solution etching, crystal defects due to damage do not occur on the inner surface of the formed groove (7), unlike when reactive ion etching is used.
一方、例えば4MビットダイナミンクRAMのトレンチ
キャパシタは深さ3〜4μmの溝が必要であるが、第1
図の例でSiO2層(5)をこのように厚く形成するこ
とはむづかしい。第2図はこのようにより深い溝を必要
とする場合に通した製法例である。On the other hand, for example, a trench capacitor for a 4M bit dynamic RAM requires a trench with a depth of 3 to 4 μm.
In the example shown in the figure, it is difficult to form the SiO2 layer (5) so thickly. FIG. 2 shows an example of a manufacturing method used when deeper grooves are required.
先ず、第2図Aに示すように単結晶半導体基体例えば単
結晶シリコン基体(1)の−主面上に、形成すべき溝部
の深さに対応した厚さの多結晶シリコン層(10)を被
着形成する。First, as shown in FIG. 2A, a polycrystalline silicon layer (10) having a thickness corresponding to the depth of the groove to be formed is formed on the main surface of a single crystal semiconductor substrate, for example, a single crystal silicon substrate (1). Adhesion is formed.
次に、第2図Bに示すように多結晶シリコン層(10)
をパターニングして溝部を形成すべき部分にのみ多結晶
シリコン層(10)を残して後、第2図Cに示すように
熱酸化する。この熱酸化工程で多結晶シリコン1(10
)及びシリコン基体(1)の表面が酸化され、5i02
5 (11)となる。Next, as shown in FIG. 2B, a polycrystalline silicon layer (10) is formed.
After patterning the polycrystalline silicon layer (10) to leave only the portion where the groove is to be formed, thermal oxidation is performed as shown in FIG. 2C. In this thermal oxidation process, polycrystalline silicon 1 (10
) and the surface of the silicon substrate (1) are oxidized to form 5i02
5 (11).
次に、第2図りに示すように5i02層(11)をパタ
ーニングして溝部を形成すべき部分の5i02層(11
)を残す。Next, as shown in the second diagram, the 5i02 layer (11) is patterned to form a groove.
).
次いで、第21已に示すようにSi)!4+HCJ!の
混合ガス、または5i8202+H口の混合ガスによる
選択エピタキシャル成長を行い、5i02層(11)以
外のシリコン基体表面に5i02層(11)の厚みと同
程度の厚さの単結晶シリコン層(6)を形成する。Then, as shown in the 21st page, Si)! 4+HCJ! Perform selective epitaxial growth using a mixed gas of 5i8202+H or a mixed gas of 5i8202+H to form a single crystal silicon layer (6) with a thickness similar to that of the 5i02 layer (11) on the surface of the silicon substrate other than the 5i02 layer (11). do.
しかる後、5iO2fi (11)をHF溶液によって
エツチング除去して、基体表面に所要の溝部(7)を形
成する。Thereafter, 5iO2fi (11) is removed by etching with an HF solution to form a required groove (7) on the surface of the substrate.
この例では5i02に代えて厚く形成できる多結晶シリ
コンを用いこれを熱酸化してSiO2とするので、最終
的にエツチング除去されるSiO2層(11)を厚く形
成することができ、深い溝部(7)を形成することがで
きる。In this example, instead of 5i02, polycrystalline silicon, which can be formed thickly, is used and thermally oxidized to form SiO2, so that the SiO2 layer (11) that is finally etched away can be formed thickly, and the deep grooves (7 ) can be formed.
本発明によれば、単結晶半導体基体表面に深く且つ形状
のよい溝部を形成することができる。また溝部の形成に
際して溝部内面にダメージを与えることがな(、結晶性
のよい溝部の形成ができる。According to the present invention, a deep and well-shaped groove can be formed on the surface of a single crystal semiconductor substrate. Further, when forming the groove, the inner surface of the groove is not damaged (and the groove can be formed with good crystallinity).
従って、特に微細化、高集積化した半導体集積回路にお
ける素子間分離用又はトレンキャパシタ用の溝部形成に
適用して好適ならしめるものである。Therefore, the present invention is particularly suitable for forming grooves for isolation between elements or trench capacitors in semiconductor integrated circuits that are miniaturized and highly integrated.
第1図A−Dは本発明による半導体装置の製法の−・例
を示す工程図、第2図A−Fは本発明による半導体装置
の製法の他の例を示す工程図、第3図A及びBは夫々従
来の反応性イオンエツチング法を用いて溝部を形成した
例を示す断面図である。
(1)は単結晶シリコン基体、(5)はS i02層、
(6)は単結晶シリコン層、(7)は溝部、(10)は
多結晶シリコン層、(11)はSiO7層である。
(e埋入 伊)丙 貞
同 松隈秀盛
A B
第3図1A to 1D are process diagrams showing an example of the method for manufacturing a semiconductor device according to the present invention, FIGS. 2A to 2F are process diagrams showing another example of the method for manufacturing a semiconductor device according to the present invention, and FIG. 3A and B are cross-sectional views showing examples in which grooves are formed using the conventional reactive ion etching method. (1) is a single crystal silicon substrate, (5) is a Si02 layer,
(6) is a single crystal silicon layer, (7) is a groove portion, (10) is a polycrystalline silicon layer, and (11) is a SiO7 layer. (e-embedded Italy) Sadado Hei Matsukuma Hidemori A B Figure 3
Claims (1)
記単結晶半導体基体とはエッチング特性の異なる物質層
を形成する工程と、 前記単結晶半導体基体が露出された部分に選択的に単結
晶半導体層をエピタキシャル成長させる工程と、 上記物質層を選択的にエッチング除去して単結晶半導体
基体表面に溝部を形成する工程を有する特徴とする半導
体装置の製造方法。[Scope of Claims] A step of selectively forming a layer of material having etching characteristics different from that of the single crystal semiconductor substrate in a portion of the single crystal semiconductor substrate where a groove is to be formed; and a portion where the single crystal semiconductor substrate is exposed. 1. A method for manufacturing a semiconductor device, comprising: selectively epitaxially growing a single crystal semiconductor layer; and selectively etching away the material layer to form a groove on a surface of a single crystal semiconductor substrate.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12068986A JPS62277732A (en) | 1986-05-26 | 1986-05-26 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP12068986A JPS62277732A (en) | 1986-05-26 | 1986-05-26 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62277732A true JPS62277732A (en) | 1987-12-02 |
Family
ID=14792519
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP12068986A Pending JPS62277732A (en) | 1986-05-26 | 1986-05-26 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62277732A (en) |
-
1986
- 1986-05-26 JP JP12068986A patent/JPS62277732A/en active Pending
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