JPS622750B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a mode display circuit for an audio multiplex receiver, etc., and particularly to a control circuit that generates two or three modes of control output by combining outputs of two states, high and low. An audio multiplex receiver that is connected to the two output terminals of the controller, supplies 2-mode or 3-mode interface output to the controlled circuit, and accurately displays 2-mode or 3-mode with a simple circuit configuration. This provides a mode display circuit for devices such as machines.

For example, in each broadcast reception mode of stereo and dual (bilingual broadcast), such as an audio multiplex receiver, the program can be set in a mode preset by the listener.
That is, stereo, monaural, main, sub,
In order to adopt a configuration that can be heard in each preset mode (main + sub), the audio multiplex signal demodulation
When IC control signals are created by a microcomputer that constitutes a random access type electronic channel selection device, the number of input/output terminal pins of each IC circuit is limited, so an extremely limited number of signals is required. It is necessary to drive the controlled circuit well and to display the operating mode. The present invention provides a mode display circuit for an audio multiplex receiver or the like that can satisfy such requirements.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS The details of the present invention will be explained below with reference to the drawings showing an embodiment in which the present invention is applied to a listening mode display circuit of an audio multiplex receiver.

The figure number (LA) indicates an IC for demodulating audio multiplexed signals. As this IC, we plan to use, for example, an IC manufactured by Tokyo Sanyo Electric Co., Ltd., LA-7751, or an equivalent product.

This IC is equipped with two reception mode identification output terminal pins 16, 17 and three listening mode control input terminal pins 11, 12, and 23, and depending on the received audio multiplexed signal, the reception mode identification output terminal Three state outputs of H (high), (low) and floating are produced at pins 16 and 17 as shown in Table 1. Furthermore, when control signals as shown in Table 2 are applied to the listening mode control input terminal pins 11, 12, and 23, a pair of audio outputs according to the specified mode, that is, main, sub, (main + sub), or The configuration is such that stereo and monaural outputs are supplied to a downstream integrated amplifier (not shown). CG is a random access format PLL
A microcomputer controller that controls the programmable divider (not shown) of the tuning circuit.
This is a control signal generation circuit that can be constructed from part of an IC or MC. This circuit receives and stores listening mode selection signals in the form of touch selection or remote control signals, receives reception mode identification signals at two input terminals I ₁ and I ₂ , and outputs output terminals O ₁ and O ₂ .
Then, control signals as shown in Table 3 are generated. R indicates a remote control transmitter, and S indicates a selection panel.

At that time, the latest listening mode selection signal is always updated and stored, so even if the reception mode changes from stereo to dual to stereo to dual, the latest signal is always output from output terminals O ₁ and O ₂ . A control signal according to the selected listening mode is output.

Next, the interface circuit portion, which is a feature of the circuit of the present invention, will be explained.

This interface circuit is a control signal generation circuit CG consisting of an IC for a microcomputer.
Viewed from the side, it is roughly divided into an input interface circuit IF and an output interface circuit OF.

The input interface circuit IF inverts the 3-state signal shown in Table 1 generated at the output terminal pin 16 of the audio multiplex demodulation IC and LA, and at the same time changes the operating voltage (high level peak value).
A first transistor _T1 functions as a buffer to convert the 12V of the audio multiplexing and demodulation IC LA to 5V of the microcomputer MC and apply it to the second input terminal _IN2 of the microcomputer MC.
Then, the 3-state signal generated at the output terminal pin 17 of the above IC/LA as shown in Table 1 is set to a high level peak.
It is composed of second and third transistors T ₂ and T ₃ that function as a buffer for converting into a 5V signal.

The first transistor _T1 operates in a grounded-emitter type, and serves as the midpoint output of a pair of totem-pole connected transistors (not shown).
The control signal generation circuit uses a 3-state signal as shown in Table 1 generated at pin 16 of LA as a base input.
The high (H) and low (L) two-state signals listed in the "Input I ₂ " column of Table 3 are applied as input to the first input terminal _I 1 of the CG.

The output of the 16th pin is connected to the base of the first transistor _T1 via the voltage dividing resistors _r1 and _r2 with one end grounded, so the floating output generated at the 16th pin is a low level. Processed according to signal L.

The second and third transistors T ₂ and T ₃ are connected in a quasi-complementary manner and operate in a grounded-emitter format. The base of this second transistor _T2 is
_{This transistor T 2}
is turned on by the high level H output and floating level output generated at pin 17 of the above IC and LA. Therefore, the third transistor _T3 that inverts the output of the second transistor _T2 is connected to the first input terminal _I1 of the control signal generation circuit CG as shown in Table 3 "Input
The signals listed in each column of ``I ₁ '' are supplied.

The output interface circuit OF is further divided into a dual output circuit DO and a stereo output circuit SO.

The dual output circuit DO includes fourth and fifth transistors T ₄ and T ₅ for buffering, three LEDs for indicating reception mode, l _M , l _S , l _MS and two switching diodes d ₁ and d. Equipped with ₂ .

The fourth transistor _T4 is connected to the "output voltage" shown in Table 3, which is generated at the first output terminal _O1 of the control signal generation circuit CG.
O ₁ ” is used as the base input, and the inverted output generated at the collector is sent to the audio multiplex signal demodulation IC, LA 1.
Add to pin 1 (dual broadcast reception mode control terminal).

The collector of this fourth transistor _T4 and the power supply Vcc
In between, an LED for indicating "main channel reception mode" and l _M are connected via protective resistors r _M and r ₁₁ , respectively.
and the first switching diode _d1 are connected. Further, the emitter of the fourth transistor _T4 is connected to the collector of the third transistor T3, and the collector-emitter channel is connected to the collector of _{the third} transistor T3.
It is shared as a current path for the LED, _lM , and switching diode _d1 .

Collector of the third transistor _T3 and power supply Vcc
An LED, _LS , for displaying "subchannel reception mode" is connected in series with the protective resistor _RS , and its on/off is controlled by connecting the anode of the LED, _LS and the collector of the fifth transistor _T5 . It is controlled by a switching diode _d2 connected in the forward direction between the two.

The fifth transistor _T5 is connected to the "output" in Table 3, which is generated at the second output terminal _O2 of the control signal generation circuit CG.
O ₂ ' is used as the base input, and the inverted output generated at its collector is applied as a control input to pin 12 (dual broadcast reception mode control terminal) of the above IC and LA. Between the collector of the fifth transistor _T5 and the power supply _Vcc , a "main
_LED for displaying “Subchannel reception mode”.
In the mode in which both the fourth and fifth transistors T ₄ and T 5 are turned on by the switching diode _{d 1} which is turned on when the fourth transistor T ₄ is turned on _, the LED, l Without turning on _{the MS} ,
In the "main + subchannel reception mode" in which the fifth transistor T ₅ is turned on, when the output listed in the relevant column of Table 3 appears at the output terminals O ₁ and O ₂ of the control signal generation circuit CG, only, i.e. the fifth
In the mode in which only the transistor _T5 is turned on, the LED, _lMS, is turned on.

The stereo output circuit SO includes sixth and seventh buffer transistors T ₆ and T ₇ , two LEDs for indicating stereo and monaural reception modes, L _S and L _M
and a switching diode _d3 .

The sixth transistor _T6 shares the second output terminal _O2 of the control signal generation circuit CG, and outputs the "output" generated at the terminal during stereo broadcast reception in Table 3.
_O2 '' as the base input, and its collector output controls the seventh transistor _T7 . The collector output of the seventh transistor _T7 is applied as a control input to pin 23 of the audio multiplex signal demodulation IC.

LED for displaying the stereo reception mode, L _S
is the collector and power supply of the sixth transistor _T6
Vcc is connected in series through a resistor _r13 , and the LED for monaural reception mode indication, L _M , is connected between the power supply Vcc and the emitter of the sixth transistor _T6 with a protective resistor r13. connected in series through ₁₄ . A switching diode _d3 is directly connected between the anode of the latter LED, L _M and the collector of the sixth transistor _T6 , and when the sixth transistor _T6 is conductive, the monaural receiving LED, L _M Turn off, and only the LED for stereo reception display, L _S , lights up.

The emitter of the _sixth transistor T6 is directly connected to the collector of the first transistor _T1 , and its collector-emitter channel is connected to both the LE,
Commonly used for the current return path of DL _M , L _S and switching diode d ₃ .

With such a configuration, in the stereo reception mode, the third output terminal is connected to the output terminal of the control signal generation circuit CG.
When H output occurs as shown in "Output O ₂ " in the table,
Open pin 23 of IC and LA, and set IC and LA to stereo demodulation mode.

Since the present invention has the above-described configuration, the control signal generating circuit receives the three-state signals shown in Table 1 from the IC, LA, etc. for audio multiplexed signal demodulation, and transmits the signals to the control signal generating circuit.
The IC is controlled by the combination of the two-state signals generated at the output terminals O ₁ and O ₂ of the control signal generation circuit CG according to the listening selection mode and reception mode. Since it is possible to operate in three modes and to display the modes, it is possible to provide an interface circuit that can efficiently drive a controlled circuit and display the operation mode using limited signal channels. be.

[Brief explanation of the drawing]

The drawings represent an example of a circuit for implementing the present invention. LA... IC for audio multiplex signal demodulation, MC... Microcomputer, CG... Control signal generation circuit,
IF...Input interface circuit, OF...Output interface circuit.

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Claims (1)

[Claims] 1. Each base is directly connected to two output terminals of a control circuit that generates a three-mode output by a combination of two-state outputs, each emitter is connected to a common flow path, and each emitter is connected to a common flow path. The first and second display devices are provided with first and second display elements as loads between the collector and the power source.
a third display element connected between the power source and the emitters of both the transistors;
when controlled by the first transistor and conductive;
a first switching element forming a bypass circuit of the second display element and a second switching element forming a bypass circuit of the third display element when conductive under the control of the first switching element and the second transistor; A mode display circuit for an audio multiplex receiver or the like configured to supply an interface control output from each collector of the first and second transistors, and to display three modes using the first to third display elements. 2. The audio multiplex receiver according to claim 1, wherein the three modes are modes of main audio listening, sub audio listening, and simultaneous main audio and sub audio listening during dual broadcast reception. etc. mode display circuit. 3. A mode display circuit for an audio multiplex receiver or the like according to claim 1, characterized in that LEDs are used as the first to third display elements.