JPS62274919A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To reduce the noise and stabilize the output level and prevent the malfunction by dividing output circuits into plural groups and dividing output MOSFETs corresponding to a relatively quickly established level into several stages in each group in accordance with the output characteristic of a semiconductor integrated circuit device including these output circuits and setting divided output MOSFETs to the operating state. CONSTITUTION:Eight output circuits DOB0-DOB7 are provided for the purpose of outputting read data by every 8 bits, namely, in byte units. These output circuits are divided into two groups by 4. Timing signals phioel and phioe2 which set N-channel MOSFETs for low level output to the operating state are supplied to the first and second groups of output circuits respectively. An inverted timing sinal phioe' which sets P-channel MOSFETs for high level output to the operating state is supplied to all output circuits. Thus, the variation of the level of the earth potential in circuits due to a leading-in current at the time of low level output and the peak value of the noise are held down though MOSFETs for low level output are divided into two stages and are set to the operating state.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a semiconductor integrated circuit device, and for example, a semiconductor integrated circuit device having a plurality of output circuits that are simultaneously activated. It is related to effective technology that can be used for.

C. Prior Art] Regarding semiconductor integrated circuit devices such as semiconductor storage devices that output read data in units of multiple bits such as bytes, for example, ■Hitachi IC Memory Data Book published September 1985 by Hitachi, Ltd. Pages 307-31 of
It is written on page 1.

[Problems to be Solved by the Invention] For an output circuit in units of multiple bits in such a semiconductor memory device, for example, an I.R.I.C.I. output circuit as shown in FIG. 3 is used as a unit circuit. . In other words, as typified by the output circuit DOBO,
A so-called high-level output P-channel MOSFET QI is provided between external output terminal 1) 0 and the circuit power supply voltage, which makes the output potential of the external output terminal DO a high level like the power supply voltage Vcc. A so-called low-level output N-channel MOSFET Q3 is provided between the output terminal Do and the ground potential of the circuit, which sets the output potential of the external output terminal DO to a low level similar to the ground potential of the circuit. MOS F' ET Q] is turned on when both the inverted timing signal T and the inverted read signal n10 are at low level, and the MOS
FETQ3 is turned on when the inverted timing signal TARE is at a low level and the inverted read signal TARE is at a high level.

Since a relatively large load capacitance existing in the output signal line is coupled to such a conventional output circuit, as the speed of semiconductor built-in circuits including the circuit becomes faster, the size of the output MOS FET as described above has increased. There is a tendency to increase the conductance, that is, the on-resistance, and to reduce the on-resistance. For this reason, especially in a semiconductor integrated circuit device having a plurality of output circuits that are activated at the same time, a plurality of output MOS F
The simultaneous operation of the ETs causes sudden changes in current in their power supply voltage lines and ground potential lines. This change is particularly noticeable in the ground potential line, and when the output MO3FE'1' for low level output such as MOSFET Q3 in Fig. 1 operates simultaneously, a peak current flows to the ground potential of the circuit, causing fluctuations in the ground potential and noise. Cause.

That is, multiple output MO5F such as MOSFETQ3
Ground potential line GN I) to which the sources of ET are commonly connected
, there are parasitic resistance R3 due to wiring within the chip or bonding wires, and parasitic inductances l and s. Output MOSFE with large conductance
With the relatively large current change due to the simultaneous operation of T, a voltage drop or a reverse voltage due to the ground current occurs across the parasitic resistance R8 and the parasitic inductances l and s. This causes the level of the ground potential of the circuit to fluctuate, generating noise on the ground potential line and causing malfunctions of input circuits and the like disposed close to the output circuit.

In order to deal with this, the above output circuits are divided into multiple groups, and the above timing signal T product is supplied to each output circuit group as multiple timing signals with time differences, so that multiple output circuits can be divided into several stages. One possible method is to divide the state into operating states.

However, when such a method is adopted, the access time of a semiconductor memory device, etc. including an output circuit is reduced by the time required for all the operations of the output circuit divided into multiple stages to be completed.
It becomes long.

An object of the present invention is to provide a semiconductor integrated circuit device having an output circuit that reduces noise and stabilizes the output level without sacrificing operating speed.

The above and other objects and novel features of this invention include:
It will become clear from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows. That is,
Divide the output circuit into multiple groups, and divide the output circuit into MOSFETs for high level output and MOSFETs for low level output.
A timing signal is provided for specifying the operation timing of each ET, and depending on the output characteristics of the semiconductor integrated circuit device including these output circuits, one of the timing signals is commonly supplied to all the output circuits, and the other one is commonly supplied to all output circuits. one is a plurality of timing signals each formed with a time difference,
The output circuit is supplied to each of the plurality of divided groups of the output circuits.

[For production]

According to the above-mentioned means, the output MO5FIET corresponding to the level that is established relatively quickly is divided into several stages and put into an operating state according to the output characteristics of the semiconductor integrated circuit device including the output circuit. output MOS
Because it is possible to suppress fluctuations in the power supply voltage line or ground potential due to the simultaneous operation of FETs, it is possible to reduce noise and stabilize the output level without increasing the access time of semiconductor integrated circuit devices. A semiconductor integrated circuit device having a circuit can be realized.

〔Example〕

FIG. 1 shows a circuit diagram of an embodiment of a tri-state output circuit of a semiconductor memory device to which the present invention is applied. Each circuit element in the figure is formed on a semiconductor substrate such as, but not limited to, N-type single crystal silicon using a known CMO3 integrated circuit manufacturing technique. In the figure, a MOSFET with an arrow added to its channel (back gate) portion is a P-channel type, and is distinguished from an N-channel MOSFET without an arrow added.

A P-channel MOSFET consists of a source region formed on the surface of a semiconductor substrate, a train region, and a polygon film formed on the semiconductor substrate surface between the source region and the train region with a thin insulating film interposed therebetween. It consists of a gate electrode made of silicon. The N-channel O3FET is formed in a P-type well region formed on the surface of the semiconductor substrate. Thereby, the semiconductor substrate constitutes a common substrate gate for a plurality of P-channel MOSFETs formed thereon. The P-type well region constitutes the substrate gate of the N-channel MO3FE'r formed thereon. The substrate gate, ie, the semiconductor substrate, of P-channel MO31·'ET is coupled to power supply voltage Vcc. Further, the expanded gate of the N-channel O3FET, that is, the P-type well region, is coupled to the ground potential of the circuit.

Although not particularly limited, the semiconductor memory device of this embodiment outputs read data in units of 8 pins, that is, in units of bytes, and therefore has 8 output circuits DOBO to DOB.
7 is provided. These output circuits are divided into two groups of four circuits each, and the first group is the output circuits DOBO to DOB3.
, the second group is composed of D0134 to 1) OB 7, respectively. The first group of output circuits is supplied with a timing signal φoel for activating the N-channel O3FET for low level output, and the second group of output circuits is similarly supplied with a timing signal φoe2. . Further, all the output circuits are commonly supplied with an inverted timing signal for activating the P-channel MO5FET for high-level output. In semiconductor storage devices,
The read speed for logic "1" and logic "0" data tends to differ depending on the operating characteristics of the read circuit, sense amplifier, etc. In the semiconductor memory device of this embodiment, its output characteristics are designed according to the "1" rule, that is, the read speed of logic "0" data is faster than the read speed of logic "1", so the access time is is defined by the read speed of logic "1" data. Therefore, as mentioned above, even though the MO5FET for low level output is activated in two stages, its access time is not affected, and the level of the ground potential of the circuit changes due to the current drawn during low level output. The peak value of noise is suppressed.

In FIG. 1, the inverted timing signal E7' is an internal timing signal generated by a timing control circuit (not shown), and changes from high level to low level at the timing when the read data of logic "0" becomes valid. This inverted timing signal Eφoe is inverted by an inverter circuit N1 to form a timing signal φoel for activating the low level output MOSFETs of the first group of output circuits. timing signal φoel
is the NAND of the output circuits DOBO to DOB3 of the first group.
AND) Chi 1 - is supplied to one input terminal of the circuit NAGl, and is also supplied to the inverters [8N 6 to N7. Inverter circuits N6 to N7 are constituted by MOSFETs having relatively small conductance, and thereby act as delay circuits DL. Inverter circuit N
The delay circuit IJL consisting of 6 to N7 forms a timing φoe 24- delayed by a set delay time '1'd with respect to the timing signal φoel. This timing signal φoe2 is the output bM path IJOB4 to DOB of the second group.
7 is supplied to one input terminal of the NAND 1-circuit NAG2, and is also supplied to the inverter circuit N8.

Inverter circuit N8 inverts timing signal φoe to form an inverted timing signal i. This inverted timing signal Eτ is applied to all output circuits.

BO~DOB7 NOR Day 1-Circuit N.

It is commonly supplied to one input terminal of G1 or N0G2.

The other input terminals of the NOR gate circuit N0G1 and the NAND gate circuit NAG1 or the NOR gate circuit N0G2 and the NANT gate circuit NAG2 of each output circuit are connected in common, and the corresponding inverted readout signals τ1 to 7 are connected in common.
1 is supplied respectively. These inverted readout signals π
.tau.go to (7)go are set to high level when the data read from the memory cell of the corresponding bit is logic "0", and are set to low level when the data is logic "1".

From the above, the output signal of the NOR gate N0G1 or NOG2 of the output circuits DOBO to DOB7 is at a low level when the inverted timing signal poe is at a low level and the inverted readout signal signal DoO to Do7 of the corresponding bit is at a low level, that is, logic "1". , is considered to be at a high level. Furthermore, when the timing signal φoel is at a low level and the inverted read signals T7 to W at the corresponding bits are at a high level, that is, logic "0", the output signal of the output gate NAG1 of each output circuit of the first group becomes low level. be done. Similarly, the output No. 18 of NAG2 of each output circuit of the second group is output when the timing signal φoe2 is at a low level and the inverted readout signal of the corresponding bit is at a high level, that is, logic "0". , is considered to be low level.

Power supply voltage Vcc of each output circuit and circuit ground potential line GND
There is a P-channel type output MOFETQI between
(or G2) and N-channel type output MOSF
ETQ3 (or G4) is provided in series configuration.

The drains of the commonly connected MOSFETs Ql and G3 (or G2 and G4) are connected to corresponding external output terminals DO to D7. Output MOSFET QI
(Or, for the gate of G2, Noah gate N0G1
(or the inverter circuit N2 of the output signal of N0G2>
(or N4) is supplied. Therefore, when the output signal of the inverter circuit N2 (or N4) is at a low level, that is, when the inverted timing signal poe is at a low level, MOSFET QI (or G2) is turned on if the corresponding readout signal LO-Do7 is at logic "1". Thus, a high-level output voltage such as the power supply voltage Vcc is supplied to the corresponding output terminal Do-D7.

On the other hand, the gate of the output MOSFET Q3 (or G4) is connected to the Nant gate NAGI (or NAG2
) is supplied with an inverted signal from an inverter circuit N3 (or N5). Therefore, the output MOSFET Q3 of each output circuit of the first group is connected to the inverter circuit N3.
The output signal of is high level, that is, the timing signal φo
When el is low level, the corresponding read signal DoO
If ~Do3 is at a high level (logic "0"), it becomes an on state, and a low level output voltage such as the ground potential of the circuit is supplied to the corresponding output terminal DO~D3.

Similarly, when the output signal of the inverter circuit N5 is at a high level, that is, when the timing signal φoe2 is at a low level, the output MOSFET Q4 of each output circuit of the second group has a high level (logical " 0”), it becomes an on state, and the corresponding output terminal D
A low level output voltage is supplied to D4 to D7.

FIG. 2 is a timing chart showing an example of signal waveforms at each part in the output circuits DOBO to DOB7 of FIG. 1. As described above, the semiconductor memory device of this embodiment is designed so that its output characteristics conform to the "1" rule. Therefore, as shown in FIG. 2, the read signal DoO-D
o7 starts from an address signal or chip selection signal C5 (not shown), and is established at a timing in which a rising change occurs when reading logic "0" data and a falling change occurs when reading logic "1" data.

The inverted timing signal Eφoe changes from high level to low level at the timing when the read signal DoO~007 is established when reading this logic "O" data. Therefore, this inverted timing signal Btpoe
The low-level output signal DO-D3 (LL) of the first group of output circuits, which is output in synchronization with the timing signal φoel obtained by inverting the signal φoel by the inverter circuit N1, converts into a high-impedance state jlJ(z
is established to a low level like the ground potential of a circuit.

Further, the timing signal φoe2 supplied to the output circuits DOB4 to DOB7 of @2# is the timing signal φ
oel is formed with a delay of the set delay time Td of the delay circuit DL. Therefore, the low-level output signals D4 to D7 (L2) of the second group of output circuits output in synchronization with this timing signal φoe2 are the read signals Do4 to Do7 corresponding to the output signal DO-03. Even though it is output from the memory cell at the same time as =IJo3, it is established at a relatively late timing from the high impedance state Hz to a low level like the # ground potential of the @ path.

On the other hand, an inverted timing signal chamber commonly supplied to all output circuits DOBO to DOB7 is formed by inverting the timing signal φoe2 using an inverter circuit N8. The fall timing of this timing signal T product is set to the timing at which the read signals DoO-Do7 are established when reading the above-mentioned logic "1" data. Therefore, the high level output signal DO-07 (l(2)) of all the output circuits output in synchronization with this inverted timing signal i is similar to the low level output signals D4 to D7 (L2) of the second group. , is established at a relatively late timing from a high impedance state hHz to a high level such as the circuit power supply voltage Vcc.

From the above, when the MO3F series 1 for low level output are turned on all at once, the ground potential line GND of the circuit
As shown in FIG. 2, the peak current generated in φoel and φoe2 is distributed twice by timing signals φoel and φoe2. The current peak value ip at this time is approximately one-half of the current peak value + po when all the MOSFETs for low level output are brought into operation at the same time without operating in two stages. Malfunctions of semiconductor storage devices and the like due to such noise signals largely depend on the magnitude of the peak current value, and most malfunctions can be prevented by halving the peak current.

In addition, as mentioned above, the output characteristics of semiconductor storage devices, etc.
Depending on the operating characteristics of the readout circuit, sense amplifier, etc., there is a tendency for either the readout speed of logic "1" or logic "0" data to be faster. In this case, the access time of such a semiconductor memory device is defined by the slower data readout speed. As in this embodiment, the read speed of logic "0" data is the same as that of logic.

l” faster than the data read speed, so-called “1”
By designing the semiconductor memory device according to the law and dispersing the output timing of the logic "O" data read signal within the difference in data read speed, the access time of the semiconductor memory device will not become longer.

As shown in the above embodiment, when the present invention is applied to an output circuit of a semiconductor integrated circuit device such as a semiconductor memory device, the following effects can be obtained.

That is, (1) The output circuits are divided into a plurality of groups, and the output MO8FI! corresponds to a level that is established relatively quickly according to the output characteristics of the semiconductor integrated circuit device including these output circuits. , T
By dividing each group into several stages and setting them in an operating state, it is possible to suppress fluctuations in the power supply voltage or ground potential due to simultaneous operation of the output MOS FETs at the above level.

(2) The division operation described in the above ('') is performed within the time difference in which the output characteristics of the semiconductor integrated circuit devices and the two levels of the read signal are respectively established, so the access of these semiconductor integrated circuit devices is Affects time
-j without changing the power supply voltage or connection Il! l! The effect of being able to suppress the fluctuation of the dragon position is fH.

(3) A semiconductor integrated circuit device having multiple output circuits that reduces noise, stabilizes the output level, and prevents malfunctions without increasing access time, according to the above ft1 and (2) terms. This has the effect of realizing the following.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that this invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. Nor. For example, the output circuit in Figure @1 is a P-channel MOSFET QI or Q2
Instead, an N-channel MOSFET may be used, and the signals output simultaneously may be other than 8 bits. In this embodiment, the operation timing λ of the low-level output MOSFET is divided, but if the peak current of the power supply voltage line is more of a problem, the output characteristics of the semiconductor integrated circuit device should be set to the "0" rule. By dividing the operation timing of MO5FET for high level output,
It may also be possible to suppress fluctuations in the power supply voltage. In addition, in this embodiment, the output circuit is divided into two groups, but by dividing the output circuit into more groups and forming operation timing signals corresponding to each group, it is possible to It is also possible to lower the current even further. Various embodiments can be adopted, such as the specific circuit configuration of each output circuit and the configuration of delay circuit II)L.

The above explanation has mainly been about the case where the invention made by the present inventor is applied to the output circuit of a semiconductor memory device, which is the background field of application, but the invention is not limited to this. It can also be used in gate arrays with circuits and various microcomputers.

The present invention is applicable to a semiconductor integrated circuit device having a plurality of output circuits that are activated at least simultaneously.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, the output circuits are divided into a plurality of groups, and output MOSFs corresponding to levels that are established relatively quickly according to the output characteristics of the semiconductor integrated circuit device including these output circuits are divided.
By dividing the ET into several stages for each group and putting it into operation,
It is possible to suppress fluctuations in the power supply voltage or ground potential due to simultaneous operation of the output MOS FETs mentioned above, and reduce noise without increasing access time.
It is possible to realize a semiconductor integrated circuit device having a plurality of output circuits that stabilizes the output level and prevents malfunctions.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of a tri-state output circuit to which the present invention is applied, FIG. 2 is a timing diagram for explaining the operation of the tri-state output circuit of FIG. 1, and FIG. 1 is a circuit diagram showing a conventional tri-state output circuit. DOBO~DOB? ...output circuit, DL...delay circuit. Q1~Q2...P channel MOSFET. Q3~Q4...N Nayan FET MO5FET, N0GI
-NOG2...Nor gate circuit, NAG1~NAG2
...Nant gate circuit, N1 to N8... Inverter circuit, Rs... Parasitic resistance, Ls... Parasitic inductance. Figure 1 Figure 2 "n" Figure 3

Claims (1)

[Claims] 1. Provided between the output terminal and the first voltage terminal, the first
a first output MOSFET that is turned on at one level of the corresponding output data according to the timing signal;
a plurality of output circuits including a second output MOSFET provided between the output terminal and the second voltage terminal and turned on at the other level of the corresponding output data according to the second timing signal; one of the first or second timing signals is commonly supplied to the plurality of output circuits, and the other is supplied to each of the plurality of divided groups of the plurality of output circuits with a time difference. A semiconductor integrated circuit device comprising a plurality of timing signals. 2. The first output MOSFET is a P-channel MOSFET provided between the output terminal and the circuit power supply voltage.
The second output MOSFET is an N-channel MOSFET provided between the output terminal and the ground potential of the circuit.
The first timing signal is output from the first output MOS at a level where the output data is logic "1".
The FET is turned on, and the second timing signal is
2. The semiconductor integrated circuit device according to claim 1, wherein said second output MOSFET is turned on at a logic "0" level of said output data. 3. The second timing signal is composed of a plurality of timing signals each having a time difference, and the first timing signal is the second timing signal that is the most 3. The semiconductor integrated circuit device according to claim 1, wherein the semiconductor integrated circuit device is formed substantially in synchronization with a timing signal that is formed with a delay. 4. The above semiconductor integrated circuit device has a readout speed of
Specified in the read operation of logic “1” data,
4. A semiconductor integrated circuit device according to claim 1, 2, or 3, wherein the semiconductor integrated circuit device is a semiconductor memory device having characteristics of the "1" rule.