JPS62274789A - Optical and electronic integrated circuit and manufacture thereof - Google Patents

Abstract

PURPOSE:To enable manufacture of an optical and electronic integrated circuit suitable for a high speed, high reliability and high integration by a method wherein a hetero junction bipolar transistor (HBT) element is manufactured according to the ion implantation method to an epitaxial substrate for double hetero laser. CONSTITUTION:An n<+> type GaAs layer 2 to be used as the emitter electrode of an HBT is formed on a semiinsulating GaAs substrate 1. A first semiconductor layer 3 consisting of n-type wide gap AlxGa1-xAs (0<x<1) is used as the clad layer of a laser diode (LD) and as the emitter layer of the HBT. A second semiconductor layer 4 consisting of a p-type GaAs or p-type narrow gap AlyGa1-yAs (x>y) is the part to be used as the active layer of the LD, and at the same time, to be used also as the base layer of the HBT. A third semiconductor layer 5 consisting of p-type wide gap AlxGa1-xAs is the part to be used as the clad layer of the LD and to be used as the collector layer of the HBT. A p<+> type GaAs cap layer 6 is provided for realization of low resistance ohmic contact, and an insulating region 7 for interelement isolation, a p<+> type region 8 formed in high carrier concentration and a region 9 inverted to an n-type are provided.

Description

Detailed Description of the Invention 3. Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a third opto-electronic integrated circuit used as a transmitter for optical communication capable of high-speed modulation and a method for manufacturing the same. It is something.

(Problems to be solved by the prior art and the invention) In order to increase the speed and reliability of optical transmitters, it is necessary to integrate the semiconductor laser and the elaborate electronic elements that drive and modulate it on the same substrate. method, so-called opto-electronic integrated circuit (hereinafter referred to as 0EIC)
It is effective to employ the molecule 9.

An example of this simple QEIC is the report by Shibata et al.
? A report by J.K. et al. (A.
ppl, Phys, Lett, 37(2), 19
80).

Among these, Shibata et al.'s IC first forms a multilayer epitaxial film used as an L relay laser diode (hereinafter referred to as LD) using the liquid phase epitaxial growth method, and then forms a portion of this multilayer epitaxy cell film other than the LD. The entire layer is removed, and a buried layer for burying the cleaning layer formed by the removal is grown again by liquid phase epitaxial method. In this case, this buried layer has a t-npn structure, and a heterojunction bipolar transistor (hereinafter referred to as HBT) t-
It is unique in that it is manufactured.

However, this process of growing multilayer epitaxial films for LDs and HBTs in two steps has problems as a method of manufacturing integrated circuits, such as complicating the process and reducing yield.

Furthermore, since it is used as a fully buried layer of a multilayer epitaxial film for HBT, it has the disadvantage that it is difficult to satisfy the conditions for the epitaxial cell layer suitable for HBT operation.

Next, the structure of the t-element proposed by Jie Kaat et al. is shown in FIG. 3, and all the problems with this element will be explained below.

FIG. 3 shows the structure shown in the above report, in which a first layer of n-AlGaAs 21 and a second layer of p-GaAs are formed on a tfl ri''-GaAa substrate from the substrate side.
22. Grow the third layer n-AtGaAg 23 epitaxial Ila and fabricate the HBTt made of npnl structure, and add Be ions to the third layer p-GaAs 2
By implanting up to 2, n -At0aAs of the third layer n
A device has been devised in which a part of the LD is changed to all p-type 24, so that it can also be operated as an LD having an npp structure. However, such a structure has the following two drawbacks.

(a) First, in this device, contact with the base layer is made, Be ions are implanted into the emitter layer n, and a p-type inertial region 24i is provided within the n-type emitter 1m23. A leakage current flows between the base 22 and the emitter n throughout.

(b) Since the base layer 22 of the HBT is also used as the active layer of the LD, it is necessary to prevent light absorption by free carriers, so the carrier concentration of this layer is set to be high (≧5×10I″c).
On the other hand, the operating speed of HBT is given by Cc (collector capacity weight), which is a guideline for HBT operation speed, which indicates that the speed increases as the base resistance decreases. . Therefore, with the structure of Kaatsu et al., in which the base resistance cannot be sufficiently reduced, it is difficult to create a device capable of high-speed operation.

Since an f9n+ substrate is used and the bottom surface of the substrate is used as the collector electrode, the collector displacement Cc is large. Finally, as can be seen from the hole in fo's table above, it can be said that this structure is not suitable for increasing the speed of HBT.

(ii) Since the collector electrode is on the bottom surface of the substrate, separation between elements and wiring are difficult, making the structure unsuitable for integration.As explained above, both Shibata et al.'s device and Kaatsu et al. It can be said that there is a problem in terms of integration. (The tth means to solve all problems)
If the epitaxial film for LD and LD is grown in two separate steps, the process becomes complicated and the yield decreases.0 (0) It is difficult to realize epitaxial conditions suitable for improving the performance of HBT and LDG.

C → A sentence structure suitable for integration cannot be obtained due to isolation between elements, wiring, etc.

Our goal is to provide multiplication tables and electronic integrated circuits that are fast and suitable for integration.

In order to achieve all of the above objects, the present invention includes a first conductivity type wide gap first semiconductor layer, a second conductivity type wide gap semiconductor layer, and a second conductivity type wide-gap semiconductor layer on a semi-insulating substrate.
A narrow-gap second semiconductor layer of conductivity type 1-1 and a third semiconductor layer of wide-gap conductivity type are sequentially laminated.
A double hetero injection laser is constructed in a first region within the multilayer epitaxial film, with the second semiconductor layer 41 as an active layer and the first and third semiconductor layers as cladding layers. In the region of 7, the first semiconductor layer is the emitter, the first conductive type impurity region formed mainly in the third semiconductor layer is the collector, and the second semiconductor layer is sandwiched between the emitter and the collector as the king. The gist of the invention is an opto-electronic integrated circuit characterized in that a heterojunction bipolar transistor based on a region is constructed.

Furthermore, the present invention provides a semiconductor layer having a wide gap of the first conductivity type, a narrow gap second semiconductor layer of the second conductivity type, and a third semiconductor layer of the wide gap of the 22nd conductivity type on a semi-insulating substrate. All the semiconductor layers are sequentially stacked to form a multilayer epitaxial i.
forming a double hetero injection type laser in which the second semiconductor layer is an active layer and the first and third half-quaternary layers are cladding layers in a first region of a multi-no epitaxy cell pIA circle; In the second region within the multilayer epitaxial film, the third
A first conductivity type impurity region is formed in the third semiconductor layer using an ion implantation method, and the first conductivity type impurity region is formed in the third semiconductor layer as an emitter and a collector as soon as it is formed in the third semiconductor layer. 21! of an opto-electronic integrated circuit characterized in that it constitutes a heterojunction bipolar transistor mainly sandwiched between an emitter and a collector in a second semiconductor layer and based on a region 7! ! The gist of the invention is a method of transmitting data.

However, the features of the invention are as follows: (a) It is used as an epitaxial layer for an NPP type multilayer structure grown on a semi-insulating substrate. This is an extremely simple and easy-to-manage LDK structure as well as an epitaxial conversion for 0EIC.

(b) Regarding the J HBT, the conductivity (p-type) of the epitaxial top layer is partially reversed by ion implantation, and it is manufactured in the part where the npnp structure is formed. The ninth advantage of using the ion implantation method is that it is possible to do high-concentration doping (≧IX 10"on-') in the base region, which is essential for increasing the speed of devices.・It is an up type, and the emitter-base junction is formed during epitaxial growth and uses the pn junction as it is.As a result, there is less damage from ion implantation to the emitter-base junction, and carrier recombination at the interface is improved. = avoids deterioration of emitter injection efficiency,
Good HBT operation can be realized. -The function of the collector is to extract the carriers that are injected into the base layer, so it is sufficient to have sufficient reverse breakdown voltage.For this reason, the pn junction between the base and collector is formed by ion implantation. There is no problem in terms of device operation.

(c) Since a semi-insulating substrate is used, isolation between elements and wiring can be easily and reliably performed. At the same time, since the LD and HBT are electrically separated by the semi-insulating substrate, the capacitance of the entire confectionery can be reduced, allowing high-speed operation of the device.

Next, an embodiment of the non-invention will be explained with reference to the attached drawings. 0 Will it be implemented? lIf'X, this is just one example, and it is not intended that various changes and improvements may be made without departing from the spirit of non-invention.

(Example 1) Fig. 1 shows the first implementation of the present invention? lJ t-show. The LD is provided on the left side of the figure, and the HBT element is provided on the right side. In this example, the material is KGa
The case where As-based material is used is shown.

Next, a wedge structure of a non-example will be explained. 1 semi-insulating Ga
The layer 2 on top of the As substrate is an n''-GaAs layer that serves as the emitter of the IBT. Although this layer is not necessary in principle, n-AlGaAs and n-GaAs are also used.
As is the ninth material that can provide better ohmic contact, especially when it is provided. 3 is. Type wide gap At, Ga
1-. ．． As (0< x < 1) L first
This part is the LD cladding t-s, -x
and becomes the emitter layer of the HBT. 4 is p-GaAs or Hp type narrow gap AtGa1-.

AsCx>y) This is the second semiconductor layer that becomes the active node of %LD, and is also used as the base layer of the HBT. Here, the type of x>y is AlGaA
This is because the bandgap of s widens with the type of AL composition. 5 is p-type wide gap AZJGa 1-
This is the third semiconductor layer called Js, which is the cladding layer of the LD and the collector layer of the HBT. (however,
It is necessary to perform ion implantation in the part used as the collector of the HBT (up to the vicinity of the boundary between 4 and 5). 6 is p"
- A GaAs cap layer, which, like 2, is required in principle, but is provided as a filler to realize a low-resistance ohmic contact. 7 is an insulating region for isolation between elements. 8 is a p+ region with high carrier concentration, H13T
This is provided to reduce the internal base resistance. 9 is S
In addition to the above examples, as a combination of wide gap semiconductor/narrow gap semiconductor, InP/InGaAsP,
It is also possible to apply to AjGaAsSb/Garb, etc.

Note that the semiconductor layers 3 and 5 are InP, and the semiconductors 1-4 are InG.
In the figure, b, c, and e are the bases of the HBT, respectively.

Collector, emitter electrode, a, la! C shows the electrodes of each LD.

Next, the manufacturing method will be explained.

First, an n''-GaAs layer 2 is formed on a semi-insulating GaAs substrate 1. Next, a wide-gap first semiconductor 113 is formed on the n-At, Ga1-, As (0(x
(1) is formed. On this layer, a narrow gap second semiconductor IWI 4 of p-GaAs or U p-At is applied.
yGa tym (x>y). Next, a wide gap third semiconductor layer 115 is placed on top of this node.
-At□Ga1-Air As is formed, and then p
A GaAs layer 6 is formed to form a multilayer epitaxial structure.The semiconductor layers 5 and 6 are etched to have a convex shape.

In the first region (left side of the figure) in this multilayer epitaxial film, a second semiconductor/im4'e active layer, a first and a third
The laser consists of a double heteroinjection with semiconductor layers 3 and 5 as cladding layers, respectively.
In AA), Be and Zn are contained in the third semi-coherent layer 5.
A p-type impurity ion such as ion is implanted to increase the carrier concentration and form a 9p+ trap region 8. Impurity # degree is 2 x 10
'/cm'' is appropriate.Here, the implantation is performed in the p-type base layer 4.
Inject until the depth is reached, and control it so that it does not go any deeper.

Next, impurity ions such as Si and S are implanted into the approximately central region of the layer 8 to invert it to n-type and form a region 9.
Semiconductor N3 is emitter, dust region 9 is collector, semi-integrated layer 4
A heterojunction bipolar transistor has a base region sandwiched between an emitter and a collector.

Next, ions such as B and H are implanted to form insulating regions 7 for isolation between elements, and electrodes are formed on the LD and HBT, respectively.

(Embodiment 2) FIG. 2 shows a second embodiment of the present invention. The difference from Embodiment 1 is that) the implantation of p-type impurity ions into the base region of the IBT is omitted, and only the collector portion is formed by ion implantation. n n”-Ga
Ag layer, 3 is n-A of the first semi-coherent layer of wine gap
t-work Ga1-, As % 4 is the second narrow gap
p-GaA, s (also a AL, Ga
1-, Ag), 5 is a wide-gap third semi-coherent layer P-AtxG'1-zAa, 6 is a p''-GaAs layer, and the semi-coherent layers 3 and 4.5 constitute an LD.9 is the ion implantation nm region, the semi-coated layer 3 is an emitter, and the semi-coated layers 4 and 5 are
The base is completely formed in the n-phase region 9, and the collector is completely formed in the n-phase region 9.) (BTk is formed in this structure.) This structure has a higher base resistance than in Example 1, which is disadvantageous for high-speed operation, but the ion implantation process Since it is simple and simple, there is an advantage that manufacturing of 0EIC is easy and yield is improved.

(Effects of the Invention) As described above, according to the present invention, (4) an epitaxial substrate for a double hetero laser.

By manufacturing the HBT resistor using the ion implantation method, it is possible to manufacture an 0EIC suitable for high speed, high reliability, and high integration. This OE and IC device has the effect of being suitable for use as an elementary optical transmitter for optical communications.

(b) As the epitaxial film, an npp type polygonal film grown on a semi-insulating substrate is used. This has a structure suitable for LDK, and is extremely simple and easy to manufacture as an epitaxial film for 0EIC.

Regarding HHBTK, the conductivity (p-type) of the epitaxial top layer is partially reversed by using ion implantation method to form np
n structure is formed and manufactured on the skin part. By using the ion implantation method, it becomes possible to dope the base region at a high concentration (≧IXIO"crn-"), which is necessary for increasing the speed of the device.

2) Since a semi-insulating substrate is used, separation and wiring between elements can be easily and reliably performed. At the same time, since the LD and HBT are electrically isolated by the semi-insulating substrate, the capacitance of the entire device can be reduced, so that the device can operate at high speed.

(E) For the above, set the F cutoff frequency to l G H
It can be made higher than z.

(f) Furthermore, the threshold current can be lowered to about 10 mA.

It has the following effects.

[Brief explanation of drawings]

FIG. 1 is a top view of the first embodiment of the present invention, FIG. 2 is a sectional view of the second embodiment of the invention, and FIG. 3 is a monolithic integration of a laser diode and a heterojunction bipolar transistor. For example, I will show you one proposed by Jie Kaatsu et al. 3...Tenth semiconductor layer 4...Second semiconductor layer 5...Third semiconductor I- Patent applicant Nichifu Telegraph and Telephone Co., Ltd. Figure 1 Figure 2 Figure 3 n-AlxGO5zAS ++
+210°GaAs each a −,
,20;shi77

Claims (14)

[Claims] (1) A first conductivity type wide-gap first semiconductor layer, a second conductivity type narrow-gap second semiconductor layer on a semi-insulating substrate.
A second semiconductor layer is placed in a first region of a multilayer epitaxial film in which a wide gap semiconductor layer of a second conductivity type and a wide gap third semiconductor layer of a second conductivity type are sequentially stacked. A double-hetero injection laser is constructed with a cladding layer of
The semiconductor layer is the emitter, the impurity region of the first conductivity type formed mainly in the third semiconductor layer is the collector, and the base is mainly the region sandwiched between the emitter and collector in the second semiconductor layer. An optical/electronic integrated circuit characterized by being composed of transistors. (2) The opto-electronic integrated circuit according to claim 1, wherein the base has a second conductivity type high concentration impurity region on the collector side. (3) The opto-electronic integrated circuit according to claim 1, wherein the first conductivity type is n type and the second conductivity type is p type. (4) The opto-electronic integrated circuit according to claim 1, wherein the first and third semiconductor layers are made of AlGaAs, and the second semiconductor layer is made of GaAs or AlGaAs. (5) The opto-electronic integrated circuit according to claim 3, wherein the second semiconductor layer is made of AlGaAs and has an Al composition lower than that of the first and third semiconductor layers. (6) The opto-electronic integrated circuit according to claim 1, wherein the first and third semiconductor layers are InP and the second semiconductor layer is InGaAs or InGaAsP. (7) The opto-electronic integrated circuit according to claim 1, wherein the semi-insulating substrate is GaAs or InP. (8) A first conductivity type wide-gap first semiconductor layer, a second conductivity type narrow-gap second semiconductor layer on a semi-insulating substrate;
A multilayer epitaxial film is formed by sequentially stacking a semiconductor layer of a second conductivity type and a wide gap third semiconductor layer, and a second semiconductor layer is placed in a first region of the multilayer epitaxial film as an active layer and a third semiconductor layer of a wide gap of a second conductivity type. A double hetero implantation type laser is constructed in which the first and third semiconductor layers serve as cladding layers, and in the second region of the multilayer epitaxial film, the first conductivity type is implanted into the third semiconductor layer using an ion implantation method. An impurity region is formed, the first semiconductor layer is an emitter, the impurity region of the first conductivity type formed mainly in the third semiconductor layer is a collector, and the impurity region is mainly sandwiched between an emitter and a collector in the second semiconductor layer. 1. A method for manufacturing an optical/electronic integrated circuit, characterized by configuring a region-based heterojunction bipolar transistor. (9) The method of manufacturing an opto-electronic integrated circuit according to claim 8, wherein the base has a second conductivity type high concentration impurity region on the collector side. (10) The method for manufacturing an optoelectronic integrated circuit according to claim 8, wherein the first conductivity type is n type and the second conductivity type is p type. (11) The method for manufacturing an opto-electronic integrated circuit according to claim 8, wherein the first and third semiconductor layers are made of AlGaAs, and the second semiconductor layer is made of GaAs or AlGaAs. (12) The opto-electronic integrated circuit according to claim 11, wherein the second semiconductor layer is made of AlGaAs and has an Al composition lower than that of the first and third semiconductor layers. Production method. (13) The method for manufacturing an opto-electronic integrated circuit according to claim 8, wherein the first and third semiconductor layers are InP and the second semiconductor layer is InGaAs or InGaAsP. (14) The method for manufacturing an opto-electronic integrated circuit according to claim 8, wherein the semi-insulating substrate is GaAs or InP.