JPS62274649A - Printed wiring board - Google Patents
Printed wiring boardInfo
- Publication number
- JPS62274649A JPS62274649A JP61117740A JP11774086A JPS62274649A JP S62274649 A JPS62274649 A JP S62274649A JP 61117740 A JP61117740 A JP 61117740A JP 11774086 A JP11774086 A JP 11774086A JP S62274649 A JPS62274649 A JP S62274649A
- Authority
- JP
- Japan
- Prior art keywords
- rom
- switch
- ultraviolet
- printed wiring
- wiring board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 claims abstract description 11
- 239000011347 resin Substances 0.000 claims abstract description 9
- 229920005989 resin Polymers 0.000 claims abstract description 9
- 238000007789 sealing Methods 0.000 abstract description 3
- 238000000465 moulding Methods 0.000 abstract description 2
- 238000010586 diagram Methods 0.000 description 3
- 238000005516 engineering process Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 239000000463 material Substances 0.000 description 2
- 239000004065 semiconductor Substances 0.000 description 2
- 230000009977 dual effect Effects 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
- H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
- H01L25/04—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
- H01L25/065—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
- H01L25/0655—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00 the devices being arranged next to each other
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/18—Printed circuits structurally associated with non-printed electric components
- H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔産業上の利用分野〕
本発明はメモリー素子及びその他の電気回路が配線、実
装されたプリント配線基板に関する。Detailed Description of the Invention 3. Detailed Description of the Invention [Field of Industrial Application] The present invention relates to a printed wiring board on which a memory element and other electric circuits are wired and mounted.
従来プリント配線基板上のメモリー素子のプログラム内
容を書き換える場合、ＩＣソケット及び紫外線透過窓付
きのＤＩＰ（Ｄｕａｌ ｉｎ Ｌｉｎｅ Ｐａｃ
ｃａ’ｇｅ）タイプのＵＶ−ＥＰＲＯＭを用い、ＤＩＰ
タイプのＥＰ−ＲＯＭをソケットから取り外して書き換
える方法、ＲＡＭＩＣを用いて電気的に書き換える方法
、Ｅ”−ＦＲＯＭ （電気的消去形プログラマブル Ｒ
ＯＭ）ｒＣを用いる方法等が知られている。Conventionally, when rewriting the program contents of a memory element on a printed wiring board, a DIP (Dual in Line Pac) with an IC socket and an ultraviolet transparent window is used.
ca'ge) type UV-EPROM, DIP
A method of rewriting an EP-ROM by removing it from the socket, a method of electrically rewriting it using a RAMIC, an E”-FROM (Electrically Erasable Programmable R
A method using rC (OM) is known.
しかし、前述の従来技術では、ＤＩＰタイプのＥＦ
ＲＯＭを用いる場合、ＣＯＢ方式に比べ、プリント基板
が大型化する。ＲＡＭを用いる場合そのプリント基板あ
るいはプリント基板により構成された機器を使用し、な
い場合にもＲＡＭ素子に電源電圧を印加しておかないと
、ＲＡＭ素子のメモリー内容が消去してしまう。Ｅ”
−ＦＲＯＭを用いる場合、ＵＶ−ＥＰ ＲＯＭに比ベ
コスト的に高くなる等それぞれの方法に問題点を有する
。However, in the above-mentioned conventional technology, the DIP type EF
When using ROM, the printed circuit board becomes larger compared to the COB method. When using a RAM, use the printed circuit board or a device configured with the printed circuit board, and even if there is no RAM, unless a power supply voltage is applied to the RAM element, the memory contents of the RAM element will be erased. E”
When using -FROM, each method has its own problems, such as higher cost compared to UV-EP ROM.
そこで本発明はこれらの問題点を解決するもので、その
目的とするところは、小型、安価で、その実装されたメ
モリー素子のプログラム内容を容易に書き変えられ、プ
ログラム内容が容易に保持できるプリント配線基板を提
供するところにある。The present invention is intended to solve these problems, and its purpose is to create a print that is small, inexpensive, allows the program contents of the memory element mounted thereon to be easily rewritten, and that allows the program contents to be easily retained. The company provides wiring boards.
本発明のプリント配線基板は、［ＪＶ−ＥＰ ＲＯＭ
ＩＣ及び他ＩＣをＣＯＢ方式で実装し、ＵＶ−ＥＦ
ＲＯＭ ＩＣは紫外線透過型樹脂で封止し、かつＵＶ
−ＥＦ ＲＯＭ ＩＣを他の電気回路から電気的に
切り離すための機械的あるいは電気的スイッチを有する
ことを特徴とする。The printed wiring board of the present invention is [JV-EP ROM
IC and other ICs are mounted using COB method, and UV-EF
The ROM IC is sealed with UV-transparent resin and
- It is characterized by having a mechanical or electrical switch for electrically disconnecting the EF ROM IC from other electrical circuits.
本発明の上記の構成によれば、ＣＯＢ実装のためプリン
ト配線基板を小型化できる。また、プリント配線基板に
紫外線を照射することによりその実装されたメモリー素
子の内容を容易に消去できメモリー素子を他の電気回路
から電気的に切り離すことにより、他の電気回路部分の
影響を受けずに、書き込み装置を用いて容易にメモリー
素子にプログラムすることが可能である。According to the above configuration of the present invention, the printed wiring board can be downsized due to COB mounting. In addition, by irradiating the printed wiring board with ultraviolet rays, the contents of the mounted memory element can be easily erased, and by electrically isolating the memory element from other electrical circuits, it is not affected by other electrical circuit parts. Furthermore, it is possible to easily program the memory device using a writing device.
第１図は本発明の実施例におけるプリント配線基板の断
面図であって、■のＵＶ−ＥＦ ＲＯＭＩＣをＣＯＢ
実装し、■の紫外線透過型樹脂で封止した状態を示す、
ＵＶ−ＥＦ ＲＯＭ以外のＩＣチップ■も同様にＣＯ
Ｂ実装し、これらは通常のモールド用樹脂■で封止する
。FIG. 1 is a cross-sectional view of a printed wiring board in an embodiment of the present invention, in which the UV-EF ROMIC (■) is
The state shown is mounted and sealed with ultraviolet-transmissive resin (■).
IC chips other than UV-EF ROM are also CO
B-mounted and sealed with ordinary molding resin (■).
第２図は本発明の実施例におけるＵＶ−ＥＰＲＯＭ素子
周辺の電気接続図であって、■のＵＶＥＦ ＲＯＭ
ＩＣを紫外線により消去後、■のスイッチをオープン
させることにより、他の電気回路から切り離し、さらに
■の書き込み用端子に書き込み装置を接続してＵＶ−Ｅ
Ｆ ＲＯＭにプログラムすることができる。書き込み
終了後は再びスイッチ■をクローズして他の電気回路と
接続させ、回路基板全体の一部として動作させることが
できる。このスイッチ■は機械的スイッチでもアナログ
スイッチ等の電気的接点でも一部にかまわない。FIG. 2 is an electrical connection diagram around the UV-EPROM element in the embodiment of the present invention.
After erasing the IC with ultraviolet light, open the switch (■) to disconnect it from other electrical circuits, and then connect the writing device to the writing terminal (■) to erase the IC with UV-E.
It can be programmed into F ROM. After writing is completed, switch (2) is closed again to connect it to other electrical circuits, allowing it to operate as part of the entire circuit board. This switch (2) may be a mechanical switch or an electrical contact such as an analog switch.
以上述べたように本発明によれば、小型、安価で、容易
にプログラムの書き変えが可能な、しかもｉｔ源を切り
離してもその内容を保持していることの可能なメモリー
素子を有する電気回路基板を構築できる。As described above, according to the present invention, an electric circuit having a memory element that is small, inexpensive, easily reprogrammable, and capable of retaining its contents even when the IT source is disconnected. You can build a board.
第１図は本発明のプリント配線基板の主要断面図。
■紫外線透過型半導体封止樹脂
■配線パターン
■半導体封止樹脂
■プリント配線基板基材
■ＵＶ−ＥＦ ＲＯＭ素子
■ＵＶ−ＥＦ ＲＯＭ以外の半専体素子第２図は本発
明の実施例におけるＵＶ−ＥＰＲＯＭ素子周辺の電気接
続図。
■書き込み装置接続端子
■ＵＶ−ＥＦ ＲＯＭ素子
■切り離し用スイッチ
■アドレスバス
■データバス
■ＵＶ−ＥＦ ＲＯＭコントロールライン第３図は従
来技術の一例でＤＩＰタイプＥＦＲＯＭをＩＣソケット
を用いて実装した状態を示した図。
■配線パターン
■プリント配線基板基材
■ＤＩＰタイプＵＶ−ＥＰ ＲＯＭ素子■ＩＣソケッ
ト
以 上
出願人 セイコーエプソン株式会社
葬１吃
図面の浄書（内容に変更なし）
第２図
手 続 補 正 書 〔方式〕
昭和６１年８ 月２７ 日
１１」帽庁長官 殿 兜
１．１［件の表示
［−′（和６１年 特許願 第１１７７４０号２発
明の名１ｆｌｉ
プリント配１Ｍ基板
３ 補正とする者
１ト件との関係
出願人東京都新宿区西新宿２丁目４番１号（２５６）セ
イコーエプソン株式会社
４１、 よ い 代表取締役 服 部 −
部〒１０４ 東京都中央区京橋２丁目６番２１号株式
会社 眼部セイコー内 最上特許事務所（４６６４）
弁理士 最 上 務（他１名）図面術２図（内
容に変更なし〕FIG. 1 is a main sectional view of the printed wiring board of the present invention. ■Ultraviolet-transmissive semiconductor sealing resin ■Wiring pattern ■Semiconductor sealing resin ■Printed wiring board base material ■UV-EF ROM element ■Semi-dedicated element other than UV-EF ROM Figure 2 shows UV in the embodiment of the present invention - Electrical connection diagram around the EPROM element. ■Writing device connection terminal ■UV-EF ROM element ■Disconnection switch ■Address bus ■Data bus ■UV-EF ROM control line Figure 3 is an example of the conventional technology, and shows a DIP type EFROM mounted using an IC socket. The diagram shown. ■Wiring pattern ■Printed wiring board base material ■DIP type UV-EP ROM element ■IC socket and above Applicant: Seiko Epson Co., Ltd. Engraving of the first drawing (no change in content) Fig. 2 Procedures Amendment [Method] ] August 27, 1985 11 "To the Director General of the Agency" 1.1 [Indication [-' (Japanese 61st year Patent Application No. 117740 2 Name of the invention 1fli Printed 1M board 3 Person making the amendment 1) Applicant related to the matter: Seiko Epson Corporation 41, 2-4-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo (256), Representative Director Hattori -
Mogami Patent Office (4664), Eye Department Seiko Co., Ltd., 2-6-21 Kyobashi, Chuo-ku, Tokyo 104
Patent Attorney Tsutomu Mogami (1 other person) Drawing techniques 2 drawings (no change in content)
Claims (1)
ＲＯＭ）ＩＣ及びＣＰＵ等その他のＩＣがＣＯＢ（Ｃｈ
ｉｐ ｏｎ Ｂｏｒｄ）方式で実装されたプリント配線
基板において、ＵＶ−ＥＰＲＯＭ ＩＣを紫外線透過型
樹脂で封止し、かつＵＶ−ＥＰ ＲＯＭ ＩＣを他の電
気回路から電気的に切り離すための機械的あるいは電気
的スイッチを有することを特徴とするプリント配線基板
。UV-EP ROM (ultraviolet erasable programmable
ROM) IC and other ICs such as CPU are COB (Ch
In a printed wiring board mounted using the IP on Board method, the UV-EPROM IC is sealed with an ultraviolet-transmissive resin, and mechanical or electrical 1. A printed wiring board characterized by having a mechanical switch.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61117740A JPS62274649A (en) | 1986-05-22 | 1986-05-22 | Printed wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61117740A JPS62274649A (en) | 1986-05-22 | 1986-05-22 | Printed wiring board |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62274649A true JPS62274649A (en) | 1987-11-28 |
Family
ID=14719126
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61117740A Pending JPS62274649A (en) | 1986-05-22 | 1986-05-22 | Printed wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62274649A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1991007753A1 (en) * | 1989-11-08 | 1991-05-30 | Signalling Technology Pty. Ltd. | In-circuit programming of integrated circuits |
-
1986
- 1986-05-22 JP JP61117740A patent/JPS62274649A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1991007753A1 (en) * | 1989-11-08 | 1991-05-30 | Signalling Technology Pty. Ltd. | In-circuit programming of integrated circuits |
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