JPS62272632A - Division and transmission equipment for television signal - Google Patents
Division and transmission equipment for television signalInfo
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- JPS62272632A JPS62272632A JP61116460A JP11646086A JPS62272632A JP S62272632 A JPS62272632 A JP S62272632A JP 61116460 A JP61116460 A JP 61116460A JP 11646086 A JP11646086 A JP 11646086A JP S62272632 A JPS62272632 A JP S62272632A
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- 238000003786 synthesis reaction Methods 0.000 abstract description 19
- 230000006866 deterioration Effects 0.000 abstract description 4
- 238000010586 diagram Methods 0.000 description 18
- 230000007274 generation of a signal involved in cell-cell signaling Effects 0.000 description 12
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Abstract
Description
【発明の詳細な説明】
３、発明の詳細な説明
〔概要〕
テレビ信号を送信側で第１〜第ｎ （ｒ１≧２）のディ
ジタル信号に分割し、それぞれを第１〜第ｎの伝送路に
並列伝送し、受信側では受信した各分割信号を合成して
原テレビ信号に復原するテレビ信号の分割伝送において
、
テレビ信号をフィールド単位、ライン単位または画素単
位等テレビ信号の特徴を生かしたプロ・７り単位での分
割を行って送信側から送出し、もし第１〜第ｎのうち一
部の伝送路でデータ信号の欠落や誤りが発生した場合に
は、受信側に当該信号を判別する機能をもたせるととも
に、欠落や誤りがあると判別した分割信号を使用せず、
テレビ信号の画面構成の特性から信号の近慎相関性の強
い隣接フィールド、隣接ライン或は隣接画素の分割信号
を代替として使用し補間すること、および、受信データ
信号からのクロック抽出についても欠落や誤りがあると
判別した分割信号を避は正常な分割信号からクロック抽
出を行うことによって、
第１〜第ｎの一部の伝送路でデータ信号の欠落や誤りを
発生した場合でも、画質劣化の少ないテレビ画像の復原
を可能とする。[Detailed Description of the Invention] 3. Detailed Description of the Invention [Summary] A television signal is divided into first to nth (r1≧2) digital signals on the transmitting side, and each is transmitted to the first to nth transmission paths. In the divided transmission of television signals, the received divided signals are combined and restored to the original television signal on the receiving side.・It is divided into 7 units and sent from the transmitting side, and if a data signal is missing or an error occurs in some of the 1st to nth transmission paths, the receiving side can identify the signal. In addition to having the function of
Due to the characteristics of the screen configuration of television signals, it is necessary to interpolate by using divided signals of adjacent fields, adjacent lines, or adjacent pixels with strong signal correlation, and also to eliminate omissions in clock extraction from received data signals. By extracting a clock from a normal divided signal instead of a divided signal determined to have an error, it is possible to prevent image quality from deteriorating even if a data signal is missing or an error occurs in some of the 1st to nth transmission paths. To make it possible to restore a small number of television images.
テレビ信号を送イ８側で第１〜第ｎ （ｎ≧２）のディ
ジタル信号に分割し、それぞれ第１〜第ｎの伝送路に並
列伝送し、受信側で受信した該第１〜第ｎの分割信号を
合成して原テレビ信号に復原するテレビ信号の分割伝送
装置の改良に関する。The TV signal is divided into the first to nth (n≧2) digital signals on the transmission side, and transmitted in parallel to the first to nth transmission paths, respectively, and the first to nth digital signals received on the receiving side are The present invention relates to an improvement in a television signal division transmission device that combines divided signals of and restores the original television signal.
テレビ信号のディジタル伝送の分野では、伝送路の伝送
容量（伝送速度）の制約がある場合に経済的にこれを解
決する方法として、原テレビ信号を複数の低速ディジク
ル伝送路に分割して送信し、受信側で再び原テレビ信号
に復原する方法がよく用いられている。In the field of digital transmission of television signals, when there is a restriction on the transmission capacity (transmission speed) of the transmission line, an economical way to solve this problem is to divide the original television signal over multiple low-speed digital transmission lines and transmit it. , a method is often used in which the receiving side restores the original television signal again.
この場合伝送路途中の状況により、もし分割信号の一部
に符号欠落や誤りが生じた時でも、復原画像の品質を維
持できる方式が望まれる。In this case, it is desirable to have a method that can maintain the quality of the restored image even if code loss or errors occur in part of the divided signals due to conditions on the transmission path.
第２図は従来例の送信側回路構成を説明するブロック図
、第３図は従来例の受信側回路構成を説明するブロック
図、第４図は第２図、第３図の場合の主要部データ信号
のタイムチャートで、第４図中の（Ａ）、 （Ｂ）、
（Ｃ）、 ・・・・ （Ｇ）はそれぞれ第２図、
第３図中に付した記号ａ、ｂ。Fig. 2 is a block diagram explaining the transmitting side circuit configuration of the conventional example, Fig. 3 is a block diagram explaining the receiving side circuit configuration of the conventional example, and Fig. 4 shows the main parts in the case of Figs. 2 and 3. In the time chart of the data signal, (A), (B),
(C), ... (G) are respectively shown in Figure 2,
Symbols a and b in Fig. 3.
Ｃ２・・・・ｇに対応させである。C2...corresponds to g.
また、第５図は第２図、第３図の制御信号発生の詳細を
示す１例のブロック図、第６図は第２図の分割用セレク
タの詳細を示す１例のブロック図である。Further, FIG. 5 is a block diagram of an example showing details of control signal generation in FIGS. 2 and 3, and FIG. 6 is a block diagram of an example showing details of the division selector of FIG. 2.
第２図は分割信号が２つ（ｎ ＝ ２）の場合の例であ
る。同図において、
クロック発生回路６は、送信側各回路に必要なりロック
信号を供給する回路であって、伝送路クロックＣＬ−２
の繰り返し周波数は符号化クロックＣＬ−１の繰り返し
周波数の１／２である。FIG. 2 shows an example in which there are two divided signals (n=2). In the same figure, a clock generation circuit 6 is a circuit that supplies a lock signal necessary to each circuit on the transmission side, and is a circuit that supplies a transmission line clock CL-2.
The repetition frequency is 1/2 of the repetition frequency of the encoding clock CL-1.
まず、アナログテレビ信号はＡ／Ｄ変換部１、帯域圧縮
符号化部２を経由して分割用セレクタ３３のＤ端子に入
力される。First, an analog television signal is input to the D terminal of the division selector 33 via the A/D converter 1 and the band compression encoder 2.
分割用セレクタ３３は、そのＳ端子に制御信号発生回路
３２から供給されている制御信号のタイミングに従って
、第４図（Ａ）、 （Ｂ）に示すようにデータ信号を
分割して、出力端子ＡおよびＢから交互に送出する。The division selector 33 divides the data signal as shown in FIG. and B alternately.
この動作について、制御信号発生回路３２と分割用セレ
クタ３３の回路例により具体的に説明する。This operation will be specifically explained using a circuit example of the control signal generation circuit 32 and the division selector 33.
制御信号発生回路３２の１回路例は第５図（Ａ）に示す
如きＦＦ回路であって、ＣＬ端子への入力トリガパルス
のタイミングで同図（Ｂ）に示す波形の制御信号をＱ端
子から出力する。従来例の送信側回路構成では、入力ト
リガパルスとして第２図に示すようにカウンタ３１でデ
ータ信号ｌブロック分の所定パルス数をカウントした桁
上げ信号を入力する。One circuit example of the control signal generation circuit 32 is an FF circuit as shown in FIG. 5(A), which generates a control signal having the waveform shown in FIG. 5(B) from the Q terminal at the timing of the input trigger pulse to the CL terminal. Output. In the conventional transmitting side circuit configuration, as shown in FIG. 2, a carry signal obtained by counting a predetermined number of pulses for one block of data signals by a counter 31 is input as an input trigger pulse.
分割用セレクタ３３の１回路例は第６図に示す如き回路
であって、そのＳ端子へ制御信号発生回路３２から入力
される第５図（Ｂ）のような制御信号により、第１およ
び第２の分割データ信号が出力端子ＡおよびＢから交互
に出力される。One circuit example of the dividing selector 33 is a circuit as shown in FIG. 6, in which the first and second Two divided data signals are output from output terminals A and B alternately.
これらの分割データ信号は、それぞれ分割用ＦＦ回路３
４．３５を経てバッファメモリ４１．４２に一旦記憶さ
れた後、クロック信号ＣＬ−２によって読み出され伝送
フレーム構成・誤り訂正符号化を受け、第４図（Ｃ）、
（Ｄ）に示すような低速データ信号として伝送路第１
および第２に送出される。These divided data signals are sent to the dividing FF circuit 3.
4.35 and is temporarily stored in the buffer memory 41.42, it is read out by the clock signal CL-2 and subjected to transmission frame configuration and error correction encoding, as shown in FIG. 4(C).
The first transmission line is used as a low-speed data signal as shown in (D).
and secondly sent out.
次に受信側では、各伝送路から受信された第１および第
２の分割データ信号（Ｃ）、 （Ｄ）は受信部７で誤り
訂正復号化、伝送フレーム分解の過程を経て、それぞれ
バッファメモリ８Ｌ ８２に記憶された後、クロック抽
出回路１２からの号号化クロック信号ＣＬ−１’で読み
出されるので、合成用ＦＦ回路９Ｌ ９２から合成用セ
レクタ９３のＡ、Ｓ端子への入力信号は、それぞれ第４
図の（Ｅ）、 （Ｆ）に示すような奇数または偶数ブロ
ックを２回宛繰り返す信号となる。Next, on the receiving side, the first and second divided data signals (C) and (D) received from each transmission path are subjected to error correction decoding and transmission frame disassembly processes in the receiving section 7, and are stored in buffer memory respectively. After being stored in the 8L 82, it is read out using the encoded clock signal CL-1' from the clock extraction circuit 12, so the input signal from the synthesis FF circuit 9L 92 to the A and S terminals of the synthesis selector 93 is as follows. 4th each
This is a signal that repeats odd or even blocks twice as shown in (E) and (F) in the figure.
合成部９のカウンタ９４は、復号化クロックＣＬ−１′
の周期で原データ信号の１ブロック分のパルス数をカウ
ントし、その桁上げ信号を基に制御信号発生回路９５か
ら合成用セレクタ９３のＳ端子へ制御信号を入力させる
ので、合成用セレクタ９３のＤ出力端子からは第４図（
Ｇ）に示すような合成信号を出力し、以下、帯域圧縮復
号化、Ｄ／Ａ変換の過程を経て原アナログＴＶに復原さ
れる。The counter 94 of the synthesis unit 9 receives the decoding clock CL-1'
The number of pulses for one block of the original data signal is counted at the period of From the D output terminal, Fig. 4 (
A composite signal as shown in G) is output, and is then restored to the original analog TV through the processes of band compression decoding and D/A conversion.
次に、一般にｎ≧３の場合については、各分割信号用ク
ロックとして、
（ア）その繰り返し周波数が、ＣＬ−１の繰り返し周波
数の１／ｎであって、
（イ）第２〜第ｎの分割信号用クロックについては、第
１の分割信号用クロックに対する位相遅れが、
第２の分割信号用クロックは２πＸ （１／ｎ）第３の
分割信号用り、ロックは２πＸ （２／ｎ）第ｎの分割
信号用クロックは２πｘ （ｎ−１／ｎ ）であるｎ個
のパルスを各伝送路クロックとして用いれば、前記説明
と類似の手段で分割、合成が可能である。Next, in general, in the case of n≧3, as a clock for each divided signal, (a) its repetition frequency is 1/n of the repetition frequency of CL-1, and (b) the second to nth Regarding the divided signal clock, the phase delay with respect to the first divided signal clock is 2πX (1/n) for the second divided signal, and the lock is 2πX (2/n) for the third divided signal. If the n divided signal clocks are 2πx (n-1/n) and n pulses are used as each transmission line clock, division and synthesis can be performed by means similar to those described above.
しかしながら、もし第１〜第ｎの伝送路の何れか１つで
も伝送路途中でデータ信号に欠落や誤りを生じた場合に
は、当該分割信号が正確でないため復原テレビ画像の顕
著な画質劣化が現れるという問題点、および、受信側に
おいてクロックを抽出している伝送路にもし誤りが発生
した場合には、画像の復原が困難になるという問題点が
ある。However, if a dropout or error occurs in the data signal in any one of the first to nth transmission paths, the divided signals will not be accurate and the reconstructed television image will be significantly degraded in image quality. If an error occurs in the transmission path from which the clock is extracted on the receiving side, it becomes difficult to restore the image.
上記問題点は第１図本発明の原理説明ブロック図に示す
如く、テレビ信号をフィールド単位、ライン単位または
画素単位等テレビ信号の特徴を生かしたブロック単位で
の分割を行って送信側から送出し、もし第１〜第ｎのう
ち一部の伝送路でデータ信号の欠落や誤りを発生した場
合には、受信側で当該信号を判別する機能をもたせると
ともに、欠落や誤りがあると判別した分割信号に替えて
正常な他の分割信号で補間すること、および受信データ
信号からのクロック抽出についても欠落や誤りがあると
判別した分割信号を避は正常な分割信号からクロック抽
出を行うようにした本発明によるテレビ信号の分割伝送
装置によって解決される。As shown in Figure 1, a block diagram explaining the principle of the present invention, the above problem is solved by dividing the television signal into blocks that take advantage of the characteristics of the television signal, such as by field, by line, or by pixel, and then sending it out from the transmitting side. If a data signal is missing or an error occurs in some of the first to nth transmission paths, the receiving side is provided with a function to identify the signal, and the division that determines that there is a loss or error occurs. Interpolating with another normal divided signal instead of the received data signal, and extracting the clock from the normal divided signal instead of the divided signal determined to be missing or erroneous when extracting the clock from the received data signal. The problem is solved by a television signal division transmission device according to the present invention.
本発明によれば、
送信側では、テレビ信号の分割に当って従来例のように
任意のブロックに分割するのでなく、フィールド単位、
ライン単位または画素単位等テレビ信号の特徴を生かし
たブロック単位で分割して送信するために、テレビ画像
信号に固有の同期信号を抽出する同期信−号抽出回路１
３を設け、受信側では、途中伝送路でデータ信号の欠落
や誤りが発生した場合に、誤り訂正限界信号によって当
該信号を判別する機能をもたせ、
欠落や誤りが生じたと判別した場合には、合成部で当該
分割信号を使用せず、代替として信号の近似相関性の強
い隣接フィールド、隣接ライン或は隣接画素の分割信号
で補間するための制御信号選択回路１４を設け、
また、受信データ信号からのクロック抽出についても欠
落や誤りがあると判別した分割信号を避は正常な分割信
号からクロック抽出を行うための受信信号セレクタ１５
を設けることによって、伝送路の一部でデータ信号に欠
落や誤りを生じた場合でも、画質劣化の少ないテレビ画
像の復原が可能である。According to the present invention, on the transmitting side, when dividing a television signal, instead of dividing it into arbitrary blocks as in the conventional example,
Synchronization signal extraction circuit 1 that extracts a synchronization signal specific to a television image signal in order to divide and transmit it in block units that take advantage of the characteristics of the television signal, such as line units or pixel units.
3 is provided, and on the receiving side, if a data signal is missing or an error occurs on the transmission path, the receiving side has a function to identify the signal using an error correction limit signal, and if it is determined that a data signal has been lost or an error has occurred, A control signal selection circuit 14 is provided for interpolating instead of using the divided signals in the combining section, using divided signals of adjacent fields, adjacent lines, or adjacent pixels having strong signal approximate correlation, and also for receiving data signals. The received signal selector 15 is used to extract clocks from normal divided signals, avoiding divided signals determined to be missing or erroneous.
By providing this, it is possible to restore television images with less deterioration in image quality even if a data signal is missing or has an error in part of the transmission path.
以下、フィールド単位の分割で、奇数群、偶数群の２分
割（ｎ＝２）の場合について実施例を説明する。Hereinafter, an embodiment will be described in which the field is divided into two groups, an odd number group and an even number group (n=2).
第７図に示す本発明の実施例の送信側回路構成を説明す
るブロック図において、帯域圧縮符号化部２、制御信号
発生回路３２、分割用セレクタ３３、分割用ＦＦ回路３
４．３５、バッファメモリ４１．４２、送信部５、クロ
ック発生回路６は第２図の従来例と同−の回路であるが
、Ａ／Ｄ変換部１′には従来例のＡ／Ｄ変換機能の他に
、フィールド信号がら（垂直）同期信号を取り出して制
御信号発生回路３２へのトリガーパルスを与える同期信
号抽出回路１３が追加されている。In the block diagram illustrating the transmitting side circuit configuration of the embodiment of the present invention shown in FIG.
4.35, buffer memory 41, 42, transmitter 5, and clock generation circuit 6 are the same circuits as the conventional example shown in FIG. In addition to the functions, a synchronization signal extraction circuit 13 is added that extracts a (vertical) synchronization signal from the field signal and provides a trigger pulse to the control signal generation circuit 32.
従って、送信側からは奇数番、偶数番のフィールドが交
互に、分割信号として伝送路箱１および第２に送出され
る。Therefore, from the transmitting side, odd-numbered and even-numbered fields are alternately sent to transmission line boxes 1 and 2 as divided signals.
次に、第８図本発明の実施例の受信側回路構成を説明す
るブロック図において、バッファメモリ８１ Ｂ２、合
成用ＦＦｐｌｉｌ路９１．９２、合成用セレクタ９３、
制御信号発生回路９５、帯域圧縮復号化部１０、Ｄ／Ａ
変換部１１、クロック抽出回路１２は第３図の従来例と
同一の回路であるが、誤り訂正復号回路７１“。Next, in FIG. 8, a block diagram illustrating the receiving side circuit configuration of an embodiment of the present invention, a buffer memory 81B2, FFplil paths for synthesis 91, 92, selector for synthesis 93,
Control signal generation circuit 95, band compression decoding section 10, D/A
The conversion unit 11 and clock extraction circuit 12 are the same circuits as in the conventional example shown in FIG. 3, but an error correction decoding circuit 71'' is used.
７２゛には本発明による判別信号発生機能が追加されて
おり、また、同期信号抽出回路９６、制御信号選択回路
１４、受信信号セレクタ１５は本発明による追加された
回路である。A discrimination signal generation function according to the present invention is added to 72', and a synchronizing signal extraction circuit 96, a control signal selection circuit 14, and a received signal selector 15 are added circuits according to the present invention.
以下、追加された機能および各回路について詳細６°説
明ｔ６・ １まず、通常用い
られている誤り訂正符復号方式はＢＣＨ符号方式のよう
に、送信側でデータ信号１ブロツク毎に所定数の誤り訂
正ビットを付加し、受信側で符号理論に基づく訂正を行
う方法であって、この場合付加する誤り訂正ビットのビ
ット数によって定まる誤り訂正の可能限界があり、また
限界を超えた場合には、そのことを判断できる機能をも
っている。（電子通信学界績、データ通信ハンドブック
参照）
これに基づいて誤り訂正復号回路７１’、 ７２°には
、誤り訂正状態の判別信号として誤り訂正の実行可能中
は符号“１” （Ｈ４ｇｈレベル）を、誤り訂正の可能
限界を超えた場合には符号“０” （Ｌｏ−レベル）を
、発生する判別信号発生機能を付加しであるので、受信
データ信号の欠落や誤りの有無を判別することができる
。Below is a detailed explanation of the added functions and each circuit.t6.1 First, the normally used error correction code/decoding system, like the BCH code system, is a system that processes a predetermined number of errors per block of data signals on the transmitting side. This method adds correction bits and performs correction based on code theory on the receiving side. In this case, there is a possible error correction limit determined by the number of error correction bits to be added, and if the limit is exceeded, It has the ability to determine this. (Refer to the Electronic Communication Academic Report and the Data Communication Handbook) Based on this, the error correction decoding circuits 71' and 72° output a code "1" (H4gh level) as an error correction status determination signal when error correction is executable. , a discrimination signal generation function is added that generates a code "0" (Lo-level) when the possible limit of error correction is exceeded, so it is possible to distinguish whether there is a dropout or error in the received data signal. can.
合成部９′の同期信号抽出回路９６は、伝送路第１側の
入力データ信号が正常状態の時、そのフィールド信号の
（垂直）同期信号のタイミングで、第１．第２のデータ
信号を交互に配置して合成するためのタイミング用パル
スの抽出回路であって、抽出されたパルスは制御信号発
生回路９５へ入力される。When the input data signal on the first side of the transmission line is in a normal state, the synchronization signal extraction circuit 96 of the combining section 9' extracts the first . This is a timing pulse extraction circuit for alternately arranging and synthesizing second data signals, and the extracted pulses are input to the control signal generation circuit 95.
制御信号発生回路９５は既に第５図従来例の制御信号発
生回路説明図で説明したと同一の回路で、この場合のト
リガーパルスは前記のフィールド信号の（垂直）同期信
号である。The control signal generation circuit 95 is the same circuit as that already explained in FIG. 5, which is an explanatory diagram of the conventional control signal generation circuit, and the trigger pulse in this case is the (vertical) synchronization signal of the field signal.
合成部９”の合成用セレクタ９３および制御信号選択回
路１４の動作を具体的に説明するための回路例は、第１
０図の本発明の実施例の合成用セレクタ及び制御信号選
択回路ブロック図に示す如くである。A circuit example for specifically explaining the operation of the synthesis selector 93 and the control signal selection circuit 14 of the synthesis section 9'' is shown in the first example.
0 is a block diagram of a synthesis selector and control signal selection circuit according to an embodiment of the present invention.
第１０図において第１．第２の分割データ信号が正常の
場合には、第１．第２の判別信号としてそれぞれ“１”
が入力されるので制御信号選択回路１４の出力は、第１
の分割信号からの制御信号そのものである。従って合成
用セレクタ９３のＤ端子出力は、第９図のタイムチャー
ト中の（Ｇ−１）に示すような奇数番、偶数番フレーム
交互配置の合成信号が得られる。In Figure 10, 1. When the second divided data signal is normal, the first divided data signal is normal. “1” for each as the second discrimination signal
is input, the output of the control signal selection circuit 14 is the first
This is the control signal itself from the divided signal. Therefore, the output from the D terminal of the synthesis selector 93 is a synthesis signal in which odd and even frames are alternately arranged as shown at (G-1) in the time chart of FIG.
また、第１正常、第２異常の場合には、第１の判別信号
“１”、第２の判別信号“０”が人力されるので、制御
信号選択回路１４の出力は“１”となる。従って合成用
セレクタ９３のＤ端子出力は第９図の（Ｇ−２）に示す
ように合成用セレクタ９３のＡ端子入力そのもので、結
局異常と判別された第２の分割データ信号に替えて第１
の分割データ信号を補完した形の合成信号となる。In addition, in the case of the first normality and the second abnormality, the first discrimination signal "1" and the second discrimination signal "0" are manually input, so the output of the control signal selection circuit 14 becomes "1". . Therefore, the D terminal output of the synthesis selector 93 is the A terminal input of the synthesis selector 93 itself, as shown in (G-2) in FIG. 1
This is a composite signal that complements the divided data signals.
同様に第１異常、第２正常の場合には、制御信号選択回
路１４の出力が“Ｏ”となるので、第９図中の（Ｇ−３
）に示すように異常と判別された第１の分割データ信号
に替えて第２の分割データ信号を補完した合成信号出力
を得る。Similarly, in the case of the first abnormality and the second normality, the output of the control signal selection circuit 14 becomes "O", so (G-3
), a composite signal output is obtained by supplementing the second divided data signal in place of the first divided data signal determined to be abnormal.
次に、正常な状態の分割データ信号からクロックを抽出
するための受信信号セレクタ１５の回路例を第８図本発
明の実施例の受信信号セレクタブロック図に示しである
。同図で第１の分割データ信号が正常な場合には第１の
分割データ信号がその出力となり、また、第１の分割デ
ータ信号が異常で第２の分割データ信号が正常な場合に
は、第２の分割データ信号が出力となるので、次段のク
ロック抽出回路１２から常に正常なりロック信号出力を
得ることができる。Next, a circuit example of the received signal selector 15 for extracting a clock from a divided data signal in a normal state is shown in FIG. 8, a block diagram of a received signal selector according to an embodiment of the present invention. In the figure, when the first divided data signal is normal, the first divided data signal becomes the output, and when the first divided data signal is abnormal and the second divided data signal is normal, Since the second divided data signal is output, a normal lock signal output can always be obtained from the clock extraction circuit 12 at the next stage.
以上説明したように分割数ｎ＝２の場合には追加回路が
簡単な構成で済み、本発明の適用による経済的高価も特
に大きい。As explained above, when the number of divisions is n=2, the additional circuit can be of a simple configuration, and the economical cost of applying the present invention is particularly large.
またｎ≧３の場合には、異常発生した分割信号の組合せ
パターンと対処すべき代替分割信号の組合せパターンが
多くなり、前記のような論理回路を拡大する方法は得策
でないので、ＲＯＭに対応パターンを記憶させこれを読
み出して制御信号を選択する方法によって、前記説明と
同様の効果をもつ受信側回路を構成することができる。In addition, when n≧3, there are many combination patterns of the abnormally generated divided signals and alternative divided signals to be dealt with, and the method of expanding the logic circuit as described above is not a good idea. By storing and reading out the information to select a control signal, a receiving side circuit having the same effect as described above can be constructed.
以上説明したように、本発明は分割ディジタル信号が誤
り訂正符復号方式の訂正限界を超えた場合には、欠落や
誤りがある分割信号の使用を避け、テレビ信号の特性を
活かして信号の近似相関性の強い隣接フィールド、隣接
ライン或は隣接画素の分割信号での補間合成を行い、
また、クロック抽出は常に正常な分割信号から行うので
、
第１〜第ｎの一部の伝送路でデータ信号の欠落や誤りを
発生した場合でも、画質劣化の少ないテレビ画像を復原
する効果が大きい。As explained above, the present invention avoids the use of divided signals with omissions or errors when the divided digital signal exceeds the correction limit of the error correction code/decoding system, and approximates the signal by taking advantage of the characteristics of the television signal. Interpolation synthesis is performed using divided signals of adjacent fields, adjacent lines, or adjacent pixels with strong correlation, and clock extraction is always performed from normal divided signals. Even when signal loss or errors occur, it is highly effective in restoring television images with little deterioration in image quality.
第１図は本発明の原理説明ブロック図、第２図は従来例
の送信側回路構成を説明するブロック図、
第３図は従来例の受信側回路構成を説明するブロック図
、
第４図は従来例の主要部データ信号の
タイムチャート、
第５図は従来例の制御信号発生回路説明図、第６図は従
来例の分割用セレクタブロック図、第７図は本発明の実
施例の送信側回路構成を説明するブロック図、
第８図は本発明の実施例の受信側回路構成を説明するブ
ロック図、
第９図は本発明の実施例の受信側主要部データ信号のタ
イムチャート、
第１０図は本発明の実施例の合成用セレクタ及び制御信
号選択回路ブロック図、
第１１図は本発明の実施例の受信信号セレクタブロック
図
である。
図において、
■、１′は Ａ／Ｄ変換部、
２ は 帯域圧縮符号化部、
３．３′は 分割部、
５ は 送信部、
６ は クロック発生回路、
７．７′は 受信部、
９．９′は 合成部、
１０ は 帯域圧縮復号化部、
１１ は Ｄ／Ａ変換部、
１２ は クロック抽出回路、
１３．９６ は 同期信号抽出回路、１４ は
制御信号選択回路、
１５ は 受信信号セレクタ、
３１．９４ は カウンタ、
３２．９５ は 制御信号発生回路、３３ は
分割用セレクタ、
３４．３５ は 分割用ＦＦ回路、
４１．４２．８１．８２ は バッファメモリ、７
１．７１’ 、７２．７２′は 誤り訂正復号回路、９
１．９２ は 合成用ＦＦ回路、
９３ は 合成用セレクタ
である。
本発明の実施例の受信信号セレクタプロ第１１図
ツク図FIG. 1 is a block diagram explaining the principle of the present invention, FIG. 2 is a block diagram explaining the transmitting side circuit configuration of a conventional example, FIG. 3 is a block diagram explaining the receiving side circuit configuration of the conventional example, and FIG. A time chart of the main part data signal of the conventional example, FIG. 5 is an explanatory diagram of the control signal generation circuit of the conventional example, FIG. 6 is a block diagram of the division selector of the conventional example, and FIG. 7 is the transmitting side of the embodiment of the present invention. 8 is a block diagram illustrating the circuit configuration of the receiving side according to the embodiment of the present invention; FIG. 9 is a time chart of the main data signal of the receiving side according to the embodiment of the present invention; 10. FIG. 11 is a block diagram of a synthesis selector and control signal selection circuit according to an embodiment of the present invention, and FIG. 11 is a block diagram of a received signal selector according to an embodiment of the present invention. In the figure, ■, 1' is the A/D conversion section, 2 is the band compression encoding section, 3.3' is the dividing section, 5 is the transmitting section, 6 is the clock generation circuit, 7.7' is the receiving section, 9 .9' is a synthesis section, 10 is a band compression decoding section, 11 is a D/A conversion section, 12 is a clock extraction circuit, 13.96 is a synchronization signal extraction circuit, 14 is a control signal selection circuit, 15 is a received signal selector , 31.94 is a counter, 32.95 is a control signal generation circuit, 33 is a selector for division, 34.35 is an FF circuit for division, 41.42.81.82 is a buffer memory, 7
1.71' and 72.72' are error correction decoding circuits, 9
1.92 is a synthesis FF circuit, and 93 is a synthesis selector. Figure 11: Reception signal selector program according to the embodiment of the present invention
Claims (1)
ル信号に分割し、それぞれを第１〜第ｎの伝送路に並列
伝送し、受信側で受信した該第１〜第ｎの分割信号を合
成して原テレビ信号に復原するテレビ信号の分割伝送に
おいて、 送信側には、フィールド単位、ライン単位または画素単
位のブロックに分けてテレビ信号を送信する同期信号抽
出回路（１３）を設け、 受信側には、分割伝送されたディジタル信号の一部に、
途中伝送路で欠落や誤りが発生し、誤り訂正復号の可能
限界を超えた場合に、該分割信号に替えて正常な他の分
割信号で補間して信号合成する手段（１４）と、正常な
他の分割信号からクロックを抽出する手段（１５）とを
設けることを特徴とするテレビ信号の分割伝送装置。[Claims] A television signal is divided into first to nth (n≧2) digital signals on the transmitting side, each of which is transmitted in parallel to the first to nth transmission paths, and the receiving side receives the corresponding digital signals. In divided transmission of a television signal in which the first to nth divided signals are combined and restored to the original television signal, the transmitting side has a synchronization signal that transmits the television signal divided into blocks of field units, line units, or pixel units. An extraction circuit (13) is provided, and on the receiving side, a part of the divided and transmitted digital signal is
means (14) for interpolating and combining signals with other normal divided signals in place of the divided signals when a loss or error occurs in the transmission path and exceeds the possible limit of error correction decoding; 1. A divided transmission apparatus for a television signal, comprising means (15) for extracting a clock from another divided signal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61116460A JPS62272632A (en) | 1986-05-20 | 1986-05-20 | Division and transmission equipment for television signal |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61116460A JPS62272632A (en) | 1986-05-20 | 1986-05-20 | Division and transmission equipment for television signal |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62272632A true JPS62272632A (en) | 1987-11-26 |
Family
ID=14687662
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61116460A Pending JPS62272632A (en) | 1986-05-20 | 1986-05-20 | Division and transmission equipment for television signal |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62272632A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0556413A (en) * | 1991-08-28 | 1993-03-05 | Nec Corp | Picture transmission equipment |
| JPH0955925A (en) * | 1995-08-11 | 1997-02-25 | Nippon Telegr & Teleph Corp <Ntt> | Picture system |
| JPH09214932A (en) * | 1996-01-30 | 1997-08-15 | Nippon Telegr & Teleph Corp <Ntt> | Image device and image communication system |
| US6563875B2 (en) | 1987-12-30 | 2003-05-13 | Thomson Licensing S.A. | Adaptive method of encoding and decoding a series of pictures by transformation, and devices for implementing this method |
| JP2006279550A (en) * | 2005-03-29 | 2006-10-12 | Kddi R & D Laboratories Inc | Video transmitting device and receiving and reproducing device therefor |
| JP2008048444A (en) * | 2007-09-21 | 2008-02-28 | Kddi Corp | Multi-route image receiving apparatus |
| WO2008075608A1 (en) * | 2006-12-20 | 2008-06-26 | Nec Corporation | Transmission system, transmission device, reception device, signal transmission method, and program |
-
1986
- 1986-05-20 JP JP61116460A patent/JPS62272632A/en active Pending
Cited By (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6563875B2 (en) | 1987-12-30 | 2003-05-13 | Thomson Licensing S.A. | Adaptive method of encoding and decoding a series of pictures by transformation, and devices for implementing this method |
| US6661844B2 (en) | 1987-12-30 | 2003-12-09 | Thomson Licensing S.A. | Adaptive method of encoding and decoding a series of pictures by transformation, and devices for implementing this method |
| US7020204B2 (en) | 1987-12-30 | 2006-03-28 | Thomson Licensing | Adaptive method of encoding and decoding a series of pictures by transformation, and devices for implementing this method |
| JPH0556413A (en) * | 1991-08-28 | 1993-03-05 | Nec Corp | Picture transmission equipment |
| JPH0955925A (en) * | 1995-08-11 | 1997-02-25 | Nippon Telegr & Teleph Corp <Ntt> | Picture system |
| JPH09214932A (en) * | 1996-01-30 | 1997-08-15 | Nippon Telegr & Teleph Corp <Ntt> | Image device and image communication system |
| JP2006279550A (en) * | 2005-03-29 | 2006-10-12 | Kddi R & D Laboratories Inc | Video transmitting device and receiving and reproducing device therefor |
| JP4510678B2 (en) * | 2005-03-29 | 2010-07-28 | 株式会社Ｋｄｄｉ研究所 | Video transmission device and video transmission / reception playback device |
| WO2008075608A1 (en) * | 2006-12-20 | 2008-06-26 | Nec Corporation | Transmission system, transmission device, reception device, signal transmission method, and program |
| JP2008048444A (en) * | 2007-09-21 | 2008-02-28 | Kddi Corp | Multi-route image receiving apparatus |
| JP4510861B2 (en) * | 2007-09-21 | 2010-07-28 | Ｋｄｄｉ株式会社 | Multi-path image receiver |
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