JPS62269363A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To improve characteristic through reduction and equalization of source resistance and also improve reliability through flatness of interlayer insulation film by forming a MOS memory element of double layered gate structure. CONSTITUTION:An N-type buried layer 2 is provided on a semiconductor substrate 1, a P-type epitaxial layer 3 is formed thereon, an N-type source region 5 is formed at the bottom part of a groove 4 formed within such epitaxial layer 3, and an N-type drain region 12 is formed on the surface of epitaxial layer 3 at the surroundings of groove 4. Moreover, a first gate oxide film 6 is formed on the inner surface of groove 4, floating gate 7 is formed in the adjoining area of such gate oxide film 6, a second gate oxide film 8 is formed on the side surface of such floating gate 7, and a control gate 9 is formed in the adjusting area of such second gate oxide film 8. A word line 10 is stacked on the control gate 9 and is then covered with a protectin oxide film 11 and interlayer insulation film 13.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor memory devices, and in particular to programmable read-only memories (EPROMs) with floating gates.
Regarding.

[Conventional technology]

Conventionally, an EPROM has been proposed in which the gate electrode of a MOS transistor is constructed in two layers, consisting of a floating gate and a control gate to constitute a memory element! has been done. That is, as shown in FIG.
Gate 1 - Oxide film 32. Floating Day 133. Second
A gate oxide film 34 and a control gate 135 are formed in layers, and a source region 36 and a drain region 37 are formed at positions sandwiching these gates 33 and 35. The source region 36 is mutually connected to the source region of each TA element,
Connections are made to the power (ground) line for every few elements. Further, an interlayer insulating film 38 is formed to cover each of the gates 33 and 35, and an aluminum wiring 39 as a digit wire is connected to the drain region 37 through a contact hole opened in the interlayer insulating film 38.

[Problem that the invention seeks to solve]

In this type of memory element, information is written by channel hot electron injection or avalanche injection into the floating gate 33, but the writing speed at this time is greatly influenced by the resistance of the source region 36. For this reason, a configuration is adopted in which the source region 36 that interconnects each memory element is connected to a power supply (ground) line every several memory elements (several bits) for grounding.

Therefore, an area of a contact diffusion layer is required for making this connection, which is disadvantageous for miniaturization and high integration of elements. There is also the problem that the source resistance of a memory element that is farther away from the contact I section increases, and the write speed in the t1 element is reduced.

Furthermore, since the gate is configured in two layers, the interlayer insulating film 3
A step is formed on the surface of the aluminum wiring 39, and the reliability of the upper layer aluminum wiring 39 is lowered. Specifically, the interlayer insulating film 38 is reflowed, but this raises the temperature of the steam treatment and requires a long treatment time.

[Means for solving problems]

In the semiconductor memory device of the present invention, the source resistance of the element is reduced and made uniform to improve characteristics, and the interlayer insulating film is planarized to improve reliability.

In the semiconductor memory device of the present invention, a first gate oxide film, a floating gate, a second gate oxide film, and a control gate are laterally stacked on the inner surface of a trench formed in a semiconductor substrate, and the bottom surface of the trench is A source region connected to the buried layer of the substrate is formed in the groove 1-r(ii
I? 1. A MOS type with a two-layer gate structure in which a drain region is formed around J. (Constitutes the element.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

1 to 3 are diagrams showing one embodiment of the present invention,
FIG. 1 is a bottom view, and FIGS. 2 and 3 are cross-sectional views taken along lines AA and BB in FIG. 1, respectively.

As shown in the figure, a memory element of a semiconductor memory device includes an N-type buried layer 2 provided on a semiconductor substrate 1, a P-type epitaxial layer 3 formed thereon, and a groove 4 formed in this epitaxial layer 3. Floating gates 7 and control gates 9 are arranged in the horizontal direction. That is, groove 4
An N-type source region 5 is formed at the bottom of the trench 4, and an N-type drain region 12 is formed at the surface of the epitaxial layer 3 around the groove 4. In addition, a first groove is provided on the inner surface of the groove 4.
A gate oxide film 6 is formed, and a floating gate 7 is formed adjacent to this. Furthermore, a second gate oxide film 8 is formed on the side surface of this floating gate 7, and a control gate 9 is formed adjacent to this.

A word line IO is formed in layers on this control gate 9, and is covered with a protective oxide film 11 and an interlayer insulating film 13. A contact hole 15 is formed in this interlayer insulating film 13, and a digit line 14 connected to the drain region 12 is extended in a direction perpendicular to the word line 10.

Next, a method for manufacturing a memory element having the following second configuration is shown in FIG. 4(a).
The manufacturing steps will be explained in the order of manufacturing steps using cross-sectional views of ) to (k). Here, the same figures (e) and (f) show cross-sectional structures along the BB line in FIG. 1, and the others show cross-sectional structures along the AA line in FIG. 1.

First, as shown in the figure (a), an N-type impurity is introduced into the surface of a silicon substrate 1 of P or Nl type to form an N-type buried layer 2, and this upper layer is doped with P to a thickness of 2 to 3 μm. Grow the layer 3 of the type Ephitaxia soyal. Then, the C epitaxial layer 3 is etched to form a groove 4 (~1.5 μm) with a depth that does not reach the N-type buried layer 2, using the photoresist 20 patterned in a lattice pattern as a mask. Open. Furthermore, using the photoresist 20 and the polymer 21 generated when forming the groove 4 as a mask, N such as arsenic is injected into the groove.
N type impurity ions are implanted to reach the N type buried layer 2.
A type source region 5 is formed.

Next, after removing the photoresist 20 and the polymer 21, the grooves 4 are formed by thermal oxidation as shown in FIG.
A first gate oxide film 6 is formed on the inner surface. Further, the first polycrystalline silicon film 22 is grown over the entire surface by chemical vapor deposition. At this time, the thickness of the polycrystalline silicon film 22 in the groove 4 is adjusted so that the polycrystalline silicon film 22 is not completely buried in the groove 4.

After that, an N-type impurity such as phosphorus is added to the first polycrystalline silicon film 2.
2 to reduce resistance.

Next, the first polycrystalline silicon film 22 is anisotropically etched, leaving the first polycrystalline silicon film 22 only on the side surfaces of the groove 4 as shown in FIG. Configure as.

Thereafter, this floating gate 7 is thermally oxidized to form a second gate oxide film 8 on the surface.

Next, a second polycrystalline silicon film 23 is formed again by chemical vapor deposition to fill at least the inside of the trench 4,
By introducing N-type impurities into the film to lower its resistance and then performing anisotropic etching, the second polycrystalline silicon film 23 is left only in the groove 4 and the control gate 9 is removed, as shown in FIG. Form.

Next, as shown in the figure ((1), a groove 24 having a depth reaching the N-type buried layer 2 is formed in a direction perpendicular to the groove 4. When forming this groove 24, a photoresist (not shown) is used. Of course, it goes without saying that an insulating film such as silicon oxide is deposited on the entire surface by chemical vapor deposition method '1q, and the dirt is etched away by isotropic etching. An insulating film 25 is buried only in the groove 24 as shown in ).The insulating film 25 insulates and isolates the memory elements from each other.

After that, 11; j control game 1! I J=
- After removing the natural oxide film, a metal film or a third polycrystalline silicon film is deposited as shown in FIG.
form. Then, a protective oxide film 11 is formed by thermal oxidation, and then an N-type impurity is ion-implanted to form an 11 twin region 12.

Thereafter, an interlayer insulating film 13 is formed on the entire surface, a contact hole 15 is opened, and aluminum wiring in a desired pattern is formed to form a digit line 14, thereby completing a plurality of memory elements arranged in a matrix. be done.

Therefore, according to this memory element, since the source region 5 is formed at the bottom of the trench 4, it vertically overlaps with the drain region 12, reducing the area occupied by the source and allowing miniaturization and high integration of the memory element. It is possible to aim for Furthermore, since the source region 5 in each element is connected to the low resistance N-type buried layer 2 directly below, the source resistance is reduced and there is no variation in writing speed between the elements.

Furthermore, with this configuration, the profile in the depth direction can be freely controlled when forming the epitaxial layer 3, so writing efficiency can be improved by, for example, increasing the concentration near the drain region 12.

On the other hand, since the word line 10 is only protruded from the surface of the substrate on which the element is formed, the level difference can be reduced, and the reflow process for flattening the interlayer insulating film 13 can be performed at a lower temperature and in a shorter time. This prevents an adverse effect on the source/drain regions, etc., and improves the reliability of the upper layer digit cotton 14.

FIGS. 5(a) to 5([) are cross-sectional views showing an embodiment in which the minus part of the above-mentioned memory element is modified, in the order of manufacturing steps.

In addition, the same reference numerals are attached to the same or equivalent parts as in FIG. 4 in the figure.

First, by the same process as in FIGS. 4(a) and 4(b) described above, the first polycrystalline silicon film 22 is left only on the side surfaces inside the groove 4, and the floating gate 1 is formed as shown in FIG. 5(a). 7
form.

After that, as in FIGS. 4(e) and 4(f), the groove 4 is
A groove is formed in a direction perpendicular to
By performing the step of burying the insulating film 25, the insulating film 25 is also buried in the trench 4, as shown in FIG. 5(b).

Next, a photoresist 26 is formed to open the groove 4 as shown in FIG.

After that, as shown in the same figure (d), the first polycrystalline silicon 11g
A second gate oxide film 8 is grown on 22 and the exposed surface of the source region 5 by thermal oxidation, and then a second polycrystalline silicon film 23 is grown over the entire surface by chemical vapor deposition. N-type impurities are introduced into this second polycrystalline silicon film 23 to lower its resistance.

Next, etching is performed using the flat I resist 27 as a mask, leaving the second polycrystalline silicon film 23 only on the groove 4, and forming control gates 1 to 9, as shown in FIG. 2(e). This control gate 9 is continuous in a direction perpendicular to the plane of the paper, and therefore, a portion of the two sides thereof is configured as a word line 10A.

Hereinafter, by performing the same process as in Fig. 4, <r> in the same figure
The above element can be completed as shown below.

In this embodiment as well, the same effects as in the previous embodiment can be obtained.

〔Effect of the invention〕

As explained above, the present invention provides a structure in which a first gate oxide film is formed on the inner surface of a trench formed in a semiconductor substrate.
5. A second gate oxide film and a control gate are laminated laterally, and a source region connected to the buried layer of the substrate is formed at the bottom of the trench, and a drain region is formed around the top of the trench. Because of this, it is possible to lower the resistance of the source that goes into each memory element, improve the writing speed, and prevent variations in the writing speed. In addition, only a word line connected to the control gate is protruded on the semiconductor substrate, and low temperature in the planarization process of the interlayer insulating film is required.
It is possible to shorten the time, prevent adverse effects on device characteristics, and improve the reliability of upper layer wiring.

[Brief explanation of drawings]

Fig. 1 is a plan view of an embodiment of the present invention, Fig. 2 is a sectional view taken along line AA in Fig. 1, Fig. 3 is a sectional view taken along line BB in Fig. 1, and Fig. 4(a). -(fτ) are cross-sectional views showing the manufacturing method of the device of the present invention in the order of steps, FIGS. FIG. 3 is a cross-sectional view of the structure. 1... Silicon substrate, 2... N-type buried layer, 3...
P-type epitaxial layer, 4... Groove, 5... Source region, 6... First gate oxide film, 7... Floating gate, 8... Second gate oxide film, 9... Contact ]
・Roll gate, 10, IOA...word line, 11・
...Protective oxide film, 12...Drain region, 13...
Interlayer insulating film, 14... Digit line, 15... Contact hole, 20... Photoresist crystal silicon film, 23... Second polycrystalline silicon film,
24... Groove, 25... Insulating film, 26.27... Photoresist, 31... Semiconductor substrate, 32... First
Gate oxide film, 33...Floating gate, 34
...Second gate] - Oxide film, 35... Control gate, 36... Source region, 37... Drain region, 38... Interlayer insulating film, 39... Digit line. Fig. 1 Fig. 2 Towards So-Zuzu Drunk Fig. 3 Fig. 6

Claims (2)

[Claims] (1) A first gate oxide film, a floating gate, a second gate oxide film, and a control gate are laterally stacked on the inner side of a trench formed in a semiconductor substrate, and the bottom of the trench is filled with a substrate. 1. A semiconductor memory device comprising a source region connected to a trench, and a drain region formed around the upper surface of the trench to constitute a MOS type memory element having a two-layer gate structure. (2) The control gates are interconnected by word lines extended on the surface of the semiconductor substrate, contact holes are formed in the interlayer insulating film formed on the word lines, and digit lines are connected to the drains through the contact holes. 2. A semiconductor memory device according to claim 1, wherein said word line extends in a direction perpendicular to said word line.