JPS62269350A - Semiconductor integrated circuit and manufacture thereof - Google Patents

Abstract

PURPOSE:To contrive to improve the high-speed efficiency and the yield of a semiconductor integrated circuit by a method wherein a plurality of semicon ductor chips with a circuit formed thereon are arranged on a substrate, these chips are filled with an insulative resin and wirings, by which the chips are 4 mutually connected, are provided thereon. CONSTITUTION:A plurality of semiconductor chips 20 with such a circuit block as a logic circuit, an RAM circuit or an ROM circuit formed thereon are arranged and adhered on an Si substrate 11, gaps between the chips 20 are filled with an insulator layer 12 consisting of insulative resin and also, the substrate surface is flatly formed being covered the chips 20 with the insulator layer 12. Connecting pads 13; which consist of a metal, such as Al, are positioned at the peripheral parts of the substrate and are used for connection with the outside; and wirings 14; by which the chips 20 are mutually connected and the chips 20 and the pads 13 are connected; are formed thereon. Thereby, the aptitude to speedup, which is the feature of a wafer scale IC, is succeeded intact and moreover, as non-defectives only can be used for the chips 20, the insurance of the yield of material becomes easier.

Description

[Detailed Description of the Invention] [Summary] In a multi-conductor integrated circuit with an expanded integration scale, a plurality of semiconductor chips each having an Ill path formed therein are arranged on a base board,
By filling this with insulating resin and providing wiring to connect the chips to each other, it is possible to achieve high speed and easily maintain manufacturing yield.

[Industrial application field]

The present invention relates to a structure of a semiconductor integrated circuit with an expanded beam stacking scale.

Electronic devices generally have many [
It has a configuration in which 0 circuits are combined and connected. And its functions require simplicity and speed.

Due to the complexity, the scale of the circuit board is 11 (1)
1. In order to increase the speed, it is necessary to shorten the length of the connection wiring.

Semiconductor integrated circuits (ICs) are widely used to meet the above requirements, and there is a desire for further expansion in the scale of construction, which is the scale of circuit combinations. And part 1
〃It's for one person! It is important to ensure I-building yield.

[Problems to be solved by the prior art and the invention] In order to assemble and connect many circuits, conventional ICs with limited circuits are mounted on a mounting board, for example, a 7th A method has been adopted in which it is shown in the plan view of the figure.

In the figure, 1 is a mounting board, and 2 is a logic circuit IC, RAM-IC, )'? mounted on the board l. OM-IC
These are conventional ICs.

The substrate 1 is a printed wiring board made of, for example, synthetic resin and on which wiring is previously formed.

The IC2 has a configuration in which an IC chip 2a with a circuit embedded therein is packaged and a lead terminal 2b is led out, and the lead terminal 2b is connected to the wiring of the substrate 1 and coupled to the phase t1''.

The IC port configured as shown in the figure is because IC2 has a built-in circuit such as 11+1 for interfacing with other circuits, and the wiring length becomes longer because the interval between the IC chips 2a and 11 becomes larger. For the sake of Hatake
*There is a drawback that the conversion is lowered.

As a measure to eliminate this drawback, the size of the IC chip is increased to the size of a wafer, and all of the circuits included in the above-mentioned 1C board are formed on one chip, reducing the stacking scale to 1.
For example, a wafer scale IC as shown in the top view of FIG. 8 has been proposed.

In the same figure, ゛(, j3 is a wafer that will become one semiconductor chip, 4 is a circuit block formed in η-ha31- in which M circuits, ROM circuits, etc. are respectively deposited on the logic circuit 1/8.1 pin). , and one circuit block 4 is placed on the above IC board (IC2).

The circuit blocks 4 are arranged with mutual spacing much smaller than the corresponding spacing in the Ic hoard, and are connected to each other by wires 41 (not shown). The wiring has a structure similar to that of an ordinary IC-1 knob, is formed in a fine pattern, and is directly led out from the circuit elements in the circuit board 4.

The wafer scale IG for this purpose is the circuit block 4.
It becomes possible to omit the buffer circuit mentioned earlier,
Combined with the shortening of the wiring length between four phases and one circuit block, it is suitable for high speed.

However, since various circuits are formed, the number of manufacturing steps increases, and as the number of circuit blocks 4 increases, there is a problem that the manufacturing yield decreases exponentially.

[Means for solving problems]

(The problem described in - is that the substrate has a plurality of semiconductor chips on which circuits are formed and an insulating layer that fills the gaps between the chips and covers the chips, and wiring that connects the chips. This problem is solved by the Ic of the present invention provided on the insulating layer.

In addition, there is a step of arranging and bonding a plurality of semiconductor chips on which circuits are formed on a substrate, and filling the gaps between the bonded chips using a fluid insulating resin and covering the chips with resin. The problem is solved by the manufacturing method of the present invention, which includes a step of solidifying to form an insulating layer with a flat surface, and then forming a wiring on the insulating layer to connect the vaginal chips. .

[Effect]

The IC with the above configuration is the same as the wafer scale IG mentioned earlier.
It can be considered that the circuit block 4 in is replaced with the above-mentioned semiconductor chip, and the suitability for the +Mi speed increase, which is a feature of the wafer scale IC, is inherited as is.

Furthermore, it is possible to appropriately select and mix semiconductor chips such as silicon (Si) and compound semiconductors such as gallium arsenide (GaAs), thereby improving the IC function compared to wafer scale ICs. is possible.

In addition, in manufacturing, it is possible to separately manufacture the above-mentioned semiconductor chips and arrange the good ones on the substrate, so it is easy to ensure the yield as an IC.

The present invention uses an IC with this configuration as a BIC (1ioad
Scale Integrated C1rcit)
It was named.

r Example] Hereinafter, FIGS. 1 to 4 will be used for examples of Ic (Ic) according to the present invention, and the manufacturing method θ, - according to the present invention.
An example will be described using FIGS. 5 and 6.

The same symbols refer to the same symbols throughout the drawings.

Figures 1 and 2M are invention 1c (+3Ic), respectively.
FIG. 3 is a schematic plan view ia) and a schematic side sectional view fbl of the first and second embodiments, and FIG. 3 is a partial side sectional view illustrating a chip incorporated in the embodiment.

Further, FIG. 4 is a schematic side sectional view of an example of a package for the tenth embodiment of the present invention.

+3 IC, which is the first embodiment shown in FIG.
Logic circuit, RAM circuit, R
A plurality of semiconductor chips 20 on which circuit blocks such as OM111 circuit blocks are formed are arranged and bonded, and an insulating layer 12 made of polyimide is bonded to the chips 20 in an insulating resin plate.
Fill the gap between the phases t1' and cover the chip 20 one by one to make the surface flat.
l1, etc., in the peripheral area (17 placed for connection with the outside, I1 and V connection baths 1 and 13, nap 2o phase L1 question and chip 20 paso) between -13 The wiring 14 connecting the two is formed in a wiring layer like the J'7fs IC chip.

131C, which is the second embodiment shown in FIG. The difference is that PMSS (silylated polymethylsilsesdio+thane) is used as the material for the insulating layer 12. Further, the P/N3 is located in the frame 151- via the insulator 1-12.

The following explanation will be given below (1, 1, and 4) since 1ffl was applied to both the first and second embodiments.

In other words, in the diagram? IW8, but wiring 14.0>
.

As shown in FIG. 3, the chip 20 includes a semiconductor substrate 21F, necessary circuit elements (1-transistor, etc.) 22, and a wiring ξ and a spring 2 for connecting the circuit elements 22, as shown in FIG.
3 and an insulating layer 24 are formed on the surface, and a relay bat 26 for connecting the wiring 14 to the wiring 23 by providing a contact l-$25 on the surface, and a relay bat 26 arranged around the chip 20 so that the chip 20 can be inspected under heavy conditions. Positioning marks (not shown) are provided for visually confirming the precise positions of the measuring vane F27 and the chip 20 from the direction F. As shown in Note F (because the wiring 14 is connected to the circuit element 22, the HASO circuit is omitted as in the circuit block 4 of the wafer scale IC described above).

Each of the chips 20 arranged on the substrate 1-
In order to realize the desired function of the 3 IC, a material made of Si or a compound semiconductor such as GaAs is appropriately selected.

The reason why the material of the substrate 11 was made of Si was to prevent the substrate 11 from warping due to heat generation during operation, since most of the chip 20 is made of Sj, and the thermal expansion coefficient of both Other lumber I may be used as long as the balance can be maintained. The material of the frame 15 in the second embodiment is Si/rubber, but it is combined with the substrate 11 based on the same concept as 4).

The BIC configured in this way can be regarded as replacing the circuit board 20 in a wafer scale IC with a chip 20, and the suitability for increasing the speed of 114I, which is a characteristic of a wafer scale IC, is inherited as is. However, since the material of the chip 20 is selected to be suitable for realizing the desired function, it is possible to improve the function compared to the case of a wafer scale IC.Furthermore, a good quality metal plate is used for the chip 20. Therefore, it is easy to ensure manufacturing yield.

Note 131 C: is preferably used in a regular package, and FIG. 4 shows an example of this.

In the same figure, the back side of the substrate 11 (HIC is heat dissipating) is bonded to the back side of the substrate 31 with high conductivity, and the burner 113 is connected to the output bin 32 (the heat dissipation part consists of 11). The pad 33 for internal connection (for connection) and the pad 33 for internal connection connected thereto are connected by a wire 35 to the pad 33 of the vano cage side wall 34, which is IM attached to the back surface of the base of the heat dissipation fin 31, and a lid 36 is attached to the side wall 34 and sealed. 1) - has been done. In this package, the entire back surface of the board 11 is covered by the radiation fins 3.
Since it is bonded to 1, it is possible to obtain an extremely excellent cooling effect by 1 layer.

In addition, the 13 IC of this configuration can be used as a unit of module, and by connecting the first few stacked connection baths l'14 to the phase, it is possible to form an IC with a larger circuit integration scale. .

Note that although polyimide was used in the former and PMSS was used as the material for the insulating layer 2 in the above embodiment, both materials can be used for both.

Hereinafter, embodiments of the BIC according to the present invention have been described. Next, examples of the manufacturing method according to the present invention will be described below.

FIG. 5 is a sectional view (al to tC) of the Ln forward side of the first embodiment of the manufacturing method of the present invention, and shows the case of manufacturing +3 IC shown in FIG.

That is, in FIG. 5, first [see diagram fat], the substrate 11
Semiconductor chips 20 are arranged and bonded to 1-. The chips 20 used are manufactured separately and tested (obtained as non-defective products).

The bonding of the chip 20 is performed by attaching, for example, a lVa group element such as titanium (Ti) or zirconium (Zr) to the chip 20.
This is done by depositing it on the back surface of the chip, pressing it onto the substrate 11, and heating it from the substrate 11 side with a lamp or laser beam to turn it into a silicide (-). Chip 2 can be silicided without raising it to 111+ temperature, for example, 500°C or higher.
It is effective for injury prevention 11- of 0.

In addition, the gap between chip 2 ( ) phase n is (multiple insulator layers 1
In order to facilitate the formation of 2, it is desirable to make it as narrow as possible, for example, 0.11 mm below.

Next, [see Figure fbl jjQ), the gap between the chip 20 phase 17 is filled using an insulating resin (in this case Boliimi 1-) having a flow → iJ+ l'l, the chip 20 is covered with 1(), and the surface is covered with I( After flattening, the resin is solidified to form an insulating layer 12.
form.

In order to reliably fill the gaps and make use of the AI surface, a good method is, for example, to drop fluid polyimide in a vacuum atmosphere and apply a uniform wind IE to the vibrated surface. If the gaps in the 20-phase U are large or small, or if all the gaps are large, first wet the entire surface with a polyimide with a low viscosity. It is better to fill in the large gaps that have become insufficiently filled.

Note that applying the above air pressure is also effective in preventing the thickness of the 1000 sliver 201 in the insulator layer 12 from becoming excessively large.

Next, [see Figure fcl], connection pads 13 and wiring 14 are formed on the insulator layers] 2 , . This has j
Any conventional photolithography technique may be used. That is, first, a contact window 25 is opened to expose the relay pad 26 (shown in the figure) of the chip 20, and the material for the wiring 14 is deposited by a sputtering method or a method such as a wafer method, and this is patterned. Slightly (31st). During this patterning, by using the alignment marks provided on the nap 20, even if there is some error in the arrangement position of the chips 20, the error can be compensated for.

When the wiring 14 has multiple layers, the same material as the insulator layer 12, ie, polyimide, may be used for interlayer insulation.

Thereafter, the desired 13 IC is completed by performing banishing in the same way as a normal IC chip.

FIG. 6 is a side sectional view (ill to ffl) of the second embodiment of the 'J manufacturing method of the present invention, and shows the case of manufacturing B I G shown in FIG. 2.

That is, in FIG. 6, first [see figure ta+], the substrate 11
Place the substrate 11a of a size that allows cutting out the PI, O8 (
A plurality of bright spots on the periphery of the substrate 11a are fixed to the reinforcing plate 16 using an adhesive 17 made of Boli Ladder Organos.

This fixing is done by attaching the P L OS to the fixing location and attaching it to the substrate 1.
It is sufficient to harden PLO3 by heating it to about 500° C. while pressing 1a.

Next, the frame 15 is sprayed onto the substrate 11a using Pl and O8 (see figure (bl)). This is on the back of frame 15 I)
1. Apply LOS and heat cure it while pressing it onto the substrate 11a. This heat curing hardens the substrate 11a.
Go with it for i′ ζ 1) Good.

Then [see figure icl], the base% inside the box 15]
a Semiconductor chips 20 are arranged and bonded on the sheet. The chip 20 used is a good chip similar to that of the first embodiment.

PMSS is used to bond the chip 20. Immediately, PMSS dissolved in a solvent to a concentration of about 20% is spin-coated on the substrate 118 side to form an adhesive film 12a with a thickness of about 1 μm,
The chip 20 is pressure-bonded to the substrate lj side and heated to 400 to 500° C. using a lamp or laser beam. PMS
S is -l-t7g melted and then hardened to fix the chip 20. Heat-cured I) MSS does not melt when reheated.

It is desirable that the gap between the chips 20 be as narrow as possible, as in the case of the first embodiment.

Next, using PMS S dissolved in a solvent to a concentration of about 30%, as in the case of the first embodiment, the gap between the chip 20 and the frame 15 was filled, and the chip was removed. 20 and the A side of frame 15, about 1
The solvent is released by heating to 50°C, and the PMSS is cured by heating to approximately 450°C, resulting in an insulator with a flat surface.
-12 is formed.

At this time, since the PMSS is accompanied by a volume reduction, this step is repeated until the surface becomes thick. In the initial process, cracks may occur in the PMSS in the large gap to be filled, but this does not pose a problem because the cracks are filled with the L culm that is repeated later.

Then, in the same manner as in the first embodiment, connection pads 13 and wiring 14 are formed on the insulating layer 12-H (see Fig. te+).
to form. However, the opening of the contact window 25 is formed by active ion etching (RI) using oxygen plasma.
It is preferable to use B) and use AI as the mask material.

[See Figure ifl] After performing passivation (not shown), the board 11a is separated from the reinforcing plate 16, and the outer periphery of the frame 15 is cut with a laser beam to form the board 11, and a desired BIC is formed. Complete.

In both of the above-mentioned embodiments, only non-defective chips are used for the chip 2o, and unstable techniques are not used throughout the entire process, so it is extremely easy to ensure a manufacturing yield.

Regarding the bonding of the chip 20, although the 2+1@ method has been described, the method is not limited to the combinations of the above embodiments, and any method can be arbitrarily selected.

The same applies to the material of the insulating layer 12 (polyimide and PMSS).

Further, the reinforcing plate 16 described in the second embodiment is for preventing the board 11 from being damaged until the BIC is completed, and may be used as necessary.

〔Effect of the invention〕

As explained below, the configuration of the present invention has the effect of providing an IC that can increase the scale of integration and achieve high speed with a high manufacturing yield.

[Brief explanation of the drawing]

FIG. 1 is a schematic plan view ta+ and a schematic side cross-sectional view (BL) of the first embodiment of the RC according to the present invention, FIG. b), Fig. 3 is a partial side view illustrating the depth incorporated in the embodiment, Fig. 4 is a schematic side sectional view of the IC embodiment of the present invention without showing an example of a cage, and Fig. 5 is a schematic side sectional view of the IC embodiment of the present invention. The culm forward side cross-sectional view of the first embodiment of the manufacturing method is fat~(cl, Figure 6 is the forward side cross-sectional view ta+~ffl of the second embodiment of the manufacturing method of the present invention, and Figure 7 is an illustration of an IC boat. FIG. 8 is a plan view illustrating the wafer scale 10. In the figure, ] is a mounting board, 2 is a conventional IC, 3 is a wafer, 4 is a circuit unit, and 11 is an IC of the present invention. 11 is the substrate for cutting, 12 is the insulating layer, 12a is the adhesive film, ]3 is the connection bat, 14 is the wiring, 15 is the frame, 16
is a reinforcing plate, +711-adhesive, 20 is a semiconductor chip, 21 is the semiconductor grass of 20, 22 is a circuit element,
23 is the wiring of 20, 24 is an insulating layer, 25 is a contact window, 26 is a relay vane, 27 is a measurement bath], 31 is a radiation fin, 32 is an output pin,
33 is a connection bat, 34 is a package side wall,
35 is a wire, and 36 is a lid.

Claims (1)

[Claims] 1) A substrate having a plurality of semiconductor chips on which circuits are formed and an insulating layer that fills gaps between the chips and covers the chips, and has wiring connecting the chips. A semiconductor integrated circuit characterized by being provided on the insulating layer. 2) A process of arranging and bonding a plurality of semiconductor chips with circuits formed thereon on a substrate, filling the gaps between the bonded chips using a fluid insulating resin, and covering the chips with the resin. manufacturing a semiconductor integrated circuit, comprising the steps of solidifying to form an insulating layer with a flat surface, and then forming wiring connecting the chips on the insulating layer. Method.