JPS6226920A - Timing generator - Google Patents

Abstract

PURPOSE:To obtain a timing generator excellent in extending performance and general-purpose applications such as ease of timing design and ease of external setting change of timing period by using a selection circuit to select a delay circuit externally, thereby obtaining plural periods of timings. CONSTITUTION:A ring counter 100 having a stage number (delay circuit number) corresponding to the maximum period among desired timing periods consists of a selection circuit 103 selecting any of stage outputs by an external command to input the result to the 1st stage of the ring counter, and a OR circuit 101 receiving plural outputs of delay circuits corresponding to the pulse change point and an inverse delay circuit 102. As the input of the OR circuit 101, the output of the stage corresponding to the position of the desired timing change (0 to 1 or 1 to 0) is selected as the input and the inverse delay circuit 102 changes the logic state only with logical 1 level of logical sum. Thus, the timing period is decided according to the number of stage and the pulse change is decided by the position of the delay circuit. Moreover, the period is changed optionally by the selection circuit 103 up to the total number of the delay circuits externally.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a timing generation device comprising a periodic valve star.

[Summary of the Disclosure] This specification and drawings describe a ring counter that can change the number of stages in a timing generation device consisting of a pulse train having periodicity, and a stage of the ring counter at a position corresponding to a changing point of the pulse train. It has an inverting delay circuit whose logic state is inverted when the logical sum of the output becomes "1", and by changing the number of stages of the ring counter from outside the timing generator, different cycle timings are generated. Discloses a timing generation device that can perform the following steps.

[Prior Art J Conventionally, circuit timing design has been a big problem for those involved in logic circuit design. That is, the circuit operation required for each individual circuit is different, and the timing design has to be devised one by one to meet this requirement.

Binary counter circuits have been used from time to time to assist in timing generation. Since this generates a wide variety of different signal waveforms as shown in FIG. 1, it is possible to use a convenient one of these signals. However, the signal generated by the counter circuit is 2
Only double period signals such as double, quadruple, eight times...
This can only be applied to a few cases, and generally, flip-flops, gates, etc. are used to process and transform several signals to create the desired timing signal.

In other words, there is no standard approach to timing design; much is left to the qualifications of the designer.

Furthermore, when an unexpected circuit change occurs in a circuit that has been painstakingly created, and the timing has to be modified, the timing modification of one part of the circuit may affect another part. Designers are often troubled by this contradiction.

[Problems to be Solved by the Invention] The present invention has been made in view of the above-mentioned problems of the prior art, and has versatility and expansion in that timing design is easy and timings with different periods can be easily generated. Our goal is to provide a timing generator with rich functionality.

Means for Solving Problem E] As a means for achieving the above-mentioned problem, for example, the timing generation force method and device of the embodiment shown in FIG. The ring counter lOO having the number of stages (delay circuits) has a selection circuit 103 which selects one of the outputs of each stage according to an external instruction and inputs it to the first stage of the ring counter. It consists of an OR circuit lO1 which inputs a plurality of outputs of corresponding delay circuits, and an inverting delay circuit 102.

1 action" In the configuration shown in FIG.
1""→"O") is selected as the input, and the logical sum of the logical sum circuit lot is "1".
”, the inverting delay circuit 102 changes its logic state. Therefore, the timing period is determined according to the number of stages, and the change in the pulse is determined according to the position of the delay circuit input to the OR circuit 101. , the period can be arbitrarily changed externally by the selection circuit 103 up to the total number of delay circuits.

[Example] Hereinafter, an example of the present invention will be described in detail using the drawings.

Basic Operation> First, FIG. 3(a) shows a ring counter circuit which is a basic type for timing generation applied to the embodiment. What is a ring counter? In general, the shift I/output 4M of a shift register circuit is returned to the shift input of the same shift register circuit, forming a ``ring-shaped'' flip-flop (hereinafter referred to as F/F) string. It derives its name from its presence.

The ring counter shown in FIG. 3(a) is particularly characterized in that only one stage is preset to logic "1" at the start of operation.

FIG. 3(b) shows a state transition table when a clock is input to the water ring counter. At the start of operation (at preset),
It is assumed that the only logic "1" is set in the first stage Q1 of the ring counter. As shown in the figure, each time a clock is input, a unique logic "1" (-1) circulates through each stage of the ring counter.

An example of a timing generation circuit> FIG. 4(a) shows a specific circuit diagram of an embodiment of the present invention, in which the output of any two stages (Q7, Q9) of the ring counter 11 described above is The signal is input to an OR circuit, and further input to a half-inverting flip-flop circuit (hereinafter referred to as F/F) 20 including an OR circuit 2.

A combination of these exclusive OR circuits and an inverting F/F is an example of the structure of the inverting delay circuit shown in FIG.

Now, the condition for OR circuit 1 to output logic "1" to TXI is that any one of the ring counter stages input to OR circuit 1 becomes logic "1" (Q7+
Q9). That is, this is determined by the movement of "the only logic t" in the explanation of the ring counter in FIG. 3(a). Therefore, the tt of the exclusive OR circuit 2
The conditions for I force TY1 to be °“l” are when the output T1 of F/F 20 is °°l” and TXI is 0”, or when T1 is °O°° and TXI is “1” It's either time.

In other words, T1 is changed from °゛O'° to "1" at a certain timing.
'', the output of the stage corresponding to that timing may be input to the OR circuit.

Also, once F/F20 is set, the ltj of the OR circuit
As long as the force TX is 0′°, TYI is l″′,
F/F 20 remains set. That is, if T
If you want the timing when 1 changes from °l″ to °0″,
The output of the F/F of the stage corresponding to that timing is
Just input it to the R circuit.

Keeping in mind the above-1-, Fig. 4(b) Time Chart I
・Explain while referring to. Q7. which is the output of stage l and stage 3. Q9 is input to OR circuit 1. Therefore, the output of the OR circuit 1 indicated by TXI in the figure is only when the movement of the logic "1" in the ring counter just approaches stage l or stage 3.
Then, the final timing Kawauchi T1 inverts the state with a delay of l clock from this logic "1" output in the OR circuit 2.If the initial state of the F/F 20 is O°', then The timing wave ( ) T1 which is the output is the stage difference between Q7 and Q9, that is, 3-1-
The logic becomes "1" for a period of two clocks. The same waveform is repeated every five clock cycles, which is the cycle of the ring counter.

Since the output timing signal T1 passes through F/F20, OR
The output will be delayed by one clock from circuit 1, but
On the contrary, it has the effect of outputting a clean "" waveform from which the jitter components generated at the time of operation transition of the OR circuit and the υ1 other OR circuit 2 are removed.

(Timing Design) The following is a description mainly of the operation. Next, the procedure for designing the embodiment to suit various timing generation applications will be described.

As shown in Figure 5 (a) to (d), ■ First, draw a time chart of the required timing waveform (Figure 5 (a)), (?) Next, how many clocks are required for one cycle? Figure out.

In this example, one cycle is 5 clocks. Then, the ring counter with the same number of stages is arranged (Fig. 5(b)). Next, the number of timing signals required (in this example, 2
) only OR circuits 3 and 5, exclusive OR circuit 4.6 and F/
F 21 and 22 are arranged (Fig. 5 (C)), and the output signals of the ring counter stage corresponding to the rising - L and falling positions of the timing signal are selected, and for the timing signal A, From Figure 5(a), Ql a
+Qx 5 is input to the OR circuit 3, and in the same manner for the timing signal B, Q14. QlB is input to the OR circuit 5. (Figure 5(d)).

According to the procedure 4- below, any periodic waveform timing signal can be mechanically converted from a time chart to a circuit diagram. The quality is high. Furthermore, if it is desired to change the timing signal, it is sufficient to simply change the input signal to the OR circuit to the output of another stage tJ5 of the link counter, unless a change of 9 cycles is required. That is, it is not only inexpensive and highly flexible for changes, but also has no effect on other circuits since the ring counter itself is not changed. Even if it becomes necessary to change the cycle and the number of stages of the link counter changes, the effect this will have on others can be easily predicted.

Furthermore, if the timing signals are from the same clock system, the same ring counter can be shared, as shown in Figure 5(d), by simply adding an OR circuit, an exclusive logic circuit, and an F/F circuit. Create multiple timing signals at low cost 1
Let's make 11.

As shown in Fig. 6, if this small-scale and inexpensive exclusive OR circuit and F/F circuit are not shared and are configured in each circuit block as much as possible, it is possible to change the timing in one circuit block. This eliminates the need for other circuit blocks to be affected by this.

Now, if we look at the operation delay time in the timing circuit of the embodiment, only the OR circuit, exclusive OR circuit, and clip-flop 1 need to operate while one clock advances.
The number of stages is limited, and even from this point of view, considerably high-speed operation is possible. In other words, the star elements forming the loop of the link counter circuit are only F/Fs, and each F/F
Since F operates synchronously with a clock, it operates simultaneously and no glitches occur. In the case of using the binary counter in the conventional example described above, the number of circuit stages is large due to the occurrence of carry in the counter circuit, and the operation delay is large, but according to this embodiment, the operation speed can be improved.

Furthermore, in this embodiment, a more accurate timing signal can be formed by making the step value smaller, that is, making the clock faster, and correspondingly increasing the number of link counter stages.

However, the timing generation circuit of this embodiment is also suitable for high-speed logic circuits and measuring circuits such as high-precision pulse generators.

Modification Example 1> Now, in the above embodiment, a timing signal that makes a single change within a cycle is generated, but by further digging, it is possible to generate a timing signal that makes a single change within a cycle, or It is also possible to make the following change.

This can be done 41 by increasing the number of inputs to the aforementioned OR circuit and using as inputs the outputs of the stages of the ring counter. An example of this is shown in FIG. 7(a).

In FIG. 7(a), the tll force Q2 of the link counter
0. Q22. Q23. At each change in Q24, the output TX2 of the OR circuit 15 changes, thus creating a timing signal T that makes multiple changes within one cycle as shown in the figure.
2 is obtained. As can be easily understood from FIG. 7(a), even if there are multiple inputs to the OR circuit 15, the timing of the output T2 changes at the change timing of the F/F corresponding to the input, so it is extremely You can intuitively grasp the timing.

<Modification 2> Now, in Fig. 7(a), an even number of input signals (four in Fig. 7(a)) were used as inputs to the OR circuit, but when this is an odd number, , are shown in FIGS. 8(a) and 8(b).

In FIG. 8(b), a timing waveform T3 obtained in the same manner as in Modification 1 is shown, and the first cycle day (i.e., odd-numbered cycle) and the second cycle day (i.e., even-numbered cycle) An inverted timing signal is obtained in the U, and is suitable for cases where an inverted timing signal is required in the U. Conversely,
If the signal is inverted every half cycle, there is no need to prepare a ring counter with the number of stages for one cycle.
It only takes half a cycle.

<Variation 3> Next, in the present invention, since the output timing signal can be easily changed, an embodiment can be considered in which it is possible to obtain a modified timing signal generator. The elements that determine the timing signal for case B are the number of stages of the ring counter, which determines the period of the output timing signal, and the input to the OR circuit, which determines the timing signal's convergence and position of change. choice of faith,
There are two points.

Therefore, for these two elements, one is equipped with a selection circuit that selects which output from the stage of the ring counter should be inverted and returned to the input of the link counter.
On the other hand, a selection circuit for selecting one or more outputs from among the outputs of each stage is arranged, and an IG is used to issue selection instructions to these selection circuits from the outside. It is possible to obtain a timing signal generation circuit.

This example is not shown in FIG. The ring counter circuit formed by the shift registers of Q40...Q44..., the OR circuit, the exclusive OR circuit, and the F/F that samples the output are the same as described above. However, yellow selection circuits shown at 33, 36, . . . in the figure are further added to this.

The translation selection circuit could use a City 11 multiple l/cusa. The selection circuit 33 selects any one of the outputs of each stage of the ring counter and feeds it back to the first stage as a shift-in signal. Which stage output is fed back can be freely controlled. In other words, this is a function that allows the number of stages of the ring counter to be freely increased or decreased, and as described above, the cycle of the output timing can be made variable.

Further, other selection circuits 34 to 36 are also arranged at a stage before the input of the OR circuit. Furthermore, it is possible to freely control which stage output of the ring counter is selected as the OR circuit input. In other words, this makes the inter-temporal position and pulse width of the river timing signal variable.

(16 rivers of PLA) As another example, instead of using the selection circuit as described above to change the connections necessary to obtain various timing signals,
It is also possible to use PLA (programmable logic array). In other words, one of the characteristics of each of the embodiments described above is that a large number of gates, F/Fs, etc. are arranged in an orderly manner. In a case like Modification 3, it is extremely P L
It shows the east, which is suitable for A.

As is well known, a PLA is a basic F- type that has a large number of logic circuits such as gates and F/Fs arranged inside it, and is sold commercially with some of the internal wiring of the circuits left unconnected.

In the field, this unconnected part (one point on the lattice) can be blown by a fuse blowing method that selects and blows the fuse at each lattice point, or by destroying the pace-emitter junction at one point in each grid with a large current to create a diode. This is a new semiconductor device that can be programmatically connected and fixed from the outside using a destructive method. An embodiment of PLA according to the present invention is shown in FIG. 1O. In the figure, the X marks are locations where wiring instructions can be given from the outside.

In the figure, the setting of the number of stages of the ring counter, which determines the cycle of the generated timing signal, is determined by the stage output of the ring counter to which the input to the first stage is connected.
By making this connection shown by the mark programmable, it is possible to create timing generation circuits with different cycles by preparing multiple identical PLA devices.

Also, the time position of the timing waveform and the pulse "1" are determined by which stage output of the ring counter the input to the OR circuit 41, 43.45 is connected to, and
By making the marked wiring programmable, the timing time position and pulse Il can be adjusted using the same PLA device.
l different timing generation circuits can be created. OR circuit 4
Although two examples are shown in FIG. 10 as inputs to 1, 43, and 45, more complex timing can be generated as described above by using 3 inverted 1-1 or an odd number of inputs.

<Characteristics of Examples> As explained below in 1-1, the characteristics of each of the above-mentioned Examples are as follows.
The circuit configuration is in an orderly and arranged form m1, and it is useful for designing timing circuits, increasing or decreasing the number of stages of a ring counter, selecting inputs for an OR circuit, OR circuits, exclusive OR circuits, and/or F/ When F increases or decreases, adaptability increases, and if T is rich in expansion P1, the possibility of stagnation increases.

That is, according to this embodiment, if a timing generation circuit can be mechanically created from a time chart for any periodic timing waveform, it has a higher degree of versatility.

In addition, by increasing the number of stages of the ring counter and adding OR circuits, exclusive OR circuits, and sampling F/F circuits, the period can be lengthened, or multiple timing signals can be generated from one ring counter circuit. It has the extensibility that can be used.

Furthermore, a large number of ring counter stages j! are included in the OR circuit. By inputting a single force, it is possible to generate a timing signal with a complex waveform, and it has great applicability.

Furthermore, by inputting an odd number of signals to the OR circuit, it is possible to create a timing waveform that is reversed every half cycle.

Further, since the number of circuit stages involved in the operation delay of the circuit of the embodiment is small from π, there is an advantage that high-speed operation is possible.

Furthermore, by speeding up the clock and adding the number of ring counter stages, there is an advantage that a more accurate timing waveform can be obtained.

Further, since the timing can be changed by a slight wiring change, there is an advantage that a variable timing generation circuit can be obtained using the selection circuit.

Furthermore, by implementing PLA because the circuit configuration is arranged and the timing can be easily changed, a versatile timing generation device that can be programmed in the field can be obtained. I can do things.

N conversion of circuit elements〉 As an example of the inverting delay circuit of FIG.
In the figure, the explanation was made using a combination of a so-called D type F/F and an exclusive logic circuit, but a so-called J- type F/F is used and the OR circuit output is transferred to this J- type F/F.
A similar effect can be obtained by inputting J and F of /F to the input terminal f.

Further, the F/F used in the ring counter is just one example, and the same effect can be obtained with other delay elements such as a monostable multi-layer or a delay line.

[Effects of the Invention] As explained above, according to the present invention, the circuit configuration is in an orderly and arranged form, so timing design is easy, and furthermore, the timing period can be easily changed from the outside. This provides a timing generator that is highly expandable and versatile.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of a basic embodiment, Fig. 2 is a timing chart of the t11 force of a conventional binary counter, and Figs. 3 (a) and (b) are basic diagrams applied to an embodiment according to the present invention. Figures 4(a) and 4(b) are circuit diagrams of the embodiment and their timing charts; Figures 5(a) to (d) are diagrams showing the ring counter circuit and state transitions at each stage. FIG. 6 is a diagram showing how the timing generation circuit of the embodiment generates a plurality of timings to drive a plurality of circuit blocks. Figures (a) and (b) are the circuit diagram and timing chart of modification 1, Figures 8 (a) and (b) are the circuit diagram and timing chart of modification 2, and Figure 9 is the circuit diagram of modification 3. Circuit Diagram FIG. 10 is a circuit diagram when PLA is applied to the embodiment. In the figure, 1.3, 5, 7, 9, 11, 13, 15° 17.40,
41.43.45...OR circuit, 2゜4.6,8,1
0, 12, 14, 16.1B, 19.42.44.46
. . . exclusive logic circuit, Ql-Q44 . . . flip-flop.

Claims (4)

[Claims] (1) In a timing generation device that generates timing consisting of a pulse train having a predetermined period, the timing generation device includes either a shift circuit formed by alternately coupling the inputs and outputs of a plurality of delay circuits, or the delay circuit. It consists of a selection circuit that selects one output, and by inputting the output of the selection circuit to the first stage of the shift circuit, it can be set to "1" or "0".
a ring counter that cyclically shifts the information of ``, an OR circuit that inputs the output of the delay circuit corresponding to the change point of the pulse, and an OR circuit that inputs the output of the OR circuit, and when the logical sum is ``1''.
”, and by selecting the delay circuit by the selection circuit from outside the timing generation device, timing having a plurality of periods can be obtained. A timing generator characterized by: (2) The timing generator according to claim 1, wherein the output of the inverting delay circuit is set to a desired timing. (3) The inverting delay circuit is a JK flip-flop, and the output of the OR circuit is inputted to the J and K inputs of the JK flip-flop. The timing generator described in section. (4) The inverting delay circuit consists of an exclusive OR circuit and a flip-flop whose logic state changes depending on the input, and the input of the exclusive OR circuit is connected to the output of the OR circuit and the output of the flip-flop. A timing generation device according to claim 1 or 2, characterized in that: