JPS6226925A - Timing generator - Google Patents

Abstract

PURPOSE:To obtain a timing generation method and its apparatus with ease of timing design and excellent in general-purpose applications and extending performance by adopting a so-called programmable logic array (PLA) for a selection circuit. CONSTITUTION:The titled apparatus consists of a ring counter 100 having the number of stages corresponding to a desired timing period, a OR circuit 101 inputting any plural stage outputs in the ring counter 100 and an inverse delay circuit 102. The OR circuit 101 selects an output of a stage corresponding to a position of a desired timing change (0 to 1 or 1 to 0) as the input and the inverse delay circuit 102 changes its logic stage only when the OR of the OR circuit 101 is logical '1'.

Description

DETAILED DESCRIPTION OF THE INVENTION FIELD OF APPLICATION IN INDUSTRY-1- The present invention relates to a timing generation device consisting of a pulse train having periodicity.

[Summary of the Disclosure] This specification and drawings describe a timing generation device consisting of a pulse train having periodicity, in which a ring counter having the number of stages corresponding to one period is used, and the stage output of the ring counter corresponding to a changing point of the pulse train is calculated. Take the logical sum of
The logical sum is input to the inverting delay circuit, and the logical sum is °“l
``By inverting the logic state of the inversion delay circuit when ``, we disclose a technique to obtain the timing of the number of stages for pulse trains having different periods.

[Prior Art] Traditionally, those involved in logic circuit design have had the inclination to devise timing designs that match the required circuit operations for each individual circuit. .

Binary counter circuits have been used from time to time to assist in timing generation. Since this generates a wide variety of different signal waveforms as shown in FIG. 1, it is possible to use a convenient one of these signals. However, the signal generated by the counter circuit is 2
Only double period signals such as double, quadruple, eight times...
This can only be applied to a few cases, and in most cases, flip-flops, gates, etc. are used to add and transform several signals to create the desired timing signal.

In other words, there is no standard way to design timing, and much of it is left to the qualifications of the designer.

Furthermore, the circuit that we have painstakingly created,
When an unexpected circuit change occurs and the timing has to be modified, the timing modification of one part of the circuit will affect the other parts, and designers often suffer from this contradiction. .

[Problems to be Solved by the Invention] The present invention has been made in view of the above-mentioned problems of the prior art.It is an object of the present invention to provide a timing generation method and a device thereof that are easy to design timing and are highly versatile and expandable. The task is to

Means for Solving Problem L] As a means for achieving problem L, for example, the timing generation method and device of the embodiment shown in FIG. It consists of a counter 100 and an OR circuit 101 which inputs any one or more stage outputs in the ring counter 100, and an inverting delay circuit 102.

[Function] In the configuration shown in FIG.
The output of the stage corresponding to the position of
'' only, the inverting delay circuit 102 changes its logic state.

[Example] Hereinafter, an example of the present invention will be described in detail using the drawings.

<Basic Operation> First, FIG. 3(a) shows a ring counter circuit which is a basic type of timing generation device applied to the embodiment. A ring counter generally returns the shift output signal of a shift register circuit to the shift input of a rotary shift 1/register circuit, forming a "ring-shaped" series of flip-flops (hereinafter referred to as F/F). It derives its name from.

The ring counter shown in FIG. 3(a) is particularly characterized in that only one stage is preset to logic "1" at the start of operation.

FIG. 3(b) shows a state transition table when a clock is input to this ring counter. At the start of operation (at preset),
It is assumed that a unique logic "1" is set in the first stage Q1 of the ring counter. As shown in the figure, each time a clock is input, a unique logic "1" circulates through each stage of the ring counter.

<An example of a timing generation circuit> FIG. 4(a) is a small diagram of a specific circuit diagram of an embodiment of the present invention. is input to the OR circuit, and further input to a half-inverting flip-flop circuit (hereinafter referred to as F/F) 20 including an exclusive OR circuit 2.

A combination of these antagonistic OR circuits and an inverting F/F is an example of the structure of the inverting delay circuit shown in FIG.

The condition for OR circuit 1 to output logic "l" to TXI is that one of the ring counter stage outputs input to the OR circuit becomes logic "l'" (Q7+Q
9). That is, this is determined by the movement of the logic t'' in the description of the ring counter in FIG. 3(a). Therefore, the output TYI of the OR circuit 2 becomes ’ is the output Tl of F/F20.
When is °°l′° and T X 1 is °°0″,
or when T1 is °°O'' and T x + is "t".

In other words, T1 changes from °0°' to "1" at a certain timing.
In order to do this, it is sufficient to input the output of the stage corresponding to that timing to the OR circuit 1.

Also, once F/F20 is set, the output T of the OR circuit
As long as XI is °゛0'', TYI is l'' and F/
F20 remains set. That is, if T1 is
If you want the timing from 1'' to 0'', you can input the output of the F/F of the stage corresponding to that timing to the OR circuit.

Keeping in mind the following, explanation will be given with reference to the time chart in FIG. 4(b). Q7. which is the output of stage l and stage 3. Q9 is input to the OR circuit. Therefore,
The output of the OR circuit shown as TXI in the figure is that the ``movement of logic 1'' in the ring counter is exactly at stage l]
7 is only logical when you reach stage 3.
′ is output. And the final timing output T1 is OR
In circuit 2, the state is inverted with a delay of l clock from this logic "1"' output.The initial state of F/F 20 is
O°", the output timing signal TI becomes logic "1" for the stage difference between Q7 and Q9, that is, the time corresponding to 3-1 = 2 clocks. After that, the ring counter -・The same waveform is repeated every 5 clock cycles, which is a cycle.

Since the output timing signal T1 passes through F/F20, OR
Will the output be delayed by one clock from circuit 1?
On the contrary, it has the effect of outputting a clean waveform from which chatter components that occur during operation transitions of the OR circuit and the exclusive OR circuit 2 are removed.

<Timing Design> The following is a description mainly of the operation. Next, a procedure for designing the embodiment to suit various timing generation applications will be described.

As shown in Figure 5 (a) to (d), ■ First, draw a time chart of the required timing waveform. Figure out.

In this example, one cycle is 5 clocks. Then, the ring counters having the same number of stages are arranged (FIG. 5(b)) L, 0).Next, OR circuits 3, 5 are arranged for the number of required timing signals (two in this example). , exclusive OR circuit 4.6 and F
/F 21 and 22 (Fig. 5 (C)), and select the output signal of the ring counter stage corresponding to the rising and falling positions of the timing signal, and for the timing signal A, From Fig. 5(a), Ql 3+
Qx5 is input to the OR circuit 3, and Ql4. QlB is input to the OR circuit 5. (Figure 5(d)).

According to the procedure described below, it is possible to mechanically convert any periodic waveform timing signal from a time chart to a circuit diagram. Highly versatile. Furthermore, if it is desired to change the timing signal, it is sufficient to simply change the input signal to the OR circuit to the output of another stage of the ring counter, unless the period needs to be changed. That is, it is not only inexpensive and highly flexible for changes, but also has no effect on other circuits since the ring counter itself is not changed. Even if it becomes necessary to change the cycle and the number of stages of the ring counter changes, the effect this will have on others can be easily measured.

Furthermore, if the timing signals are from the same clock system, the same ring counter can be shared, as shown in Figure 5(d), and by simply adding an OR circuit, exclusive OR circuit, and F/F circuit. Multiple timing signals can be generated at low cost.

As shown in Fig. 6, if this small-scale and inexpensive exclusive OR circuit and F/F circuit are not shared and are configured by providing S for each circuit block, it is possible to This eliminates the need for timing changes to affect other circuit blocks.

Now, if we look at the operation delay time in the timing circuit of the embodiment, only the OR circuit, exclusive OR circuit, and flip-flop 1 should operate while l clocks advance.
The number of stages is limited, and even from this point of view, considerably high-speed operation is possible. In other words, the elements forming the loop of the ring counter circuit are only the F/Fs, and each F/F
Since F operates synchronously with a clock, it operates simultaneously and no flitch occurs. In the case of using the binary counter in the conventional example described above, the number of circuit stages is large due to the occurrence of carry in the counter circuit, and the operation delay is large, but according to this embodiment, the operation speed can be improved.

Furthermore, in this embodiment, by making the step value smaller, that is, making the clock faster, and correspondingly increasing the number of ring counter stages, a more accurate timing signal can be formed.

However, the timing generation circuit of this embodiment is also suitable for high-speed logic circuits and measuring circuits such as high-precision pulse generators.

Modification Example 1 Now, the above embodiment was an example of generating a timing signal that makes a medium change within one period, but if we dig deeper into this, we can generate a timing signal that changes twice within a period or more. It is also possible to make changes in 1.

This can be done by increasing the number of inputs to the aforementioned OR circuit and using as inputs the outputs of the stages of the ring counter. An example of this is shown in FIG. 7(a).

In FIG. 7(a), the output of the ring counter Q20.
Q22. Q23. O at each change in Q24
The output Tx2 of the R circuit 15 changes, thus obtaining a timing signal T2 that makes a plurality of changes within one cycle as shown in the figure. As can be easily understood from FIG. 7(a), even if there are multiple inputs to the OR circuit 15, the timing of the output T2 changes at the change timing of the F/F corresponding to the input, so it is extremely intuitive. You can accurately grasp the timing.

<Modification 2> Now, in Fig. 7(a), an even number of input signals (four in Fig. 7(a)) were used as inputs to the OR circuit, but when this is an odd number, , are shown in FIGS. 8(a) and 8(b).

FIG. 8(b) shows the timing waveform T3 obtained in the same manner as Modification 1. This method is suitable for cases where a timing signal that is reversed at an intersection of 1 is required. Conversely, if the signal is inverted every half-cycle, there is no need to prepare a ring counter with the number of stages for one cycle, and only half a cycle is required.

<Modification 3> Next, in the present invention, since it is easy to change the output timing signal, an embodiment can be considered in which a variable timing signal generator can be obtained. In this case, the elements that determine the output timing signal are the number of stages of the ring counter, which determines the period of the output timing signal, and the selection of the input signal to the OR circuit, which determines the width and time position of the timing signal. , 02 points.

Therefore, for these two elements, one is provided with a selection circuit that selects which output from each stage of the ring counter should be inverted and returned to the input of the ring counter.
On the other hand, any one of the outputs of each stage -L
A variable timing signal generation circuit can be obtained by providing selection circuits for selecting the ij power and instructing the selection circuits to select from the outside.

An example of this is shown in FIG. A ring counter circuit formed by shift registers Q40...Q44...
The R circuit, the exclusive OR circuit, and the F/F for sampling the output thereof are the same as those described above, but selection circuits shown at 33, 36, . . . in the figure are added.

A commercially available multiplexer could be used as the selection circuit. The selection circuit 33 selects any one of the outputs of each stage of the ring counter and feeds it back to the first stage as a shift-in signal. Which stage output is fed back can be freely controlled. That is, this is equivalent to freely increasing or decreasing the number of stages of the ring counter, and as described above, the period of the output timing is made variable.

Further, other selection circuits 34 to 36 are also arranged at a stage before the input of the OR circuit. Furthermore, it is possible to freely control which stage output of the ring counter is selected as the OR circuit input. That is, this makes the time position and pulse width of the output timing signal variable.

<Application of PLA> As yet another embodiment, the connection changes necessary to obtain various timing signals can be made by using the selection circuit as described above.
It is also conceivable to use a PLA (programmable logic array). In other words, one of the characteristics of each of the embodiments described above is that a large number of gates and F/F caps are arranged in an orderly manner. Cases like Example 3 are extremely PLA
It shows that it is suitable for

As is well known, a PLA is an element with a large number of internal logic circuits such as gates and F/Fs, and is sold commercially with the internal wiring of the circuits in the following sections left unconnected.

In the field, select the unconnected portions (lattice points) of each grid point. - By the fuse blowing method, which selects and blows the fuse, or by the junction destructive force method, which destroys the base-emitter junction at each lattice point with a large current to create a diode, it is connected programmatically from the outside and hardened to f! This is a new semiconductor device. An embodiment of PLA according to the present invention is shown in FIG. 1O. In the figure, the X mark indicates a location where wiring instructions can be given from outside.

In the figure, the setting of the number of stages of the ring counter, which determines the period of the generated timing signal, is determined by which stage output of the ring counter is connected to the input to the first stage. , This connection shown by the X mark in the figure is set to program 11), and the same Pl, A device can be used for multiple devices, 6. By doing so, it is possible to create timing generation circuits with different periods.

The time position of the timing waveform and the pulse 11 are determined by which stage output of the ring counter the input to the OR circuit 41, 43, 45 is connected to. By doing so, P of times
Using the LA device, create a timing generation circuit with different timing positions and pulses [1]. However, if three scenes F1 or an odd number of scenes are used, more complex timing can be generated as described above.

I <Characteristics of the Examples> As explained above, the characteristics of each of the above examples are that the circuit configuration is in an orderly and arranged form, and the timing circuit design 1-, the number of stages of the ring counter It can be said that it is rich in adaptability and expandability by increasing or decreasing the number of circuits, selecting the input of the OR circuit, or increasing or decreasing the number of OR circuits, exclusive OR circuits, and/or F/Fs.

That is, this embodiment has high versatility in that it is possible to mechanically create a timing generation circuit from a time chart for any periodic timing waveform.

In addition, by increasing the number of stages of the ring counter and adding OR circuits, exclusive OR circuits, and sampling F/F circuits, the period can be lengthened, or multiple timing signals can be generated from one ring counter circuit. It has the ability to expand over time.

In addition, in the case where multiple ring counter stage outputs are input to an OR circuit, it is possible to generate a timing error with a complex waveform, which has great applicability.

Furthermore, by inputting an odd number of signals to the OR circuit, it is possible to create a timing waveform that is reversed every half cycle.

Further, since the number of circuit stages Is related to the operation delay of the circuit of the embodiment is small, there is an advantage that high-speed operation f1 is possible.

Furthermore, by speeding up the clock and adding the number of ring counter stages, there is an advantage that a more accurate timing waveform can be obtained.

Further, since the timing can be changed by a slight wiring change, there is an advantage that a variable timing generation circuit can be obtained using the selection circuit.

Furthermore, the circuit configuration or arrangement, and the ease of changing the timing in P1. By performing A, it is possible to obtain a versatile timing generation device that can be programmed in the field.

<Replacement of circuit elements> As an example of the inverting delay circuit shown in FIG. 1, the combination of a so-called D type F/F and an exclusive logic circuit was explained in FIGS. A similar effect can be obtained by using a so-called 1-type F/F and inputting the OR circuit output to the J and 2 input terminals of this J- type F/F.

Further, the F/F used in the ring counter is just one example, and the same effect can be obtained with other delay elements such as a monostable multi-layer or a delay line.

Effects of the Invention As described in 1-1, according to the present invention, the circuit configuration is in an orderly and arrayed form, so the timing is easy to set and old, and the timing is extensible and versatile. A method and device for generating the same are obtained.

[Brief explanation of the drawing]

Fig. 1 is a configuration diagram of a basic embodiment, Fig. 2 is a timing chart of the output of a conventional binary counter, and Figs. Figures 4(a) and 4(b) are circuit diagrams of the embodiment and their timing charts; Figures 5(a) to (d) are diagrams showing the ring counter circuit and state transitions at each stage. FIG. 6 is a diagram showing a circuit design method step by step. The timing generation circuit of the embodiment generates a plurality of timings and a plurality of circuit processors 1. Figures 7(a) and 7(b) are circuit diagrams and timing charts of modification 1, and Figures 8(a) and 8(b) are circuits of modification 2. 9 is a circuit diagram of modification 3, and FIG. 10 is a circuit diagram when PLA is applied to the embodiment. In the figure, 1.3, 5, 7, 9, 11, 13, 15° 17.40,
41,43.45...OR circuit, 2゜4.6,8,1
0, 12, 14, 16, 18. ．． 19.42.44.4
6... Exclusive logic circuit, Ql-Q44... Flip-flop.

Claims (4)

[Claims] (1) Consisting of a shift circuit formed by alternately coupling the inputs and outputs of a plurality of delay circuits, and a selection circuit that selects the output of any one of the delay circuits, the output of the selection circuit is sent to the first stage of the shift circuit. a ring counter that cyclically shifts information of "1" or "0" by inputting it to the circuit; an OR circuit that inputs one or more outputs of the delay circuit; and an OR circuit that inputs the output of the OR circuit; 1. A timing generation device comprising an inverting delay circuit that inverts a logic state only when the sum is "1", the timing generation device characterized in that the selection circuit is formed into a so-called programmable logic array (PLA). (2) The timing generator according to claim 1, wherein the output of the inverting delay circuit is set to a desired timing. (3) The timing according to claim 2, wherein the inverting delay circuit is a JK flip-flop, and the output of the OR circuit is inputted to the J and K inputs of the JK flip-flop. Generator. (4) The inverting delay circuit consists of an exclusive OR circuit and a flip-flop whose logic state changes depending on the input, and the input of the exclusive OR circuit is connected to the output of the OR circuit and the output of the flip-flop. The timing generator according to claim 2, characterized in that: