JPS62268150A - 半導体装置 - Google Patents

半導体装置

Info

Publication number
JPS62268150A
JPS62268150A JP61113006A JP11300686A JPS62268150A JP S62268150 A JPS62268150 A JP S62268150A JP 61113006 A JP61113006 A JP 61113006A JP 11300686 A JP11300686 A JP 11300686A JP S62268150 A JPS62268150 A JP S62268150A
Authority
JP
Japan
Prior art keywords
semiconductor element
conductive members
resin layer
conductive member
fixed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP61113006A
Other languages
English (en)
Other versions
JPH0560662B2 (ja
Inventor
Ryuichiro Mori
隆一郎 森
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP61113006A priority Critical patent/JPS62268150A/ja
Publication of JPS62268150A publication Critical patent/JPS62268150A/ja
Publication of JPH0560662B2 publication Critical patent/JPH0560662B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
    • H01L2224/321—Disposition
    • H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48257—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a die pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732—Location after the connecting process
    • H01L2224/73251—Location after the connecting process on different surfaces
    • H01L2224/73265—Layer and wire connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
    • H01L2224/8338—Bonding interfaces outside the semiconductor or solid-state body
    • H01L2224/83385—Shape, e.g. interlocking features
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/181—Encapsulation

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔産業上の利用分野〕 この発明は半導体装置特にＶＡ脂封止形半導体装置に関
するものである。
〔従来の技術〕
従来のこの種樹脂封止形半導体装置は、第４図および第
５図に示す如く構成されていた。即ち第４図および第５
図において、１は仮想線で示す封止例ＩＩ層、２は半導
体素子、３は樹脂層ｌ内から外部へ延在する導電部材、
４は半導体素子２が固着層５を介して固着される載置部
、６は半導体素子２と導電部材３を電気的に接続する内
部リード線である。
〔発明が解決しようとする問題点〕
この従来のものでは、封止樹脂層１から導電部材３が配
置された残りの部分に半導体素子賊置部４および半導体
素子２を配置しており、導電部材３と載置台３とが重な
り合わないよう構成さオ］ているので、半導体素子２が
大型化した場合、収納できなくなるという問題点があっ
た。
この発明はこのような従来のものの問題点を解消するた
めになされたもので、同じ大きさの封止樹脂層１によっ
て、より大型化した半導体素子２を収納できる半導体装
置を得ろことを目的とする。
〔間頭点を解決するための手段〕
この発明に係る半導体装置は、互に独立した複数の導電
部材に半導体素子を固着すると共に半導体素子と導電部
材を内部リード線で接続し、導電部材の一部を残して半
導体素子と共に樹脂層によって封止するようにしなもの
である。
〔作用〕
乙の発明における半導体素子は、導電部材に固着されて
いるので、従来のものと同一の外形寸法で大形の半導体
素子を収納することができろ。
〔実施例〕
以下第１図および第２図にもとづいてこの発明の一実施
例を説明する。即ち第１図および第２図において、３は
樹脂層１内で且つ半導体素子２の下部からＶＡ脂層１の
外部へ延在する導電部材、７は半導体素子２を導電部材
３上に固着するための絶縁性固着層である。なおその他
の構成は、従来のものと同様であるので説明を省略する
。
このように構成されたものでは、導電部材３が半導体素
子２の下部に重なりあうようになっているため、第４図
および第５図に示す従来のもののように導電部材３の配
置された部分が半導体素子２の収納部分に対して余分な
部分にならず、大型化した半導体素子２を小容積の封止
樹脂層１内に収納することができろ。
なおここで；ま半導体素子２を絶縁性固着層７を介して
導電部材３に固着しているが第３図に示すように選択さ
れた導電部材３１と半導体素子２を導電性固着層で固着
し、残りの導電部材３と半導体素子２を絶縁性間Ｍ層で
固着するよう構成してもよい。
〔発明の効果〕
上記のようにこの発明による半導体装置は、導電部材に
半導体素子を固着するようにしたもので、大形の半導体
素子を小さい外形寸法で収納できろ。
【図面の簡単な説明】
第１図はこの発明の一実施例を示す平面図、第２図は第
１図Ｉ−ＩＩ線断面図、第３図はこの発明の他の実施例
を示す平面図、第４図は従来の＋Ａ脂封止形半導体装置
を示す平面図、第５図は第４図■−■綿断面図である。 図中、１　’ｌｉ−封正樹脂層、２　Ｉｔ半導体素子、
３は導電部材、５ば絶縁性固着層、６は内部リード線、
７は導電性固着層である。 尚、図中同一符号は同−又は相当部分を示す。

Claims (3)

    【特許請求の範囲】
  1. （１）互に独立した複数の導電部材、これらの導電部材
    に固着される半導体素子、この半導体素子と上記導電部
    材とを接続する内部リード線、上記各導電部材の一部を
    残して半導体素子と共に封止する樹脂層を備えた半導体
    装置。
  2. （２）半導体素子は導電部材に絶縁性固着層によって固
    着されている特許請求の範囲第１項記載の半導体装置。
  3. （３）半導体素子は一部の導電部材には導電性固着層に
    よって固着されると共に残りの導電部材には絶縁性固着
    層によって固着されている特許請求の範囲第１項記載の
    半導体装置。
JP61113006A 1986-05-15 1986-05-15 半導体装置 Granted JPS62268150A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61113006A JPS62268150A (ja) 1986-05-15 1986-05-15 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61113006A JPS62268150A (ja) 1986-05-15 1986-05-15 半導体装置

Publications (2)

Publication Number Publication Date
JPS62268150A true JPS62268150A (ja) 1987-11-20
JPH0560662B2 JPH0560662B2 (ja) 1993-09-02

Family

ID=14601074

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61113006A Granted JPS62268150A (ja) 1986-05-15 1986-05-15 半導体装置

Country Status (1)

Country Link
JP (1) JPS62268150A (ja)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6382950U (ja) * 1986-11-17 1988-05-31

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6382950U (ja) * 1986-11-17 1988-05-31

Also Published As

Publication number Publication date
JPH0560662B2 (ja) 1993-09-02

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