JPS62267675A - Evaluating circuit for integrated circuit - Google Patents

Abstract

PURPOSE:To simultaneously execute each test of an integrated circuit by loading a monitor circuit which has constituted a ring oscillator by providing a pseudo adder by odd stages on a full adder of necessary states, on the integrated circuit, and evaluating a DC/AC characteristic. CONSTITUTION:A pseudo adder PFA 12 of one stage is inserted into full adders FA11-13 of three stages, by which a ring oscillating circuit which is loaded on an integrated circuit is constituted. When control signals (B, C) are (0, 1), a ring oscillating circuit whose phase is shifted by 180 deg. by one round is constituted. When fan-out of each stage is '1', an equivalent circuit of 4 gates is constituted. Accordingly, when a delay time of the circuit is divided by 4, a delay time of 1 gate is derived. When the control signals (B, C) are (1, 0), an equivalent circuit of fan-out 2 and '1' is formed. By passing through 2 gates in each stage, in the same way, when the delay time is divided by 4, a delay time at the time of passing through both one gate of fan-out 2 and one gate of fan-out '1' is calculated.

Description

[Detailed Description of the Invention] [Summary] A monitor circuit configured as a ring oscillator is mounted on an integrated circuit, and the DC/AC characteristics of the integrated circuit are evaluated.

[Industrial application field]

The present invention relates to a circuit for evaluating DC/AC characteristics of an integrated circuit, and particularly to a monitor circuit mounted on an integrated circuit.

[Conventional technology]

DC/AC testing of processed ICs involves checking normal/abnormal operation, operating point, operating speed, etc. while changing conditions, but as the scale of the IC increases, test items and The analysis of the test data obtained has become extremely complex, making it difficult and time-consuming to provide feedback on designs and processes.

Therefore, it has been adopted to include some kind of evaluation circuit in the IC. One of them is a full adder ring oscillator.

FIG. 6A shows the logic circuit configuration (EC
This figure shows an IC evaluation circuit using all L series gates, with one of its input terminals, A, used for signal transmission, and the other two, B and C, used as control terminals. A,
B'i has an input OR circuit 21 and an exclusive NOR circuit 22tl-, and the output of the exclusive NOR circuit n and the signal C
An exclusive OR circuit 24 and an OR circuit 24 whose inputs are . A carry CU is obtained as the output of an AND circuit 25 which receives the outputs of the OR circuit 21 and the OR circuit 23, and a sum value SU'z is obtained as the output of the exclusive OR circuit 24.

FIG. 6B shows a conventional monitoring ring oscillator constructed using this full adder FA and an inverter. Connect the carry terminal CUI of each FA to the A terminal of the next stage, and connect one FA
An inverter INVi is interposed between the carry terminal CU of the next FA and the A terminal of the next FA. Output is SU of one FA
Figures 6C and 6D show equivalent circuit configuration diagrams of a conventional ring oscillator for monitoring.

Conventional ring oscillators for monitoring use control signals (B, C
)t(0,1), the critical path is 1 and the 6th
As shown in Figure C, a ring oscillation circuit is configured with four gates with a fanout of 1 and one inverter. Control signals (B, c
)t(1,o), each stage of the full adder F'A has a critical path of 2 and a fanout of 2, but since inverters with a fanout of 1 are mixed,
It is difficult to separate the gate delay time when the fanout is 1 from the gate delay time when the fanout is 2.

[Problem that the invention seeks to solve]

In the conventional circuit, as described above, one of the input terminals of the full adder is used for transmitting all signals, and the other two are used as control terminals. However, if you change the level of the control terminal and change the FI (fan-in)/FO (fan-out) or critical path, the full adder may or may not work as an inverter. The configuration is such that an even number of adders are connected and an inverter is sandwiched between them.

However, if this is done, the FI (fan-in)/FO (fan-out) conditions will be disrupted at the inverter, making accurate evaluation impossible.

[Means for solving problems]

The present invention completely solves all of the above-mentioned problems by configuring at least one stage of the mimetic calculator according to the present invention to be sandwiched between full adders of appropriate stages.

That is, the present invention provides an integrated circuit evaluation circuit mounted on a semiconductor integrated circuit, which is composed of elements of the same design as the elements of the integrated circuit, and one of the input terminals is for signal transmission,
The other two are control terminals; one is a full adder in the required stage that outputs an input signal in response to a control signal; the other is a full adder with a similar configuration to the full adder, with one of the input terminals being for signal transmission; Two are control terminals, and the integrated circuit evaluation circuit is characterized in that the ring oscillator is formed by connecting an odd number of stages of mimetic calculators that output an inverted signal of an input signal in response to a control signal. This is what we provide.

[Effect]

In the monitor circuit of the present invention, the mimic calculator outputs an inverted output of the input signal, so there is no need for an inverter as in the past, and during testing, the bus is determined by the signal input to the control terminal, and fanout 1 and fanout 2 are used. It becomes possible to monitor two things.

〔Example〕

FIG. 1A shows a logic circuit level circuit diagram of a pseudo arithmetic unit PFA used in an embodiment of the present invention. In the figure, one of the input terminals, A, is used for signal transmission, and the other two, B and C, are used as control terminals. 1 is an OR circuit with an inverting gate, 2 is an exclusive NOR circuit, and each input terminal receives a signal A.

B inputs. The output of exclusive NOR circuit 3 and the output of OR circuit 3 whose inputs are signal C and the output of OR circuit 1 are ANDed.
It is input to circuit 5, and a carry signal CU is output as its output. The output of the exclusive NOR circuit 3 and the signal C are input to the exclusive NOR circuit 4, and the relationship between the signals of the control terminals B and C of the full adder FA, the carry output CU, the critical path, and the fanout is shown. ing. F.A.
, When the critical path is 1 for both PFA, the fanout is 1, and when the critical path is 2, the fanout is 2 and 1.

FIG. 1B shows a configuration diagram of this embodiment to which the pseudo arithmetic unit PFA and full adder FA are applied. The control input signals C and Bi are applied to the input terminals B and C of the full adders 11, 13, and 14 in each stage, and the signal C is commonly input to the B and C terminals of the 12 pseudo arithmetic units PFA. And each FA and P
A ring oscillator is constructed by inputting the carry output CU of the FA to the A terminal of the next stage, and an output signal is obtained from the SU output terminal of the PFA. One stage of PFA is inserted into three stages of FA as shown in FIG. When the control signals (B, C) are (0, 1), the FA has a critical path of 1 and outputs the same phase as the input signal A, and the PFA has a critical path of 1 and outputs an inverted output of the input signal A. A ring oscillation circuit is constructed in which the phase shifts by 180 degrees in one round. Then, the equivalent circuit shown in FIG. 1C having four gates with a fanout of 1 in each stage is constructed.

Therefore, by dividing by the circuit delay time t-4 calculated from the oscillation frequency of the ring oscillation circuit, the delay time of one gate is calculated.

Next, when the control signals (B, C) are (1, 0), each FA
The critical path is 2, the fanout is 2 and 1, and the same phase as the input signal A is output. Since an inverted output is produced, an equivalent circuit of fanouts 2 and 1 in the first diagram is formed. Since each stage passes through two gates, if you divide the delay time calculated from the oscillation frequency of this ring oscillation circuit by 4, it will pass through both one fanout 2 gate and one fanout 1 gate. The delay time is calculated.

FIG. 3 shows a transistor level circuit diagram of the full adder FA used in the embodiment of the present invention. Further, FIG. 4 shows a transistor level circuit diagram of the pseudo calculator PFA used in the embodiment of the present invention. The circuits of this pseudo calculator PFA and the full adder FA shown above are the same except for which transistor's collector the load resistor is connected to. Note that the reference voltage VRI shown in the figure is for controlling the constant current of the emitter, and the voltages VR2 and V
B2 determines the logic level of the upper and lower stages, respectively, and the full adder and the mimetic calculator are similar in this respect. In this way, the pseudo arithmetic unit PFA of this embodiment is the full adder FA and '
If the power supplies are connected in the same way and 9. PFA and FA are used to form a ring oscillator, the dependence on the power supply voltage, the voltage margin due to the process pattern size, the dependence of the noise margin, etc. will be the same υ, compared to the conventional Analysis is easier in the case of a ring oscillator using a PFA and an inverter.

FIG. 5 shows a planar configuration of a monitor circuit including a ring oscillator in which nine stages of full adders and one stage of mimetic adders are connected according to an embodiment of the present invention. The circuit of this embodiment is mounted on an integrated circuit, and during testing, a path is determined by a signal input to a control terminal, and two fanouts, fanout 1 and fanout 2, can be monitored. The significance of monitoring in this way is that in actual devices, fanout 1 and fanout 2 are connected in a complicated way, but for example, if you change the voltage, how will data be affected at the gate of fanout 1? There are cases where it is desired to separate how the data is affected by the gate, and in such a case, the circuit of this embodiment is particularly effective.

To operate the monitor circuit of this embodiment, it is easy to apply the power supply voltage, add an appropriate reference voltage, and observe the output waveform with an oscilloscope.
Tests (for example, at what voltage should the power supply be used for operation) and AC tests (for example, the relationship between power supply voltage and operating speed) can be performed at the same time.

In addition, if you perform a test using this monitor circuit before attaching the SPGC to the IC, obtain the reference voltages VRI to VR3, power supply voltage, control signal level, etc. in advance, and measure the device using those values, you can shorten the test time. .

That is, in the actual device, the circuit is the same as the monitor circuit, only the wiring is different, so the reference voltages VRI to vR3, power supply voltage, control signals, etc. are the same, and each Determining the gate operating margin will significantly reduce the actual test time.

〔Effect of the invention〕

As described above, according to the present invention, a DC test and an AC test of an integrated circuit can be performed at the same time. In addition, if a test using the circuit of the present invention is performed before attaching the 5PEC to the IC, the reference voltages VRI to vR3, power supply voltage, control signal values, etc. are obtained in advance, and the device is measured using those values, the test time can be shortened. It has the advantage of being

[Brief explanation of drawings]

Fig. 1A is a logic circuit diagram of a mimetic calculator used in an embodiment of the present invention, Fig. 1B is a configuration diagram of a monitor circuit using a ring oscillator in an embodiment of the present invention, and Figs. 1C and 1D correspond to control signals. The equivalent circuit configuration diagram of the monitor circuit of the example shown in FIG. 2A is the full adder FA.
FIG. 2B is a diagram showing the relationship between the critical bus and the number of fanouts; FIG. 3 is a transistor-level circuit diagram of the mimic calculator used in the embodiment of the present invention; Fig. 4 is a transistor level circuit diagram of the full adder used in the present invention and the conventional example, Fig. 5 is a diagram showing the integrated circuit mounting pattern of the monitor circuit of the embodiment of the present invention, Fig. 6A, Fig. 6B 6C and 6 are block diagrams of a monitor circuit using a conventional full adder and a ring oscillator.
FIG. D is an equivalent circuit configuration diagram of a monitor circuit using a conventional ring oscillator. A... Input signal (terminal) B, C... Control input (terminal) CU... Carry output terminal SU... Sum (addition result) output terminal FA... Full adder PFA... Mimicry calculator

Claims (1)

[Claims] An integrated circuit evaluation circuit mounted on a semiconductor integrated circuit, comprising elements of the same design as elements of the integrated circuit, having one input terminal and a control terminal for signal transmission,
It consists of a full adder of the required stage in which the input signal is transmitted to the output through a transmission path determined according to the control signal, and elements of the same design as the elements of the integrated circuit, and has a similar configuration to the full adder. , and an odd-numbered pseudo adder having one input terminal and a control terminal for signal transmission, and in which an inverted signal of the input signal is transmitted to the output through a transmission path determined according to the control signal. An integrated circuit evaluation circuit comprising a ring oscillator.