JPS62266880A - Semiconductor photodetector - Google Patents

Semiconductor photodetector

Info

Publication number
JPS62266880A
JPS62266880A JP61111259A JP11125986A JPS62266880A JP S62266880 A JPS62266880 A JP S62266880A JP 61111259 A JP61111259 A JP 61111259A JP 11125986 A JP11125986 A JP 11125986A JP S62266880 A JPS62266880 A JP S62266880A
Authority
JP
Japan
Prior art keywords
layer
type
region
ingaasp
avalanche
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61111259A
Other languages
Japanese (ja)
Inventor
Tsugunori Takahashi
鷹箸 継典
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61111259A priority Critical patent/JPS62266880A/en
Publication of JPS62266880A publication Critical patent/JPS62266880A/en
Pending legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L31/00Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof
    • H01L31/08Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors
    • H01L31/10Semiconductor devices sensitive to infrared radiation, light, electromagnetic radiation of shorter wavelength or corpuscular radiation and specially adapted either for the conversion of the energy of such radiation into electrical energy or for the control of electrical energy by such radiation; Processes or apparatus specially adapted for the manufacture or treatment thereof or of parts thereof; Details thereof in which radiation controls flow of current through the device, e.g. photoresistors characterised by at least one potential-jump barrier or surface barrier, e.g. phototransistors
    • H01L31/101Devices sensitive to infrared, visible or ultraviolet radiation
    • H01L31/102Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier
    • H01L31/107Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode
    • H01L31/1075Devices sensitive to infrared, visible or ultraviolet radiation characterised by only one potential barrier or surface barrier the potential barrier working in avalanche mode, e.g. avalanche photodiode in which the active layers, e.g. absorption or multiplication layers, form an heterostructure, e.g. SAM structure

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  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Electromagnetism (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Light Receiving Elements (AREA)

Abstract

PURPOSE:To improve unevenness in an avalanche multiplying region contingent to morphology without limiting a light receiving band and to accomplish improvement in quantum efficiency and improvement in characteristics such as noise reduction, by constituting a p-n junction and an avalanche multiplier layer with InGaAsP, which is a mixed crystal compound. CONSTITUTION:On the (100) surface of a p<+>type InP substrate 1 having impurity concentration of about 1X10<19>cm<-3>, an InP buffer layer 2 and a p<+>type InGaAsP region 3 are epitaxially grown sequentially by an LPE method and the like. This semiconductor layer is etched to a depth reaching the p<+>type InP buffer layer 2. A mesa region having a diameter of, e.g., about 100mum, is formed. Then, an InGaAsP multiplying layer 4 and an InGaAs light absorbing layer 5 are epitaxially grown. An n-side electrode 8 is formed on the light absorbing layer 5 by using gold germanium. A p-type electrode 7 is arranged on the back surface of the InP substrate 1 by using, e.g., gold zinc. When the region, which is held by the p<+>type InGaAsP layer 3 in the n-type InGaAsP layer 4 and the light absorbing layer 5, is made to be the avalanche multiplying region, morphology is alleviated, and contingent unevenness in impurity concentration distribution is decreased.

Description

【発明の詳細な説明】 〔概要〕 この発明は、アバランシホトダイオードにおいて、 pn接合及びアバランシ増倍領域を混晶化合物半ぷ体に
形成し、かつこれを光吸収領域の下に配設することによ
り、 受光帯域の制限を伴うことなく、モフォロジーに付随す
るアバランシ増倍領域の不均一性を改善し、量子効率、
雑音等の特性向上を達成するものである。
[Detailed Description of the Invention] [Summary] The present invention provides an avalanche photodiode in which a pn junction and an avalanche multiplication region are formed in a mixed crystal compound half body, and this is disposed below a light absorption region. This improves the non-uniformity of the avalanche multiplication region associated with morphology without limiting the receiving band, and improves the quantum efficiency and
This achieves improvements in characteristics such as noise.

〔産業上の利用分野〕[Industrial application field]

本発明は半導体受光装置、特に化合物半導体アバランシ
ホトダイオードの改善に関する。
The present invention relates to improvements in semiconductor light receiving devices, particularly compound semiconductor avalanche photodiodes.

光を情報信号の媒体とする光通信等において、光電流が
アバランシ降伏によって増倍されるアバランシホトダイ
オード(以下APDと略称する)は、光検知器の43号
対雑音比を改善する効果が大きい。
In optical communications where light is used as a medium for information signals, avalanche photodiodes (hereinafter abbreviated as APDs), whose photocurrent is multiplied by avalanche breakdown, are highly effective in improving the No. 43 noise ratio of photodetectors. .

石英系ファイバを伝送路とする波長1.3〜1.6−程
度の帯域には、インジウム燐/インジウムガリウム砒素
(燐) (InP/ InGaAs(P))系等の化合
物半導体APDが用いられるが、エピタキシャル成長に
よって形成されるその半導体基体になお後述の如き問題
点があり、その改善が必要とされている。
Compound semiconductor APDs such as indium phosphide/indium gallium arsenide (phosphorus) (InP/InGaAs(P)) are used for the wavelength band of about 1.3 to 1.6-wavelength using quartz fiber as the transmission path. However, the semiconductor substrate formed by epitaxial growth still has problems as described below, and improvements are needed.

〔従来の技術〕[Conventional technology]

従来のInP/ InGaAs (P)系APDは例え
ば第2図の模式側断面図に示す如き構造を有する。同図
において、11は1型1nP基板、12はn型1nPバ
ッファ層、13はn型1nGaAs光吸収層、14はn
型1nPウィンドウ層、15はp+型支受光領域17は
p側電極、18はn側電極である。
A conventional InP/InGaAs (P) based APD has a structure as shown in a schematic side sectional view of FIG. 2, for example. In the figure, 11 is a 1-type 1nP substrate, 12 is an n-type 1nP buffer layer, 13 is an n-type 1nGaAs light absorption layer, and 14 is an n-type 1nP substrate.
15 is a p+ type light supporting/receiving region 17 is a p-side electrode, and 18 is an n-side electrode.

このAPDに♂型InP5板11を正、p+型支受光領
域15負の極性とする高い逆バイアス電圧を印加して、
InGaAs光吸収層13内で入力信号光によって励起
された正孔を一次キャリアとするアバランシ増倍を、禁
制帯幅がInGaAs光吸収N13より大きいInPウ
ィンドウN14のρn接合下の領域で発生させる。
A high reverse bias voltage is applied to this APD to make the ♂ type InP5 plate 11 positive and the p+ type light receiving region 15 negative polarity.
Avalanche multiplication using holes excited by the input signal light as primary carriers in the InGaAs light absorption layer 13 is generated in the region below the ρn junction of the InP window N14 whose forbidden band width is larger than that of the InGaAs light absorption N13.

この従来例の半導体基体は通常液相エピタキシャル成長
方法(LPE法)により、げ型1nP基板11上にn型
1nPバッファ層12、n型1nGaAs光吸収層13
及びn型1nPウィンドウ層14を積層成長し、この層
14に例えばカドミウム(Cd)を深さ1乃至2−程度
に拡散してp+型支受光領域15形成している。
The semiconductor substrate of this conventional example is formed by a liquid phase epitaxial growth method (LPE method) on a barbed 1nP substrate 11, an n-type 1nP buffer layer 12, an n-type 1nGaAs light absorption layer 13, etc.
Then, an n-type 1nP window layer 14 is laminated and grown, and cadmium (Cd), for example, is diffused into this layer 14 to a depth of about 1 to 2-2 to form a p+ type light receiving region 15.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

前記の如きTnP / InGaAs (P)系APD
の半導体基体をLPE法などで成長したとき、その基板
の僅かなミスオリエンテーション(misorient
ation)によって、僅かな波状のうねりを表面に現
すモルフォロジー(morphology)が多くは数
lO−の間隔でInP成長層に発生し、更にこのモルフ
ォロジーに対応してその層内に不純物濃度の不均一な分
布を生じ易い。
TnP/InGaAs (P)-based APD as described above
When a semiconductor substrate is grown using the LPE method, a slight misorientation of the substrate
ation), a morphology in which slight wavy undulations appear on the surface occurs in the InP growth layer, often at intervals of several 1O-, and corresponding to this morphology, there is a non-uniform impurity concentration within the layer. Easy to cause distribution.

n型InPウィンドウ層14がこの様な状態となれば、
不純物濃度(伝導電子濃度)の高い部分ではアバランシ
降伏電圧が濃度の低い部分より低くなり、増倍率すなわ
ち受光感度が受光面内で不均一に分布し、量子効率の低
下や雑音の増大などを招いて大きい支障となっている。
If the n-type InP window layer 14 is in this state,
In areas with high impurity concentration (conduction electron concentration), the avalanche breakdown voltage is lower than in areas with low concentration, and the multiplication factor, that is, the light-receiving sensitivity, is distributed unevenly within the light-receiving surface, leading to a decrease in quantum efficiency and an increase in noise. This is a big hindrance.

〔鷹箸他:”InP APDにおけるアバランシ増倍の
不均一分布” (Inhomogeneous Dis
tribution of AvaIanche Mu
ltiplication in InP APDs)
Jpn、J、Appl、Phys、 Vol、23(1
984)、No、2参照〕(問題点を解決するための手
段〕 前記問題点は、半導体基板上に、第1導電型の混晶化合
物からなる第1の半導体層が選択的に配設され、 該第1の半導体層を埋め込んで、第2導電型の混晶化合
物からなる第2の半導体層が設けられ、該第2の半導体
層上に、該第1及び第2の半導体層より禁制帯幅が小さ
い第2導電型の第3の半導体層が設けられて、 該第3の半導体層を光吸収層、該第2の半導体層をアバ
ランシ増倍層とする本発明による半m体受光装置により
解決される。
[Takahashi et al.: “Inhomogeneous distribution of avalanche multiplication in InP APD”
Tribution of AvaIanche Mu
(ltiplication in InP APDs)
Jpn, J, Appl, Phys, Vol, 23(1
984), No. 2] (Means for solving the problem) The problem is that the first semiconductor layer made of a mixed crystal compound of the first conductivity type is selectively disposed on the semiconductor substrate. , a second semiconductor layer made of a mixed crystal compound of a second conductivity type is provided by embedding the first semiconductor layer, and a second semiconductor layer made of a mixed crystal compound of a second conductivity type is provided on the second semiconductor layer. A semi-m-body light receiving device according to the present invention, wherein a third semiconductor layer of a second conductivity type with a small band width is provided, the third semiconductor layer is a light absorption layer, and the second semiconductor layer is an avalanche multiplication layer. Solved by the device.

〔作 用〕[For production]

前記従来例においてモルフォロジーは2元化合物である
InPに多く発生し、混晶化合物であるInGaAs、
 InGaAsPではInPより溝かに少ない。他の砒
化ガリウム/砒化アルミニウムガリウム(GaAs/A
IGaAs)系等の化合物半雁体においても同様である
In the conventional example, morphology mostly occurs in InP, which is a binary compound, and InGaAs, which is a mixed crystal compound,
InGaAsP has fewer grooves than InP. Other gallium arsenide/aluminum gallium arsenide (GaAs/A
The same applies to compounds such as IGaAs).

この事実から、pn接合及びアバランシ増倍層を混晶化
合物であるInGaAsPとすればモルフォロジーの問
題が大幅に改善されるが、仮に前記従来例の構造でウィ
ンドウ層14をInGaAsPとするならば、^poの
受光帯域の短波長側がこのウィンドウ層14によって制
約される。
From this fact, if the pn junction and the avalanche multiplication layer are made of InGaAsP, which is a mixed crystal compound, the problem of morphology can be greatly improved. However, if the window layer 14 is made of InGaAsP in the structure of the conventional example, The short wavelength side of the po light receiving band is restricted by this window layer 14.

本発明によれば後に例示する実施例の如く、pn接合か
ら見て光入射方向に光吸収層を配置し、混晶化合物アバ
ランシ増倍層による受光帯域の短波長側の制約を排除す
る。
According to the present invention, as in the embodiments to be exemplified later, a light absorption layer is disposed in the direction of light incidence when viewed from the pn junction, thereby eliminating restrictions on the short wavelength side of the light receiving band due to the mixed crystal compound avalanche multiplication layer.

〔実施例〕〔Example〕

以下本発明を実施例により具体的に説明する。 The present invention will be specifically explained below using examples.

第1図は本発明の実施例を示す模式側断面図であり、例
えば下記の様に製造される。
FIG. 1 is a schematic side sectional view showing an embodiment of the present invention, which is manufactured, for example, as follows.

例えば不純物濃度I X1019cm−’程度のp++
1nP基板1の(100)面上にLPE法等により、下
記の半導体層を順次エピタキシャル成長する。なおIn
GaAsP層の組成はルミネセンスピーク波長λgで示
す。
For example, p++ with an impurity concentration of about I
The following semiconductor layers are sequentially epitaxially grown on the (100) plane of the 1nP substrate 1 by LPE method or the like. In addition, In
The composition of the GaAsP layer is indicated by the luminescence peak wavelength λg.

半導体層   組成     不純物  厚さCm −
3− 3(p+型領領域 InGaAsP(1,3t!Tn)
  p−1xlO”  22バッファ層  InP  
    p−2X10”  3この半導体層をp+型T
nPバッファ層2に達する深さにエツチングして、直径
例えば100μm程度のメサ領域を形成する。
Semiconductor layer Composition Impurity Thickness Cm -
3-3 (p+ type region InGaAsP (1,3t!Tn)
p-1xlO” 22 buffer layer InP
p-2X10" 3This semiconductor layer is p+ type T
Etching is performed to a depth that reaches the nP buffer layer 2 to form a mesa region having a diameter of, for example, about 100 μm.

次いで再び下記の半導体層をエピタキシャル成長する。Next, the following semiconductor layer is epitaxially grown again.

この半導体層のうちInGaAsP層4はメサ領域を埋
め込み、かつメサ領域上の厚さdを0.5四程度とする
。またInn、 5sGao、 47ASのルミネセン
スピーク波長λgは約1.55μmである。
Of this semiconductor layer, the InGaAsP layer 4 buries the mesa region and has a thickness d on the mesa region of about 0.54. Furthermore, the luminescence peak wavelength λg of Inn, 5sGao, and 47AS is about 1.55 μm.

半導体層   組成     不純物  厚さcm −
34 5光吸収層 (Lo、 5iGao1Js  n−I 
X 10’ ”  24増倍層  InGaAsP(1
,3−)  n−I X 10”  0.5このInG
aAs光吸収層5上に例えば金ゲルマニウム(AuGe
)を用いてn側電極8を、またInP基板1の裏面に例
えば金亜鉛(AuZn)を用いてp側電極7を配設する
Semiconductor layer Composition Impurity Thickness cm -
34 5 light absorption layer (Lo, 5iGao1Js n-I
X 10''' 24 multiplication layer InGaAsP(1
, 3-) n-I X 10” 0.5 this InG
For example, gold germanium (AuGe) is deposited on the aAs light absorption layer 5.
), and the p-side electrode 7 is provided on the back surface of the InP substrate 1 using, for example, gold zinc (AuZn).

本実施例は光をn型1nGaAs光吸収層5側から入射
し、n型1 n’G a A s P層4のp十型1n
GaAsP層3とこの光吸収層5に決まれた領域をアバ
ランシ増倍領域とするが、先に述べた如(InGaAs
PはInPに比べてモフォロジーが緩和され、付随する
不純物濃度分布の不均一性も減少するために、受光面内
の光感度分布の均一性が向上する。
In this embodiment, light is incident from the side of the n-type 1nGaAs light absorption layer 5, and the p-type 1n of the n-type 1n'GaAs P layer 4 is
A predetermined region of the GaAsP layer 3 and this light absorption layer 5 is defined as an avalanche multiplication region.
P has a relaxed morphology compared to InP, and the accompanying non-uniformity of the impurity concentration distribution is reduced, so the uniformity of the photosensitivity distribution within the light-receiving surface is improved.

受光面内の平均増倍率をM i V %最大増倍率をM
、□、最小増倍率をMい、つとし、増倍率の変動率を±
(M□ニーM、i、、)/2Mいで表して、前記従来例
では±30%に達するのに対し、本実施例ではこれが±
5%に止まり顕著な改善が達成されている。
The average multiplication factor within the light receiving surface is M i V % The maximum multiplication factor is M
, □, the minimum multiplication factor is M, and the variation rate of the multiplication factor is ±
Expressed as (M□knee M, i, , )/2M, it reaches ±30% in the conventional example, whereas in this embodiment, this reaches ±30%.
A remarkable improvement of only 5% has been achieved.

〔発明の効果〕〔Effect of the invention〕

以上説明した如(本発明によれば、受光帯域の制限を伴
うことなくモフォロジーに付随するアバランシ増倍領域
の不均一性が顕著に改善され、量子効率の向上、雑音の
低減等の特性向上を達成する効果が得られる。
As explained above (according to the present invention), the non-uniformity of the avalanche multiplication region associated with morphology is significantly improved without limiting the light receiving band, and characteristics such as improved quantum efficiency and reduced noise are achieved. The desired effect can be obtained.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の実施例の模式側断面図、第2図は従来
例の模式側断面図である。 図において、 1はp++1nP基板、 2はp+型InPバッファ層、 3はp++1nGaAsP N、 4はn型rnGaAsPアバランシ増倍層、5はn型f
nGaAs光吸収層、 7はp側電極、 8はn側電極を示す。 夫施例分梼式@!1何勤■ 牟 1 口 峯 22
FIG. 1 is a schematic side sectional view of an embodiment of the present invention, and FIG. 2 is a schematic side sectional view of a conventional example. In the figure, 1 is a p++1nP substrate, 2 is a p+ type InP buffer layer, 3 is a p++1nGaAsP N, 4 is an n-type rnGaAsP avalanche multiplication layer, and 5 is an n-type f
An nGaAs light absorption layer, 7 is a p-side electrode, and 8 is an n-side electrode. Husband example branch ceremony @! 1 What duty ■ Mu 1 Kuchimine 22

Claims (1)

【特許請求の範囲】 半導体基板上に、第1導電型の混晶化合物からなる第1
の半導体層が選択的に配設され、該第1の半導体層を埋
め込んで、第2導電型の混晶化合物からなる第2の半導
体層が設けられ、該第2の半導体層上に、該第1及び第
2の半導体層より禁制帯幅が小さい第2導電型の第3の
半導体層が設けられて、 該第3の半導体層を光吸収層、該第2の半導体層をアバ
ランシ増倍層とすることを特徴とする半導体受光装置。
[Claims] On a semiconductor substrate, a first conductivity type compound made of a mixed crystal compound of a first conductivity type is formed.
a second semiconductor layer made of a mixed crystal compound of a second conductivity type is provided to bury the first semiconductor layer; A third semiconductor layer of a second conductivity type having a smaller band gap than the first and second semiconductor layers is provided, the third semiconductor layer is a light absorption layer, and the second semiconductor layer is an avalanche multiplication layer. A semiconductor light-receiving device characterized by having a layered structure.
JP61111259A 1986-05-15 1986-05-15 Semiconductor photodetector Pending JPS62266880A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61111259A JPS62266880A (en) 1986-05-15 1986-05-15 Semiconductor photodetector

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61111259A JPS62266880A (en) 1986-05-15 1986-05-15 Semiconductor photodetector

Publications (1)

Publication Number Publication Date
JPS62266880A true JPS62266880A (en) 1987-11-19

Family

ID=14556659

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61111259A Pending JPS62266880A (en) 1986-05-15 1986-05-15 Semiconductor photodetector

Country Status (1)

Country Link
JP (1) JPS62266880A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5654578A (en) * 1994-12-22 1997-08-05 Nec Corporation Superlattice avalanche photodiode with mesa structure

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5654578A (en) * 1994-12-22 1997-08-05 Nec Corporation Superlattice avalanche photodiode with mesa structure

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