JPS62266626A - Microprogram type microcomputer - Google Patents

Abstract

PURPOSE:To recognize the flow of a microprogram by sequentially storing the parities of contents in a microprogram memory and outputting a series of parities to a port in the final microstep of an instruction. CONSTITUTION:The parities of contents in a micro-ROM, which are read whenever a microstep is executed, are sequentially stored in a shift register 7. A control signal 14 outputted in the final microstep of the instruction makes a buffer circuit 8 active, and said parities are outputted to the port 10 through a bus 9. Since the execution sequence of microsteps comprising the flow of the microprogram in the executed instruction and the parities stored in the micro ROM corresponding to the bit array of the port 10 are outputted to the port 10 after the execution of the instruction, the flow of a microcomputer can be recognized, and simultaneously such judgement can be made that an error is pinpointed in which step of the flow.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram type microcomputer.

[Conventional technology]

Conventional microprogram type microcomputers check the contents of the microprogram memory by sequentially reading the microprogram memory from address 0 during testing, generating a parity of the read contents, and outputting it to an output terminal.

FIG. 2 is a block diagram of a conventional example of the above-mentioned microcomputer. This microcomputer includes an instruction register 1, a micro ROM section 3 consisting of a decoder and a micro ROM, and an address register 2 that holds the micro ROM address of the instruction register 1 using a clock Φ.
and the address input terminal 15 of the micro ROM, the test terminal 17, the multiplexer 16 which outputs the contents of the address input terminal 15 to the micro ROM section 3 when "1" is input to the test terminal 17, and the readout from the micro ROM section 3. 4. A latch circuit that latches the programmed microprogram using the large I pulse φ. It consists of a parity generation circuit 5, a flag 6 for storing the generated parity, and an output terminal 18. During testing, when the test terminal 17 is set to rlJ and the address to be tested is input to the address input terminal 15, the multiplexer 1B The address is input to the decoder of the micro ROM section 3, and the micro RO of the address is input.
M+7) contents are read out to the latch circuit 4, the parity generation circuit 5 generates a parity based on the output of the latch circuit 4, and the generated parity is stored in the flag 6 and output to the output terminal 18. Generally, addresses are input to the address input terminal 15 in order starting from address 0, and the parity of the contents of the micro ROM is sequentially output to the output terminal 18. Therefore, by monitoring the value of the output terminal 18, the micro ROM
M was being checked.

[Problem that the invention seeks to solve]

The above-mentioned conventional microprogram type microcomputer reads the contents of the microprogram memory (micro ROM part) sequentially from address O during testing, generates parity, and outputs it to the output terminal, thereby reading the contents of the microprogram memory. I checked, but parity of the microprogram memory is not generated during microstep execution according to the instruction-specific flow of a series of microprograms when executing instructions, so the microprogram that controls the instruction execution of the microcomputer does not generate parity in the microprogram memory. If the flow of the microprogram cannot be confirmed and the instruction execution operation is not performed correctly, it is difficult to determine whether there is an error in the flow of the microprogram or in the hardware that is the target of instruction execution. There is a drawback.

[Means for solving problems]

During testing, the microprogram type microcomputer of the present invention sequentially reads the contents of the microcomputer memory, generates parity for the read contents, and outputs it to the output terminal to check the contents of the microprogram memory. In a microprogram type microcomputer, the parity of the contents of the microprogram memory that is generated each time each step of the microprogram constituting the flow of a series of instruction-specific microprograms is executed is sequentially stored. The method is characterized in that it includes means for outputting parity to a port at the final microstep of an instruction.

Therefore, after the execution of an instruction, the parity of the microprogram memory is output to the port according to the bit arrangement of the port and the execution order of the microsteps that make up the flow of the microprogram of the executed instruction. You can check the flow of the microprogram that controls instruction execution.

〔Example〕

Next, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of a microprogram type microcomputer of the present invention. The same numbers as in Figure 2 refer to the same things.

The shift register 7 contains the signals generated by the parity generation circuit 5,
The parity stored in flag 6 is the shift clock φ
are stored sequentially. The control signal generation circuit 12 outputs a control signal 13 based on the output of the latch circuit 4, and also outputs a control signal 14 to the buffer circuit 8 when the final step of the microprogram is latched by the latch circuit 4. By this control signal 14, the contents of the shift register 7 are changed to the buffer circuit 8. It is designed to be outputted to port 10 via bus 9. Note that the output 11 of several bits from the latch circuit 4 is input to the address register 2, and the address of the micro ROM to be selected is determined in the first step.

Next, the operation of this embodiment will be explained. The contents of instruction register 1 are transferred to address register 2 of micro ROM,
Execution of a series of instruction-specific microsteps begins. The output of the address register 2 is input to the decoder of the micro ROM section 3, and the contents of the micro ROM at the address are read out to the latch circuit 4. The micro ROM stores control signal information to be output at each micro step, and the control signal generation circuit 12 outputs the plow control signal 13 based on the output of the latch circuit 4. A parity generation circuit 5 generates a desired parity based on the output of the latch circuit 4,
The generated parity is stored in the flag 6 and input to the shift register 7. On the other hand, the output 11 of several bits of the latch circuit 4 is input to the micro ROM address register 2, and the micro ROM to be selected in the next micro step is inputted to the micro ROM address register 2.
A series of instruction-specific microprograms is executed by repeating 0 or more operations in which the next microstep is executed, but the contents of the microROM read each time a microstep is executed. The parity of 1 is sequentially stored in the shift register 7, and the control signal 1 is output at the final microstep of the instruction.
4 activates the buffer circuit 8 and outputs the signal to the port 10 via the bus 9. Therefore, after the instruction execution is completed, the parity of the micro ROM is outputted to the port 10 in accordance with the bit arrangement of the port 10 and the execution order of the microsteps constituting the flow of the microprogram of the executed instructions.

〔Effect of the invention〕

As explained above, the present invention sequentially stores the parity of the contents of a microprogram memory that occurs each time each step of a microprogram constituting a series of instruction-specific microprogram flows is executed, and By providing a means for outputting the parity of the microstep to the port in parallel at the last microstep of the instruction, the port after the instruction execution is completed will be able to display the execution order of the microsteps constituting the flow of the microprogram of the executed instructions and the port's parity. Since the parity of the microprogram memory is output in accordance with the bit arrangement, it is possible to check the flow of the microprogram that controls the instruction execution of the microcomputer, and if the instruction is not executed correctly,
By comparing the port output after instruction execution with the series of parities of the flow that should have been executed and finding different bits, it is possible to determine in which step of the series of flows there is an error. If this is not the case, it can be determined that there is an error in the hardware that is the target of correct instruction execution in the flow of the microprogram, which has the effect of making it easier to evaluate the instruction function of the microcomputer and analyze defects.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of a microprogram type microcomputer according to the present invention, and FIG. 2 is a block diagram of a conventional example. l...Instruction register, 2...Address register, 3...Micro ROM section, 4...Latch circuit, 5...
...Parity generation circuit, 6...Flag, 7...Shift register, 8...Buffer circuit, 9...Bus,
10...Port, 11...Output for several bits of latch circuit 4, 12...Control signal generation circuit, 13, 14...Output of control signal generation circuit 12.

Claims (1)

[Claims] At the time of testing, a microprogram type microcomputer that sequentially reads the contents of the microprogram memory, generates parity for the read contents, and outputs it to an output terminal to check the contents of the microprogram memory. In this step, the parity of the contents of the microprogram memory that occurs each time each step of the microprogram constituting the flow of a series of instruction-specific microprograms is executed is sequentially stored, and the stored parity is stored in the final microstep of the instruction. A microprogram type microcomputer characterized by including means for outputting data to a port in parallel.