JPS6226517A - Servo-device - Google Patents

Abstract

PURPOSE:To raise the resolution by using a compared signal which is obtained by comparing an output signal of a tachometer generator and a set voltage signal as speed information, and correcting a set error of a set voltage by an operator. CONSTITUTION:A servo-device of a motor 1 is constituted of a channel selector 5, a programmable voltage source 6, a RAM 7, a logical arithmatic unit (ALU) 19, etc., and a state of the motor 1 is inputted to the first and the second comparators 11, 12 through a voltage control amplifier 3 from a tachometer generator 2. To this comprators 11, 12, an output signal from a programmable voltage source 6, which is selected by the channel selector 5 is inputted, and speed information is obtained by comparing both the signals. Also, a reference clock signal is counted by a counter 15, and its counting value is stored in the RAM 7 by said comparing signal. From this counting value, an error output is calculated by the ALU 19, the motor 1 is driven, based on the result, and also by a timing controller 26, the RAM 7 and the ALU 19, the error output is corrected.

Description

[Detailed description of the invention]

INDUSTRIAL APPLICATION FIELD The present invention relates to a servo device that controls the rotational speed of a rotating body or the moving speed of a linear moving body to a desired value. BACKGROUND ART Traditionally, as a method of controlling the moving speed of a rotating body or a linearly moving body such as a motor or a linear motor (in the case of a rotating body, the rotational speed is the moving speed) to a desired value, The mainstream has been to use a speed generator that is connected to a moving object and generates an output signal having a frequency and voltage depending on the moving speed of the moving object. This corresponds to what is called a tacho generator servo, and from the viewpoint of the usage of the output signal, it can be divided into two types: a voltage detection force type and a frequency or period detection force type. The voltage detection force type uses the fact that the amplitude of the output AC signal of many speed generators, for example, a speed generator with a generator coil, changes depending on the moving speed, and this output AC signal is determined in advance. The switching transistor is operated to discharge the charge on the capacitor when the voltage is reached, while the capacitor is charged by a constant resistance when the switching transistor is in the off state. (for example, as shown in Japanese Patent Publication No. 58-6392), or a method of rectifying the output alternating current signal of a speed generator to obtain an error voltage. A method that uses the generated voltage of the speed generator as is (for example,
The method described in US Pat. No. 2,906,876 is applicable, in which a DC motor controlled by means of a chopper is used as a speed generator during the non-energizing period of the DC motor. )and so on. However, in both cases, the generated voltage of the speed generator is used as speed information, so stability against changes in ambient temperature, changes over time, and changes over time is low, and only simple examples of servo devices can be used. Ta. On the other hand, the frequency or period detection force type uses only the frequency or repetition period of the output signal of the speed generator as speed information. ,
Alternatively, as shown in US Pat. No. 3,836,756. ) had the advantage of providing extremely high stability. By the way, this frequency or period detection power formula generates an error output signal by assuming that a predetermined edge of the output signal of the speed generator, which has been sufficiently amplified to become a rectangular wave signal, has speed information. For example, in a typical periodic detection force method, clock pulses are counted in the period from the leading edge of the output signal of the speed generator after amplification to the next leading edge. You can obtain a count value that depends on The error output is obtained by converting to Therefore, in order to achieve control with higher resolution, it is necessary to increase the number of edges. For example, when controlling the speed of a motor based on the output signal of an alternator that generates one cycle of alternating current signals for one rotation of the motor, the conventional method It is impossible to obtain speed information more than a few times and perform control based on it, and the leading edge and trailing edge of the square wave signal obtained by amplifying the output signal of the speed generator. By using both, the interval at which speed information can be obtained is reduced to 2.
It was only 1/10th of that. In addition, there is a method of multiplying the frequency of the output signal of a speed generator using a PLL (phase locked loop) (as shown in U.S. Pat. No. 4,114,075), and a method of multiplying the frequency of the speed generator's output signal by using Attempts have been made to generate two different types of alternating current signals to obtain a speed detection signal having substantially four times the frequency (for example, as shown in Japanese Patent Publication No. 6B-6166), but the former Since the speed information possessed by the multiplied signal obtained by this method depends only on the speed information possessed by the original signal, it has no effect on the purpose of increasing control resolution; Although the structure of the generator is complicated, the resolution is only twice as high as the method using both the leading edge and trailing edge of the output signal of the speed generator, which was explained earlier, so it is not very rational. It wasn't. For this reason, conventional efforts have been made to increase the output frequency of the speed generator itself. Problems to be Solved by the Invention However, with the above configuration, even if the output frequency of the speed generator is increased, the frequency will be doubled or quadrupled. A great effect cannot be expected unless the ratio of By adopting a configuration that irradiates light and detects the reflected light, the frequency of the speed generator becomes dramatically higher, but at the same time, its structure becomes extremely complex.), the structure of the speed generator It became necessary to process parts with high precision, which caused many problems. In view of the above problems, the present invention aims to realize a servo device that can perform control with higher resolution without increasing the output frequency of the speed generator. Means for Solving the Problems In order to solve the above problems, the servo device of the present invention includes a voltage source that generates at least two preset output voltages, and a combination of the output voltage of the voltage source and the rotor of a motor. By comparing the potential of an AC signal having speed information of a moving object such as a moving element of a spear near motor,
a comparator that generates an output signal of at least 10 times, a counter that counts the reference clock signal, a memory means that stores the count value of the counter at the time when the output signal of the comparator is generated, and an error output from the count value. a computing unit that calculates the error output, a driving unit that supplies driving power to the moving object based on the error output, and a deviation from a normal value of the generation time of the output signal of the comparator over at least half a cycle of the AC signal. The present invention is characterized by comprising error output correction means for calculating the calculation result and causing the arithmetic unit to correct the error output at each measurement time point. Operation The present invention uses the comparison signal obtained by comparing the output signal of the speed generator and the output signal of the voltage source that generates a preset voltage as speed information with the above-described configuration, and outputs the set voltage. Since the setting error of the voltage source is corrected by the arithmetic unit, it is possible to control with higher resolution without increasing the output frequency of the speed generator, in other words, it is possible to effectively increase the output frequency of the speed generator. It is possible to perform the same control as Embodiment Hereinafter, a servo device according to an embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention. The output of a speed generator (generally called a frequency generator or simply FG) 2 connected to a motor 1 is connected to a voltage controlled amplifier ( is amplified to a constant amplitude by a waveform shaper (indicated by the abbreviation WS in the figure) 4 until it becomes a square wave. amplified,
The output of the waveform shaper 4 is supplied to the channel selector as a reset signal. The channel selector 6 mainly generates a channel selection signal of the programmable voltage source 6 and a random access memory (hereinafter abbreviated as RAM) 717) 7 dress selection signal, and these selection signals are sent via the control bus 8. and is supplied to the programmable voltage source 6 and the RAM 7. Further, the output of the voltage controlled amplifier 3 is supplied to an amplitude controller 9, and the gain of the voltage controlled amplifier 3 is adjusted by the amplitude controller 9 so that the amplitude is constant, and the gain of the voltage controlled amplifier 3 is adjusted by the amplitude controller 9 so that the amplitude is constant. The output is supplied to an offset controller 1°, and the offset of the manual stage of the voltage controlled amplifier 3 is adjusted so that the duty of the rectangular wave output signal becomes 5o-so. The output signal of the voltage control amplifier 3, whose amplitude and offset have been adjusted in this way, is sent to a non-inverting input terminal 11& of a first comparator (indicated by the abbreviation CMPl in the figure) 11. It is supplied to an inverting input terminal 12b of a second comparator (indicated by the abbreviation OMP2 in the figure) 12. Further, an output signal from the upper output terminal 6& of the programmable voltage source 6 is supplied to the inverting input terminal 11b of the comparator 11, and an output signal from the upper output terminal 6& of the programmable voltage source 6 is supplied to the non-inverting input terminal 12& of the comparator 12. Output signals from the lower output terminals b are supplied, voltage comparison is performed with the output signal of the voltage control amplifier 3 in each comparator, and the comparison output signal is sent to the channel selector 5.
is supplied as a channel update signal. On the other hand, the output of the oscillator 14 having the crystal oscillator 13 is supplied as a clock signal to the counter 16, and the output from the most significant bit (hereinafter abbreviated as MSB) to the least significant bit (hereinafter abbreviated as LSB) of the counter 16 is The output of is supplied to the temporary register 17 via the data bus 16,
The output of the temporary register 17 is supplied via a data bus 18 to a bidirectional data bus 20 connecting a logical operation unit (hereinafter abbreviated as LU) 19 and the RAM 7, and the output of the ALU 19 is is data bus 2
1 to the latch 2.2. The output of the latch 22 is supplied via a data bus 23 to a digital-to-analog converter 24, whose output is connected to a power amplifier (indicated by two abbreviations in the figure). ) 26 and is supplied to the motor 1 as driving power. Furthermore, from the channel selector 5, the
A trigger signal and a control signal are supplied to the timing controller 26 via the a-register bus 8, an output signal is also supplied from the waveform shaper 4 to the timing controller 26, and the control signal from the timing controller 26 is sent to the temporary register. 17 via the control bus 27. is supplied to the bus selector 28 via the control bus 29. and is supplied to the RAM 7. Further, the timing controller 26 and the mu LU1
A bidirectional control bus 3o is connected between the two. Note that the output signal of the channel selector 6 is first supplied to the path selector 28 via the control bus 8. The output signal of the bus selector 28 is supplied to the RAM 7 via the control bus 31, and the bus selector 28 acts as a repeater having an input switching function, and when control data is sent from the motion timing controller 26, it is sent to the RAM 7 via the control bus 31. The input on the /l/ bus 8 side is cut off and the input on the control bus 27 side is sent to the control bus 31. However, during other normal operations, the signals on the control bus 8 are always sent to the control bus 27 as they are. 31. The timing controller 26 transfers the count value of the counter 16 to the temporary register 17 when a trigger signal is input, and also transfers the count value of the counter 16 to the temporary register 17.
7 and the previous count value stored in R.
After causing the ALU 19 to perform calculations with the desired value for speed control stored in AM7 and transferring the calculation results to the latch 22, the temporary register 17
It operates as a sequencer that transfers the count value stored in the voltage control amplifier 3 to the RAM 7, but when the motor 1 is started, the output signal of the voltage control amplifier 3 is pre-clouded for at least half a period, as will be described later. The ALU 19 calculates the deviation of the Ekisho time of 110,000 yen from the normal value, and the result is sent to the R
It also has a function to store it in the initial error storage area of AM7. Now, FIG. 2 is a circuit wiring diagram showing a specific example of the configuration of the voltage control amplifier 3, and the input terminals 31L and 3b are connected to the output signal of the speed generator 2 and the output signal of the offset controller 1o in FIG. 1, respectively. The input terminal 3d is an input terminal to which the output signal of the amplitude controller 9 shown in FIG. 1 is supplied, and the terminal vCC is a positive power supply terminal. In the voltage controlled amplifier shown in FIG. 2, the first differential amplifier 301. Second differential amplifier 302. Third differential amplifier 3
03 forms the center thereof, and a fourth differential amplifier 304 supplies a bias current dependent on the error voltage from the amplitude controller 9 supplied to the input terminal 3d to the differential amplifier 301.
~303. Further, the output section 305 of the voltage control amplifier 3 is constituted by an emitter follower type buffer 1 amplifier. Next, FIG. 3 is a circuit connection diagram showing a specific example of the configuration of the channel selector 6 shown in FIG.
, sb are input terminals to which the output signals of the comparators 11 and 12 of FIG. ) is the input terminal to which the output signal of the pit can be reused, and the input terminal 6d
is an input terminal to which the output signal of the waveform shaper 4 shown in FIG. 1 is supplied. The channel selector shown in FIG. 3 includes a 2-bit up/down counter 6Q1 and a reset signal generation circuit 602.
and an input signal switching circuit, and the outputs of the first and second bits of the up/down 4 counter 501 are supplied to output terminals 6f and F5g, respectively. Further, the clock signal supplied to the up/down counter 601 is configured to be supplied to the timing controller 26 in FIG. 1 via the output terminal 51, and the output terminal 6e is directly connected to the input terminal 6d. There is. Note that the output signals (output data) appearing at the output terminals 50 to 6g are supplied to the programmable voltage source 6 via the control bus 8 in FIG. Five output terminals are provided, and the output signals appearing at the output terminals 50 to 5g and 5j are supplied to the RAM 7 via the control bus 8 to generate selection signals for eight addresses. FIG. 4 is a signal waveform diagram for explaining the operation of the channel selector shown in FIG.
This shows the output signal waveform of the voltage control amplifier 3 in the figure.
The intermediate potential is one half of the power supply voltage. FIG. 4(b) shows the output signal waveform of the waveform shaper 4 in FIG.
That is, FIG. 3 shows the signal waveform supplied to the input terminal 6d, and FIG. 4(C) shows the signal waveform of the clock signal supplied to the input terminal 5c. 4(d) and (6) respectively show the changes in the output level of the D flip-flops 503 and 504 in FIG. 3, and the EX-OR (exclusive OR) gate 6 in FIG.
The signal waveform shown in Figure 4 (0) appears at the output terminal of 05. In the following explanation of the operation of the logic circuit, all positive logic is used, and when each output terminal or each signal line is at a high potential, the signal waveform shown in Figure 4 (0) appears. In addition, the state of high potential is expressed as "1", and the state of low potential is expressed as "0°." However, when the level of the input terminal 5a shifts to "1" at time t1, the AND-OR
(AND is logical product, OR is logical sum) Since the output signal level of gate 606 also shifts to "1", the input and output terminals of NAND (negative logical product) gate 607 and WAND gate 608 are cross-coupled with each other. The connected and configured flip-flop 0609 is set by the NAND gate 510 and the D flip-flop 511
The level of the D terminal shifts to "1" as shown in FIG. 4(h). The level of the D terminal of the D flip-flop 511 is “1”.
When the leading edge of the clock signal arrives after transitioning to "1", the output level of the D flip-flop 511 shifts to "1" as shown in FIG. 4(1), and as a result, the flip-flop 609 is reset again. Therefore, when the next leading edge of the clock signal arrives, the output level of the D flip-flop 611 also returns to "0", and the output terminal of the AND gate 612 receives a signal as shown in FIG. A waveform appears. The output signal of the AND gate 612 becomes the clock signal of the up/down counter 601, and when the output level of the D flip-flop 611 is at ml", the up/down counter 601 is in a standby state for up-counting operation. , immediately after the output level of the human ND gate 612 shifts to "1", the count value of the up/down counter 501 becomes

Count up from [00] to [01]. 4(k) and (1) show the output levels of the first and second bits of the up/down counter 501, respectively. By the way, in the signal waveform diagram shown in FIG. 4(g), the level shifts to "0°" immediately after the count value of the up/down counter 6010 becomes "01", but this is due to the fact that this is explained later. This is because the output voltage of the programmable voltage source 6 in FIG. 1 increases and the output level of the comparator 11 returns to "0" as the data at the output terminals 60 to 5g changes. When the level of the input terminal 6 section shifts to "1" at time t1, the up/down counter 601 counts up, but immediately after the level of the input terminal 6d shifts to "O" at time t2, the EX
-OR gate 1506 generates a reset signal, so
The up/down counter 501 is

It is reset to [00]. In the above explanation, it is assumed that the level of the input terminal 6& has changed, but the same can be said when the level of the input terminal 6b has changed. However, a flip-flop 616 configured by an NOR (NOR) gate 613 and a NOR gate 614
Accordingly, the input reception on the up-count side is H for attaching.
Since the AND gate 610 and the input receiver on the down-count side supply an enable signal for the NARD gate 516, the count value of the up-down counter 5010 will not change after the EX-OR gate 506 generates a reset signal. Only up-count input is accepted until it reaches [10], and when the count value of the up-down counter 601 reaches [1o], the output state of the flip-flop 516 is reversed, and from then on, only down-count input is accepted. I started to have reception. Furthermore, in the circuit of FIG. 3, the AND-OR gate 606 and the A
An amplifier counting operation is performed by the signal supplied to the input terminal S& by the ND-OR gate 518, a down-counting operation is performed by the signal supplied to the input terminal 6b, and conversely, the amplifier count operation is performed by the signal supplied to the input terminal 6b. At the 17th level of d, the down-count operation is performed by the signal supplied to the input terminal 5a, and the up-count operation is performed by the signal supplied to the input terminal 5b. Next, FIG. 5 is a circuit connection diagram showing a specific example of the programmable voltage source 6 shown in FIG.
b are output terminals for supplying output signals to the comparators 11 and 12 in FIG. 1, respectively, and terminal vCC is a power supply terminal on the glass side. Input terminals 66.6f and 6g are output terminals 6f3 and 5f of the channel selector shown in FIG. 3, respectively. This is an input terminal to which a channel selection signal is supplied from 6g. Now, in Figure 5, there are three inverters and seven AND
All gates are used as channel decoders, and for example, the levels of input terminals 6f and 6g are both “
0", the transistor 601 and the transistor 602 are turned on regardless of the level of the input terminal 6e. At this time, the potential of the output terminal 6a rises slightly above the intermediate potential, and the potential of the output terminal 6b rises above the intermediate potential. Also, when the levels of the input terminals 6e and 6f are both "1" and the level of the input terminal 6g is "ao", the transistors 603 and 604 are turned on, and the output Terminal 6! The potential of L further increases, and the potential of the output terminal 6b becomes a value slightly higher than the intermediate potential. In the circuit of FIG. 6, assuming that the on-resistance of each switching transistor is sufficiently small, the resistance 60
The step potential appearing at the output terminal 6a is determined by the resistors 5, 606, 607, 608, and the resistors 609.
Output terminal 6b by resistance value of 610, 611°612
The step potential appearing at is determined. Further, as shown in FIG. 6, by setting the resistance values of each side constituting the resistance network to be the same on the output terminal 6a side and the output terminal 6b side, for example, the output terminal 6a When the output potential of the output terminal 6b increases step by step, the output of the output terminal 6b changes accordingly. Next, FIG. 6 is a memory map showing an example of the arrangement of memory cells in the RAM 7 shown in FIG. 1, and address selection signals for 4 pits output from the path selector 28 in FIG. +f (these correspond to the signals appearing at output terminals 6j. 1)'t6g, sf, respectively, in FIG. ), addresses 701 to 708 in the C area, addresses 711 to 718 in the E area, or addresses 721 to 728 in the F area are accessed. Note that the selection of area C, area E, or area F is performed by the timing controller 26 via the control bus 29, as will be described later, and a desired position (also referred to as a reference value) for controlling the speed of the motor 1 is stored. address 710 of the B area where the cumulative error is stored, address 720 of the C area where the cumulative error is stored, address 730 of the C area used for calculations during error correction, address 731 of the H area, address 732 of the ■ area, Address 733 of the J area is directly accessed by the timing controller 26. Now, since the timing controller 26 after the motor 1 reaches a steady state operates as a sequencer as described above, it can be easily realized in terms of hardware by connecting D flip-flops in multiple stages. However, since it can be easily processed by software such as a microcomputer program, a description of a specific example of its configuration will be omitted, and the flowchart in FIG. 7 showing the operation flow of the timing controller 26 during normal operation will be omitted. An outline of the operation of the system will be explained based on the signal waveform diagram of FIG. 8 showing the signal waveforms of the main parts of the system of FIG. 1, and the memory map of FIG. 6. First, FIG. 8(&) is an output signal waveform diagram of the voltage control amplifier 3 in FIG. 1, and FIG. 8(b) is an output signal waveform diagram of the waveform shaper 4, which is shown in FIG. This is also the signal waveform supplied to the input terminal 5d of the channel selector. Figure 8 (C), (d), and (el) are the third
These are the signal waveforms appearing at the output terminals sj, 6f, and sg of the channel selector shown in the figure, and are shown in Fig. 8 (f'l, (h)
are the signal waveforms appearing at the output terminals ea and eb of the programmer mating voltage source 6 in FIG. 1, respectively, and
g>, (i) are the output signal waveforms of the comparators 11 and 12, respectively, and FIG. 8G) is the signal waveform appearing at the output terminal 61 of the channel selector in FIG. Note that the intermediate potential of the signal waveforms in Figure 8 (&), (f), and (h) is half the power supply voltage, and is further indicated by the broken line in Figure 8 (f'). The lower envelope and the upper envelope indicated by broken lines in the 8th roundworm) both represent the signal waveform shown in FIG. 8 (&). Now, the generation process of the signal waveforms shown in FIGS. 8e) to 8(j) in each block has already been explained, but here we will once again explain the outline of the operation of the entire system. At time tx in FIG.
15 is supplied with a reset signal, the count value of the up/down counter 501 at this point is [00
], and the level of the output terminal 5j becomes '1°. At this time, the output terminal 6 of the programmable voltage source 6 in FIG.
The potential of a is a little higher than the intermediate potential, and the potential of the output terminal 6b is a little lower, but at time t1, when the potential of the output signal of the voltage control amplifier 3 becomes higher than the potential of the output terminal 6a, the comparison The output level of the device 11 is “1”
°, the up/down counter 6Q1 counts up and the count value becomes [o1], and as a result,
Since the potentials of the output terminals 6& and 6b rise stepwise, the output level of the comparator 11 returns to "O". At time t2, when the potential of the output signal of the voltage control amplifier 3 becomes higher than the potential of the output terminal 6a again, the output level of the comparator 11 shifts to "1" again, and as a result, the up/down counter 501 The count value becomes [10], and the potentials of the output terminals ea and eb also rise, but as already explained, the flip-flop 615 in FIG. 3 prohibits reception of inputs on the up-count side. , this time it enters a standby state for input on the down count side. In this state, the peak point of the output signal of the voltage control amplifier 3 has passed, and the potential reaches the output terminal 6 at time t5.
When the potential becomes lower than the potential of the comparator 12, the output level of the comparator 12 shifts to "1", and the up/down counter 60
1 counts down and the count value becomes [01], thereby the potentials of the output terminals 6& and eb fall in a stepwise manner. A similar operation is performed at time t4, and the up/down counter 501 counts down, thereby causing the potentials of the output terminals 6a and eb to decrease.
When the level /L' of d shifts to "On," the output signal of the comparator 12, which had been the down-count input of the up-down counter 501, is changed to the up-count input, and the voltage remains unchanged until time t6. Every time the potential of the output signal of the control amplifier 3 becomes lower than the potential of the output terminal 6b by υ, the up/down counter 501 counts up and the potential of the output terminals ea and eb further decreases stepwise. At time t7, when the potential of the output signal of the voltage control amplifier 3 becomes higher than the potential of the output terminal 62L, the up/down counter 601 counts down, so the potential of the output terminals 6a and eb increases stepwise. In this way, the comparators 11 and 12 generate output signals one after another, so that a pulse train as shown in FIG. 8 appears at the output terminal 61 of the channel selector 5. The pulse interval of the pulse train (1) can be kept constant by selecting the optimum resistance values of the resistors 606 to 612, which determine the output voltage of the programmable voltage source shown in FIG. For example, assuming that the output signal of the speed generator 2 in FIG.
Since the structure is such that the cycle is divided into eight equal parts, the programmable voltage source 6 only needs to generate two accurate output voltages, and these voltages are designated as V, , V2.
Then, the mutual relationship is given by the following equation. vn= vp Hsin (n ・π/a−θ)+v
C/2 (1) However, n = 1.2 In formula (1), Vc is the power supply voltage, and Vp is half of the amplitude controlled by the amplitude controller 9.
The value of θ is set to π/8 in the embodiment. Therefore, when considering the system scale, if there is no problem in increasing the step precision of the output voltage of the programmable voltage source 6 to be as high as that of a 12-bit digital-to-analog converter, the system shown in FIG. 8(j) can be used. It is also possible to directly obtain an error output by comparing the pulse train interval with a reference value. Incidentally, the relative error in the output voltage of the programmable voltage source 6 is the same as that of the 12-pit daisycrew analog converter.
Assuming that Q, which corresponds to 1 LSB, is 13%, the deviation in the normalized pulse interval of the signal waveform in Fig. 8 (j) is largest in the section from time t2 to time t3 in Fig. 8. , and its value is n=2 in equation (1).
It is obtained by substituting ΔVn for 1.3X10, dividing the small angular difference by π/4, and then multiplying by 2, which is about 0.08%, which is sufficient for normal use. Accuracy can be ensured. However, in the embodiment of the present invention shown in FIG. 1, even if the relative error in the output voltage of the programmable voltage source 6 is larger (for example, about 1%), sufficient detection accuracy can be ensured, and It is configured to quickly reflect changing information in the output, and how it works is explained below. The output signal of the channel selector 5 shown in FIG. 8(j) is supplied as a trigger signal to the timing controller 26, but when the trigger signal becomes active, the timing controller 26 operates as shown in FIG. Do the following. That is, at time t1 in FIG. 8, the level of the trigger signal shifts to "1 degree," and at this time, the branch 201 in FIG. 7 (the trigger signal is indicated by the symbol TG in FIG. 7). The determination result in step 2 is yes, and the processing block 202 transfers the current count value TO of the counter 16 to the temporary register 17 (indicated by the symbol TEMP in FIG. 7), and then the processing block 203 transfers the current count value TO of the counter 16 to the RAM 7. The value stored in the tempo tree register 17 is subtracted from the value CD stored in the C area of At this time, the address selection of the RAM 7 is performed by the channel selector 6, and the 6th address is selected as the C area.
Address 701 in the figure is selected. Next, in processing block 204, the reference value CB of the RAM 70B area is subtracted from the value of the accumulator, and from the result, in processing block 206,
The value (() in the C area of the RAM 7 is subtracted, and the result is left in the accumulator.Next, in processing block 206, the value left in the accumulator is transferred to the latch 22 (indicated by OL in the flowchart of FIG. 7). ), and in processing block 207, the same value is transferred to address 711 (indicated by C1 in the flowchart of FIG. 7) of the E area of the RAM. , the value [C] of the C area of the RAM 7 and the value of address 711 of the E area of the RAM 7 (the value remaining in the accumulator) are added, and in the processing block 209, the addition result in the processing block 208 is added to the E of the RAM 7. The value at address 712 (indicated as CN up in the flowchart of FIG.
It is stored in the C area. Furthermore, in processing block 211, the value stored in the temporary register 17 is transferred to address 7Q1 of the C area of the RAM 7, and the series of processing is completed. At time t2 in FIG.
When the level of the trigger signal supplied to the controller 6 shifts to 1°, the address of the RAM 7 is incremented and exactly the same processing is performed, and thereafter the level of the trigger signal shifts to 1°. The processing shown in FIG. 7 is repeated every time. In the processing block 211 of FIG. 7, the count value of the counter 16 at that time is stored in the C area of the RAM 7. 2
The process in step 03 subtracts the current count value from the previous count value to obtain time difference data. For example, considering time t12 in FIG. 8 as the current time, the count value of the counter 15 at time t2 is stored in address 702 of the C area of the RAM 7, and this value is set as D2. When the count value is Dl, the calculation in the processing block 203 is (
D2-Dl2). However, the counter 15 is assumed to be a down counter. Furthermore, if Dl2>D2, processing block 2
The calculation in 03 is (D2+D123).Furthermore, in processing block 204, B of the RAM7 is
The reference value (desired value for speed control) stored in the area (desired value for speed control, although not shown in Figure 1, several types of data are prepared in a separate read-only memory etc. (transferred to RAM), the average error data from time t2 to time t+z is obtained. On the other hand, the C area of the RAM 7 is stored from time t2 to time 1.
The cumulative value of speed error detection values up to ++ is stored (
When an extremely large speed error is detected, such as when the motor 1 is started, zero is stored as the cumulative value. ), in the processing block 205, C of the RAM 7 is calculated from the average error data from time t2 to time t+zt.
By subtracting the cumulative value stored in the area, error data Ei2 based on speed fluctuations occurring in the section from time 1++ to time t12 is obtained. This error data Ej2 is transferred to the latch 22 in the processing block 206 and is transferred to the digital-to-analog converter 24.
The signal is converted into an analog voltage or current at , and then supplied to power amplifier 26 . As a result, the power amplifier 26 supplies the motor 1 with driving power depending on the output of the digital-to-analog converter 24 until the next reference point (in the present example, the processing time at time t15). On the other hand, the error data TL is transmitted to the processing block 207.
12 is stored at address 712 in area C of the RAM 7, and then, in processing block 208, the error data Ej is stored in the C area of the RAM 7.
2 is added. Further, in processing block 209, processing block 208
After subtracting the error data stored at address 713 of the E area (error data for the section from time t2 to time t5 is stored) from the addition result, processing block 210 adds the calculation result to the above calculation result. It is stored in area C. Therefore, at this point, the cumulative value of error data in the section from time t3 to time t12 is stored in the C area, and the time t12 at the comparison point of time t13 is stored in the C area.
It is prepared for detecting speed errors in the section from t15 to time t15. Further, in the processing block 211, the count value DI2 stored in the temporary register 17 is transferred to the RAM 7.
This is in preparation for processing at the matching point at time t22. In this way, if some speed fluctuation occurs between time t1j and time ti2 in FIG. , and is reflected in the error output at all matching points at time tz+1. For example, the speed generator 2 at the specified mouth transmission speed of the motor 1
Assuming that the output frequency of counter 15 is 48H2,
Assuming that the number of 0 bits is 16 and the clock frequency is 1MHz, the desired value B stored in the B area of the RAM is
o is 20833 (10/48:20833),
Suppose that the calculation result 4 in the processing block 204 in FIG. 7 changes almost unchanged until time 1++, and then at time t
Assuming that there is a 10% decrease in rotational speed for the first time between 11 and time t12, this result immediately appears as error detection data at the comparison point at time tj2, and its value Ei2 is as follows. E1z= 20833・(7+1-1)/s −208
33! ;26o(2) It is assumed that the motor 1 is accelerated based on the error data E12, but as a result, the rotational speed of the motor 1 returns to the specified value between time ti2 and time t+5 (actually, it is assumed that Since the mechanical time constant of the motor 1 is large, it is impossible for the rotational speed to return to the original speed instantaneously, but it is assumed that this is the case to make the explanation easier to understand. The calculation result in processing block 204 in FIG. 7 is still 260. However, in the cumulative value of the speed error from time t3 to time t12 stored in the C area of RAM 7, there is a value at time t1.
Since a history of error data from time t1 to time t+2 remains, by executing the calculation in processing block 205 in FIG. 7 (the calculation result becomes zero), time t1
It is possible to obtain error data that accurately reflects changes in the rotational speed of the motor 1 in the interval from time t+5 to time t+5. Even in the verification after time t+5, processing block 204
Although the calculation results at step 206 are affected by the decrease in the rotational speed of the motor 1 during the period from time t11 to time t12, these effects are all canceled out by executing the calculation at processing block 206. In the above explanation, the rotational speed of the motor 1 is at a specified value in advance and the speed change occurs only in a specific section. However, the C area of the RAM 7 stores the cumulative value of error data in each section Since it is stored, even if speed changes occur one after another in each section, a correct error output can be obtained without delay. That is, the detected error value En at any time tn from time tn-+ is as follows. In the embodiment of the present invention shown in FIGS. 1 and 6, (3
) formula Dn-a is stored in the D area of the RAM 7, nn is stored in the temporary register 17, B,
is stored in area B of the RAM 7, and the final term of equation (3) is stored in the area of the RAM 7 as a cumulative value. Now, in the embodiment shown in FIG. 1, although the time difference between one period of the output signal of the speed generator 2 is measured, it is as if the repetition period of the output signal of the speed generator 2 is As shown in Figure 8 (j), one-eighth of the original signal
However, even if the accuracy of the output voltage of the programmable voltage source 6 is slightly lower, no major inconvenience will occur. For example, assuming that the output signal of the speed generator 2 is a sine wave, the voltage at the upper output terminal 6& of the programmable voltage source 6 from time 1++ to time tl in FIG. 8 is (
1) If the ideal value given by the formula is 1% lower than the maximum value from the intermediate potential, then at time t1
The interval from time t1 to time t12 becomes narrower by about 3%. However, from time 1++ to time tea'! Considering the sections of one cycle in , if the intervals in a particular section become narrower, the intervals in other sections will necessarily widen, and in the current example, the interval from time t12 to time t15 will be about 3% wider. . Therefore, even if the interval from time 1++ to time ti2 is narrow, if there is no speed change of motor 1 in this interval, the error detection values obtained in processing blocks 202 to 205 in FIG. The speed change will be correctly reflected in the output. In this way, from address 711 of the RAM shown in FIG.
If the past history is correctly recorded up to address 18, as is clear from equation (3), high-resolution control that is essentially the same as increasing the frequency of the output signal of speed generator 2 can be performed. However, for that purpose, the motor 1
It is necessary to write the history into the E and C areas of the RAM from the time the system starts up until the time it switches to high-resolution control, and at that time, it is necessary to sufficiently reflect the division accuracy of each section divided into eight sections. There is. For example, the section from time t8 to time 1++ in FIG.
Hereinafter, this will be abbreviated as the first section. )1 time tj+ to time t
12 (hereinafter abbreviated as 2nd section) 1 section from time t12 to time t15 (hereinafter abbreviated as 3rd section) 9 section from time t15 to time t14 (hereinafter referred to as 4th section) ). Section from time t+4 to time t1s (hereinafter abbreviated as the 6th section) 1 Section from time t+s to time t16''& (hereinafter abbreviated as the 6th section) 9 Section from time tl to time t+7 (Hereinafter, it will be abbreviated as the 7th section.)9 The division errors of the section from time t+7 to time t18 (hereinafter, abbreviated as the 8th section) will be δ1, δ2, and δ, respectively.
5. δ4, δ5. δ6. δ7゜δ8, and if the interval that should be detected when there is no division error at the time of measurement is Tn + the deviation from the desired direction is Kn, then the time from motor 1 starting until switching to high-resolution control is When measuring the intervals of each section in between,
The error εn (n=1.2...8) left at addresses 711 to 718 in area E of RAM 7 is as follows. en = Eyl + Tl °δn (4) The dn factor caused by this division error cannot be completely eliminated even after switching to high-resolution control, so its value must be adjusted to the required control accuracy. If it is relatively large, the expected high-resolution control will not be possible. To solve this problem, either reduce the value of dn itself, or grasp the size of dn using a learning function, prepare it as a fixed offset value in the RAM 7, and then shift to high-resolution control. Methods such as the following can be considered, but as explained above, the method of reducing dn itself is not preferable because it involves increasing the precision of the analog circuit, and the latter method is expected to be effective.The method is described below. An example will be explained. First, the state in which the rotor of the motor 1 is stopped or rotating at a very slow rotational speed can be determined by, for example, monitoring the repetition period of the signal shown in FIG. 8(b), and is determined in advance. If the rotation speed is less than the specified limit value, set the discrimination flag and read the data from addresses 711 to 718 in the E area of the RAM in Figure 6 and C.
Zero is stored in address 720 of the area, and the maximum error data in the plus direction is sent to the latch 22. As a result, the motor 1 is fully accelerated, so its rotational speed gradually increases and remains below the limit value.
At that point, the discrimination flag is reset, and thereafter the timing controller 26 and ALU 19 are caused to perform a series of operations as described below. FIG. 9 shows the timing controller 26 at this time.
This is a flowchart showing an outline of the operation of the ALU 19, and it is determined whether or not the trailing edge of the output signal of the waveform shaper 4 has arrived at the branch 901, that is,
It is determined whether or not it is time ty in FIG. 8, and if yes, the process moves to processing block 902, but if not, the process returns to branch 901. Note that if the determination in the branch 901 is performed not only at the trailing edge of the output signal of the waveform shaper 4 but also at the leading edge, if the determination result at this point is negative, the next time The determination of
This is performed at time tv in the figure, allowing for more fine-grained detection. Subsequently, at branch 902.903, time t6
When time t6 arrives, in processing block 90.4, the count value T of counter 16 is
0 at address 706 in area D of RAM 7, and waits for the arrival of time t7 in branch 9Q6i. In processing block 906, temporary register 1
7, the count value TO of the counter 16 at time t7 is transferred, and the value stored in the address before the address of the D area of the RAM 7 specified by the channel selector 6 (indicated as (D) dn in FIG. 9) is transferred. The value of temporary register 17 is subtracted from
Furthermore, in branch 907, it is determined whether the subtraction result left in the accumulator of ALU 19 is larger than a reference value Bp prepared in advance, and if yes, the process moves to branch 908; otherwise, Return to the first branch 901. That is, the processing from branch 9Q1 to branch 907 measures the interval from time t6 to time t7 in FIG.
When it exceeds Bp, it is assumed that the amplitude of the signal waveform shown in FIG. . In this case, it is assumed that the amplification gain of the voltage control amplifier 3 is not controlled and is kept at a fixed value. Now, branch 908 waits until time t8 arrives (note that if the transition is made to branch 909 after measuring the interval from time t1z to time t's, branch 909 waits for time t+4 to arrive). ) Then, in processing block 909, the count value of the counter 16 is stored in the D area of the RAM 7. Branch 910 waits for the arrival of time 1v, and waits for the arrival of time 1v.
When , the count value TO of the counter 16 at that time is stored in address 730 of the G area of the RAM 7 in processing block 911 . Furthermore, branch 912 waits until the next trigger signal arrives, and when the trigger signal arrives, processing block 913 transfers the count value of counter 15 to temporary register 17, and then processing block 90
9, the count value of the counter 15 is transferred to D of the RAM 7.
Store in area. Branch 910 waits for the arrival of time 1v, and waits for the arrival of time tv
When TC arrives, the current value of the counter 15 is stored at address 730 in the G area of the RAM 7 in processing block 911. Furthermore, branch 912 waits until the next trigger signal arrives, and when the trigger signal arrives, processing block 913 transfers the count value of counter 16 to temporary register 17, and transfers the count value of counter 16 to the The value of the temporary register 17 is subtracted from the value stored at the address before the address of the area, the result is stored in the E area, and the value of the temporary register 17 is further transferred to the D area. Also, whether or not time t18 has arrived in branch 914 (R
By monitoring the AM address, it is possible to recognize the arrival of a specific time. ), and if it is true, it moves to branch 915, but if it is not, it moves to branch 9.
Return to step 12 and repeat the same process. As a result, from address 701 to 708 in area D of RAM7
At each address, the time t11+tl2+t+5.
tl4 ・t15 , t16 ・tl, ,
The count value of the counter 16 in tea is stored,
Addresses 711 to 718 in area E contain data depending on the intervals of the 1st section, 2nd section, 3rd section, 4th section, 6th section, 6th section, 7th section, and 8th section, respectively. Stored. Branch 915 waits until time 1w arrives,
When time tw arrives, at processing block 916,
The count value TO of the counter 16 at that time is transferred to the temporary register 17, and the value of the temporary register 17 is subtracted from the count value at time 1v stored in address 730 of the G area of the RAM 7, and the result is stored in the RAM 7.
The accumulator value is further divided by 8, and the result is stored at address 733 in the J area of RAM7. Therefore, the address 733 of RAM7 is stored from time 1v to time 1. The average speed of motor 1 up to
This means that data representing the speed of the motor 1 in the section is stored. Branch 917 waits until time 'h+ arrives,
Subsequently, in processing block 918, the count value TO of the counter 15 at time t2+ is transferred to the tempo tree register 17. Next, in processing block 919, the data at address 711 in area E of RAM 7 is transferred to address 731 in area H, the value of temporary register 17 is transferred to address 701 in area D, and the data is stored at address 708 in area D. The value of the temporary register 17 is subtracted from the value obtained, and the result is stored at address 711 in area 2. Furthermore, from the value stored in the H area, 7 in the E area is
After subtracting the value stored at address 11,
Divide by a fixed value of 20 and store the result at address 732 in the area. Next, in processing block 920, control data (M
SB 1" becomes a switching command for the bus selector 28,
The lower four bits correspond to data from the control bus 8. ) to address 716 of RAM 7 or 7.
After setting address 25 to be selected, RAM7
The value stored in the J area is subtracted from the value stored in the E area at address 716, and then the value stored in the B area is multiplied, and the multiplication result is stored in the C area. Divide by the value, store the value in the C area, multiply it by 2.6 and store it in the F area at address 726, and subtract the value stored in the B area from the value stored in the C area. Then, divide the result by 8, and then
The value stored at address 726 is subtracted from the division result, stored at address 715, and sent to control bus 27 with [0
0000] control data is sent to RAM7.
The address selection is returned to the channel selector 5, and the value of the accumulator is stored at address 711 of the E area. In the processing block 921, first, the control bus 27
Send control data [11o10] to R
After setting so that address 716 or 726 of AM7 is selected, the value stored in area A is subtracted from the value stored in area J, and the result is stored in area H. Also, multiply the value stored in the A area by a fixed value of 4.6, add the value stored at address 716 in the E area to the result, and then subtract the value stored in the J area. Action 1. Next, multiply the value stored in the B area, divide the multiplication result by the value stored in the H area, divide that value by 8, save it to the H area, and store it in the C area. Add this value to the value and store it again in the C area, multiply the value saved in the H area by 6.6, and store it in the F area.
26, subtract the value stored in area B from the value stored in area C, then subtract the value stored in area A, divide the result by 8, and then After subtracting the value stored at address 726, it is stored at address 71e in area E, and the control data (ooooo) is sent to the control bus 27, returning the address selection of RAM 7 to channel selector 6, and changing the address of the accumulator. The value stored at address 711 in area E is added to the value, and the addition result is stored again at address 711. In processing block 922, first, control data [10100] is sent to control bus 2, and R
After setting so that address 714 or 724 of AM7 is selected, the value ' stored in area A is added to the value stored in area J, and the result is stored in area H. Also, from the value stored at address 714 in area E,
Subtract the value stored in the A area multiplied by a fixed value of 3, then subtract the value stored in the J area, multiply it by the value stored in the B area, and apply the multiplication result to the H area. Divide by the value stored in the area, further divide by 8, save it to the H area, add this value to the value stored in the C area, store it again in the C area, and save it to the H area. Multiply the value by O, S and store it in address 724 of area F, subtract the value stored in area B from the value stored in area C, and then add the value stored in area 1. Add, divide the result by 8, subtract the value stored at address 724 from the division result, store it at address 714 in area E, and send control data of (ooooo) to control bus 27. Then, the address selection in the RAM 7 is returned to the channel selector 5, the value stored at address 711 of the E area is added to the value of the accumulator, and the addition result is stored again at address 711. In the processing block 923, [1] is sent to the control bus 27.
0001] control data is sent to RAM7.
After setting so that address 717 or 727 of Store. Also, from the value stored at address 717 in area E,
Subtract the value stored in the A area multiplied by a fixed value of 6, then subtract the value stored in the J area, and then multiply the value stored in the B area.
Divide the multiplication result by the value stored in the H area, further divide by 8, save it in the H area, add this value to the value stored in the C area, store it again in the C area, and The value saved in the area is tripled and stored in address 727 of the F area, and the value stored in the B area is subtracted from the value stored in the C area. subtract the value twice and convert the result to 8
After subtracting the value stored at address 727 from the division result, store it at address 717 in the E area, send the control bus 27K (0000 (1)), and select the address of RAM 7. is returned to the channel selector 6, the value stored at address 711 of the E area is added to the value of the accumulator, and the addition result is set to 7.
Store it again at address 11. In the processing block 924, [1] is sent to the control bus 27.
01o1] control data is sent to RAM7.
713 or 723 is selected, double the value stored in the A area and add it to the value stored in the J area, and store the result in the H area. Also, the value stored in the E area is multiplied by a fixed value of 6, the value stored in the E area at address 713 is added to the result, and the value stored in the J area is then subtracted. Multiply the value stored in area B, divide the multiplication result by the value stored in area H, further divide by 8, save in area H, and add this value to the value stored in area C. The value saved in the H area is tripled and stored at address 723 in the F area, and the value stored in the B area is calculated from the value stored in the C area. Executes subtraction, then adds the value stored in the E area twice, divides the result by 8, subtracts the value stored at address 723 from the division result, and then adds the value stored in the E area to address 713. Store it in
Send the control data [oo00o] to the control bus 27, return the address selection of RAM 7 to the channel selector 5, add the value stored at address 711 of the E area to the accumulator value, and add the addition result to 7
Store it again at address 11. In processing block 926, (1) is sent to control bus 27.
oooo) control data is sent to RAM7.
After setting the address 718 or 728 to be selected, subtract the value stored in the I area multiplied by 3 from the value stored in the J area.
Store the result in area H. Also, multiply the value stored in the I area by a fixed value of 9, add the value stored at address 718 in the Z area to the result, and then subtract the value stored in the J area. , then multiply by the value stored in area B,
Divide the multiplication result by the value stored in the H area, further divide by 8, save it in the H area, add this value to the value stored in the C area, store it again in the C area, and The value saved in the area is multiplied by 0.8 and stored at address 728 of the 7 area, and the value stored in the B area is subtracted from the value stored in the C area. Subtract the stored value three times, divide the result by 8, subtract the value stored at address 728 from the division result, store it at address 718 in the E area, and send it to the control bus 27 (0000 Send the control data in (1), return the address selection in RAM 7 to channel selector 6, add the value stored at address 711 in area E to the value in the accumulator, and read the addition result back to address 711. In the processing block 926, the control bus 27 receives [1].
1110] control data is sent to RAM7.
Set so that address 712 or 722 of
Store in area. Also, from the value stored at address 712 in area E,
After subtracting the value stored in the A area multiplied by a fixed value of 13.6, the value stored in the J area is subtracted, and the value stored in the B area is multiplied.
Divide the multiplication result by the value stored in the H area, further divide by 8, save it in the H area, add this value to the value stored in the C area, store it again in the C area, and The value saved in the area is multiplied by 6.5 and stored in address 722 of the F area, and the value stored in the B area is subtracted from the value stored in the C area before being stored in the area. Add the values three times, divide the result by 8, subtract the value stored at address 722 from the division result, store it at address 712 in the E area, and send it to the control bus 27 [Q000o]. control busk is sent, the address selection in RAM 7 is returned to the channel selector, the value stored at address 711 of the E area is added to the value of the accumulator, and the addition result is stored again at address 711. Furthermore, in processing block 927, after inverting the sign of the value stored in area C of RAM 7, the value is multiplied by a fixed value of 2.6 and stored at address 721, and
Transfer the value stored in address 1 to area C, subtract the value stored in area B from the value stored in area C, and then transfer the value stored in area 4 to
Multiply and subtract, divide the result into 1/8, subtract the value stored at address 721, and transfer it to latch 22. It is also stored at address 711 in area E. At this point, the first step to transition to high-resolution control is
The learning operation of the step is completed, but processing block 9
The meaning of the series of processing from block 18 to processing block 927 will be explained below. First, as a prerequisite for moving from branch 907 to processing block 908, it is determined whether or not the interval of the third section or the seventh section approaches a predetermined road during the acceleration period of motor 1. When detecting and correcting errors, the speed shown in Figure 8 (
Since the amplitude of the signal waveform (2L) itself changes, and the degree of change in the interval of each section with respect to the amplitude change also varies, the voltage control amplifier 3 is used to create a state as close as possible to the state in which amplitude control is actually applied. This is because the correction accuracy can be improved by performing the learning operation in step 9. By the way, FIG. 10 shows the first, second, third, and third sections when the rotational speed of the motor 1 starts from the time t8 in FIG. 8 and increases with constant acceleration. The increase/decrease in the rate of change of the reciprocal of the interval in the four sections is calculated using the amount of speed change per section as the horizontal axis, and the calculation is based on the following equation. Vn = N-Vp-5in(2-rr-aR-t+π
/B) Here, N = 1 + -t (e) In equation (6), t represents time, α is a coefficient that determines the output signal frequency of speed generator 2, and equation (6) k is a coefficient that determines the speed increase rate of motor 1, that is, the size of the horizontal axis in Fig. 10, and the other coefficients are (1)
It follows the formula. Regarding the third section, the value of 1/△N·△T is a negative number (because the influence of the amplitude amplitude is extremely large), but in FIG. 10 they are plotted in the same quadrant. From Fig. 10, although the rate of change in each section varies greatly, it is highly unlikely that the rotational speed of the motor 1 changes by several tens of percent during one-eighth period of the output signal of the speed generator 2. Taking into account that there is no such difference, it can be seen that the speed increase rate does not change much within the practical range if it is the same section. By the way, in the flowchart shown in Figure 9,
This property is utilized to further improve correction accuracy. That is, the processing in processing block 920 calculates the division error offset amount 05 of the sixth section expressed by the following equation and the sixth section
This means that the period-converted speed error E5 in the section is calculated. Os = 2-5 ・(Xs −Dz/s) ・Bo/
Dz (ηXs = (Dz Bq)/8 0
s (8) However, x5 is the value measured at the interval of the 6th section from time t14 to time t's, and DZ + BO are each RAM70G
The average speed information stored in area B is the desired value stored in area B of RAM7, and DZ/8 is the average speed information stored in area B of RAM7.
It is stored in the J area of . Now, in equation (7), Dz/s is the value that should originally be measured when there is no division error in the sixth interval, and by subtracting that value from the actual measured value, the right side of equation (4) The second term is determined, but since this value is the division error of the section according to the rotational speed at the time of measurement, if the rotational speed changes, the value corresponding to the error of the section will also change. Therefore, when the rotational speed of the motor 1 is near the set value, the division error component is the division error value of the section at the time of measurement.
B. It is obtained by multiplying by the ratio of Dz representing the rotational speed at the time of measurement. By the way, the first part of equation (7) is multiplied by 2.5. The rate of change of the interval in each section after shifting to high-resolution control is corrected, and the rate of change is calculated based on the following equation. Vn=N4p-5in (2-yr・α-N-t-1-n
・π/8) (9) However, n = 1.2, 3.4 Figure 11 shows the rate of change in each interval when starting from each interval from 1st to 4th in the same way as Figure 10. Within the practical range, the first section, second section, and third section are shown.
The values of the rate of change in the interval and the fourth interval are J6 and ej, respectively.
6, 3.0, 0.8. Note that the values for the 6th to 8th sections are the same as those for the 1st to 4th sections. Figure 12 (&) shows the relationship between the measurement interval value, offset amount, and error when the rotational speed of motor 1 becomes faster than the set speed, where the measured value is M and the set value is Z (Z
(M), offset amount is 01, calculated error is Ec
, if the original error is Ed, the calculated error Ec
and the original error Ed are expressed by the following equation. Ec=M-z-o
flQIEd=M-Z-0・M/Z
(111 i.e. the calculated error ICc
is larger than the original error Ed by (1-M/Z)·0, and error data is output so as to make the rotational speed of the motor 1 higher than the original error 1. therefore. The rotational speed of the motor can approach the set speed more quickly. Furthermore, since multiplication and division are not used in calculations, calculations can be executed quickly and the configuration can be simplified. Figure 12 (b) shows the relationship between the value of the measurement interval, the amount of offset, and the error when the rotational speed of motor 1 becomes slower than the set speed (Z>M), similar to (a-). , the calculated error Kc and the original error Kd are expressed by the following equations. Ec=Z-M-0(121 Ed=Z-M-0・M/Z 13
1, that is, the calculated error Ec is the original error Ed
The error data is output so that the rotational speed of the motor 1 becomes lower than the original error Ed by (1-M/Z)·0. Therefore, the rotational speed of the motor can approach the set speed more quickly. Next, the processing in processing block 921 calculates the division error offset amount 06 of the sixth section expressed by the following equation and the speed error E6 of period multiplication in the sixth section. 06=6.5・(X6+4-5-A-Dz/s)X B
o/ (B・(Dz/a A) ) f141E
6 = nz/ 8 A-Bo/ 8 0b
(151 Note that f141 , (In formula 151, A is the value stored in I-work!77 of RAM7, the interval of the first interval from time t8 to time 1++ is xl, and the interval of the first interval from time tea to time tl is , if the intersection of one section is Xlj, it is expressed by the following formula: A=(X+XH)/8・;2-5 (
161 In other words, ``person'' represents the amount of change in speed for each section, and 2.6 in the denominator of equation 00 is the rate of change in the first section obtained from FIG. In the round equation, the second term is the division error value obtained from the rotational speed of the motor 1 at the time of measurement and the speed change amount A for each section, and in addition to that value, the desired value BO of the rotational speed and the rotation at the time of measurement. By multiplying by the ratio (8.(Dz/8-A)) representing the speed, the division error component of the section 6 when the rotational speed of the motor 1 is near the set value is determined. Also, the fixed values of 6.6 and 4.6 in the round formula are the 11th
This is the rate of change in the 6th section obtained from the figure and Fig. 10. On the other hand, the process in processing block 922 calculates the division error offset amount 04 in the fourth section expressed by the following equation and the speed error z4 in terms of period in the fourth section. o4=o,s・(X43.3A Dz/8)×Bo
/(8・(Dz/80m))uηE4=DZ/B+person−
BQ/8-o4 Q81(
In equation 17), the division error component of section 4 when the rotational speed of motor 1 is near the set value is calculated in the same manner as equation 141. .3 is the rate of change in the fourth section obtained from FIG. 11 and FIG. Find the speed error E7 in period conversion. 07=3・(X7−3・2−mu−Dz/8)x Bo/
(s ・(Dz/ 8 2 ・A ) )
(191E7 = Dz/ 8 2A Bo/ 8 0
7 (21 (In formula 191, even though the rotational speed is higher in the 7th section than in the 6th section, x
The reason why 7-3.2.person is executed is that, as explained earlier, the illumination of the rate of change in the 7th and 3rd sections is opposite to that in the other sections. Similarly, in processing block 924, a division error offset amount 03 in the third section expressed by the following equation and a period-converted speed error E5 in the third section are determined. Os = 3・(X5 +3-2-A-Dz/8)x
Bo/ (8・(DZ/8+2・A) )
(211E3=DZ/8+2-A-Bo/8-Os
(Z) Also, in the processing block 926, the division error offset amount 08 of the 8th section expressed by the following equation and the 8th section
The period-converted speed error E8 in the section is calculated. o8=o,s ・(x8+3・3・A−Dz/8)x
Bo/ (8・(Dz/s-3・A) ) (
23) Ea = Dz/s 34-B, )/s o8
(24) In processing block 926, the second
The division error offset amount 02 of the section and the period-converted speed error E2 in the second section are determined. 02 =6.5= (X2-4.5・3 A-Dz/s
)XBo/(8・(Dz/8+34)) (
25) E2=Dz/8+34 BO/8 o2(2
61 Furthermore, in processing block 927, the division error offset amount o1 of the first section expressed by the following equation and the speed error E1 of period conversion in the first section are determined. 01=-(02/ 6-5+05/ 3+0410.
8+05/2.5+06/6-6+07/3+0810
．． 8) (5) E+ = J/a
-4・A Bq/s o, (281 The right side of the formula is the sign of the sum of the normalized division error components from the second section to the eighth section stored in the C area of RAM 7 is inverted. , its calculation is based on the following formula: △δ = o (support) k = 1 (191, (21), n, We have obtained the division error components when is near the set value.Now, (8), (151, (19), (201)
, ■, (goods), ■, (support) formula, the fifth. 6th. 4th. 7th degree 3rd. 8th. Second. Ward 1 1
Offset amount between o5, 06, 04.07, 03, 0
8,02,01, but this operation only needs to be performed once before shifting to high-resolution control, and after that, addresses 711 to 718 in area E of RAM7 are
Since an offset of 01 to 08 always remains, the control operation can then be shifted to the one shown in the Lelow chart of FIG. 7. Despite this, the reason why the offset amount for each section is left in the RAM70F area is to prepare for re-learning to further improve the correction accuracy, and also because the rotation speed of motor 1 has been changed and the offset amount for each section is left in the RAM70F area. This is to enable a faster transition to high-resolution control by referring to the offset amount of the F area, without having to perform all the operations shown in Figure 9 again. be. Furthermore, in processing blocks 919 to 927 in FIG.
Although detailed corrections as shown in formula (support) are faithfully executed, whether or not such corrections are necessarily necessary must be determined depending on the system scale and situation. For example, if the correction is performed in a state where the rotational speed of the motor 1 is controlled to be constant using the signal shown in FIG. 8(b) in advance, then in the model, BO/(s
・The operation of multiplying by (nz/s-A) is unnecessary, and AL
U19 only needs to have the function of an adder and a bit shift function (by the way, multiplication of fixed values as shown in FIG. 9 can be easily realized by a combination of addition and shift; for example, 2 (To multiply by 6, the original value shifted to the right and shifted to the left can be added.) Therefore, the configuration becomes simple. In this way, in the servo device of the present invention shown in FIG. The deviation of the generation time of the output signals of the comparators 11 and 12 from the normal time that equally divides the AC signal waveform generated by the speed generator 2 is calculated by RAM7 and ^LT). 19 and the calculation result is added as an offset value to the E area in the RAM 7 where the history of speed errors is stored, thereby enabling more accurate control. By the way, in the embodiment shown in FIG. 1, the offset controller 1o operates so that the high potential section and the low potential section of the output signal of the waveform shaper 4 are equal, but as is clear from the above explanation, for example, , time t11 in FIG.
Counter 1 at t+4, t15, tea
5 count value D11 + J4 + D15 +
Since both D+'[+ are once stored in the RAM 7, the offset can be adjusted based on these data. That is, (D1+ −D14 ) is CI)+s D
By adjusting the input offset value of the voltage control amplifier 3 so that it is equal to Even the imbalance between the upper and lower outputs can be corrected. Furthermore, if the difference between (D111h4) and (D+s DH) becomes exactly zero, the number of addresses in the RAM 7 shown in FIG. 6 can be halved. That is, in the embodiment, " is from time t1 to time 1+ in FIG.
For example, at time tH, the count value at time t11 is subtracted from the count value of the counter 15 at time t1. Considering the half-cycle section up to t5 as a reference, at time t5, time t1
By subtracting the count value at time t5 from the count value at time t5, the RAM areas from addresses 706 to 708 and from addresses 716 to 7 of the RAM area in FIG.
Addresses up to 18, and even addresses 726 to 728, are no longer needed. Furthermore, if the period between time t2 and time t3 in FIG. 8 and the period between time t6 and time t7 in FIG. 8 are adjusted to be constant under a predetermined frequency, the period shown in FIG. By utilizing the fact that the amplitude of the signal waveform is constant, the amplitude can be adjusted digitally. For example, the amplitude controller 9 in FIG. 1 is configured with an up/down counter (which may be a software counter configured in an additional area of RAM) and a digital-to-analog converter, or when the yarn upper limit value is exceeded during the period between time t6 and time t7, the up/down counter is counted down;
If the count is increased when the lower limit value is exceeded, the amplitude can be adjusted step-by-step. t5. t6. Since the count value of the counter 16 at t7 is once taken into the RAM 7, the timing controller 26 and the RAM 7. A series of operations can also be performed by the person LU19. Note that the output signal of the amplitude controller 9 is supplied to the voltage control amplifier 3 after the series of error correction processes shown in FIG. The point at which the amplification gain of the voltage control amplifier 3 is set is 1 from time t1 to time t8.
You can freely choose at each point in the cycle, and the 8th
The set value is held for at least half a cycle of the signal waveform shown in FIG. 2L. Therefore, as described above, the detection gain of the speed error in each section within the divided half cycle has different values as shown in FIG. 11. Although the flowchart in FIG. 7 does not mention correction for this variation in detection gain, for example,
In the processing block 206 of FIG. 7, before the accumulator value is transferred to the latch 22, it is also possible to perform correction using a gain correction table prepared in advance. Immediately after the motor 1 is started, the amplitude of the output signal of the speed generator 2 is extremely small, so even if the output signal of the comparator 11 at time t1 in FIG. The potential of the output signal of is shown in Figure 8 (2L
) The comparator 11 may not generate an output signal at time t2 without rising to the stage shown in FIG. For this reason, in the embodiment shown in FIG. 1, a second comparator 12 is provided separately from the comparator 11 to constantly monitor the rise and fall of the potential of the output signal of the voltage control amplifier 3. It is configured as follows, and the time 't, z, iy
. . . is configured to reset the up/down counter of the channel selector 6, so that the channel selector 6
will never send an incorrect address selection signal to RAM 7. Furthermore, by preparing both the first comparator 11 and the second comparator 12, it is possible to prevent the system from malfunctioning even if a surge pulse is mixed into the output signal of the speed generator 2. It will be done. For example, if a surge pulse larger than the step value of the output voltage of the programmable voltage source 6 is superimposed on the output signal of the voltage control amplifier 3 between time t1 and time t2 in FIG. 8, although there is a slight time difference, Since both the comparator 11 and the comparator 12 generate outputs (because many surge noises appear in the upper and lower directions of the waveform diagram in the form of ringing and are superimposed on the original signal), the channel By appropriately setting the acceptance conditions of the input signal in the selector 6 (for example, one of the clock signals
Within the period - It is set so that acceptance is prohibited when output signals from both comparators arrive. ), the noise immunity of the system can be significantly improved. If there is no concern about such noise, the output terminal 6b of the programmable voltage source 6 and the comparator 12 can be deleted, and the only output terminal 6a and the only comparator 11 can be used in a time-sharing manner. The device shown in Figure 1 can also realize the operational functions shown in Figure 8 (f'l, (g), (h), (i)). The variation in the speed error detection gain at each sampling point has been explained assuming that the output signal of the speed generator 2 in Fig. 1 is a sine wave. ,
This applies when the amplitude does not change depending on the rotational speed of the motor 1 (specifically, when the speed generator 2 is configured with a shutter plate and a light receiving element whose light transmittance gradually changes depending on the rotational position). ), the speed error detection gain at each sampling point does not change, and
The amplitude controller 9 is also unnecessary. Further, in the embodiment shown in FIG. 1, the 16-bit count value of the counter 16 is transferred as is to the ALU 9, and the calculation result at the h'ptz 9 is transferred to the latch 22 via the data bus 21. In this case, the 16-bit operation result is directly transferred to the latch 2.
2, the error detection gain (discrimination gain)
becomes extremely small. For example, in the example of equation (2), it is calculated that the error detection value becomes 260 when the rotational speed of motor 1 changes by 10%, but if the overall bit length is 16 bits, then
This value amounts to only O-4 percent, and as a result requires very high resolution and gain in power amplifier 26 of FIG. Therefore, in practice, a pit compression operation is performed to substantially increase the error detection gain during the data exchange and calculation process between the ALU 19 and the RAM 7. The specific method, the specific configuration of the ALU 9, timing controller 26, etc. in FIG. 1, and the read-only memory IJ (ROM
) and 9 are detailed in the specification of Japanese Patent Application No. 183760/1983 filed by the same applicant as the present application, so they will be omitted here. As described above, according to this embodiment, by providing a plurality of reference points in one cycle or half cycle section of an AC signal having speed information of a motor, linear motor, etc., speed detection having a substantially higher frequency can be achieved. However, the embodiment of the present invention is not necessarily limited to the device shown in FIG. 1, and the embodiment of the present invention is not limited to the device shown in FIG. In linear motors, for example, the 8th
The distance traveled can also be determined with high accuracy by counting the output signals shown in Figure (j). Effects of the Invention As described above, the present invention provides a voltage source that generates at least two preset output voltages (in the embodiment, the programmable voltage source 6 generates two output voltages, vl and vl). (However, if the configuration is configured to generate even more output voltage, control with higher resolution will be possible.) and the potential of the AC signal having the output of the voltage source and the velocity information of the moving object. a comparator (in the embodiment, two comparators 11 and 12 are used) that generates an output signal twice or more during a half cycle of the alternating current signal; and a reference clock signal. A counter for counting, a memory means for storing the count value of the counter at the time when the output signal of the comparator is generated, and an arithmetic unit (in the embodiment, an ALU1) for calculating an error output from the count value.
9 is used, but an adder or a counter may also be used. ), a driving means (in the embodiment, a power amplifier 26) for supplying driving power to the movable body based on the error output, and measuring the output signal of the comparator over at least half a period of the alternating current signal, The deviation amount of each section is calculated from the value of each section between the output signals of the comparator calculated from the measured value and the normal value, and the deviation amount of each section is calculated from the speed of the moving object at each measurement time and the normal value. An error that causes the arithmetic unit to correct the error output at each measurement point by converting the position quantity into a value at which the moving body is moving at a speed at which the value in each section becomes the normal value, and using that value as a correction amount. Output correction means (in the embodiment, the timing controller 26 and the RA
M7. ALU19 constitutes an error output correction means. ), it is possible to perform control with higher resolution without increasing the output frequency of the speed generator, that is, control that is essentially equivalent to increasing the output frequency of the speed generator. It can be done and the effect is extremely effective.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a servo device according to an embodiment of the present invention, Fig. 2 is a circuit wiring diagram showing a specific example of a voltage control amplifier, and Fig. 3 is a circuit wiring diagram showing a specific example of a channel selector. Figure 4 is a signal waveform diagram to explain the circuit operation of Figure 3, Figure 6 is a circuit connection diagram showing a specific example of a programmable voltage source, Figure 6 is a memory map showing the configuration of RAM, and Figure 7 is a timing chart. Flowchart for explaining all operations of the controller, FIG. 8 is a signal waveform diagram for explaining the operation of the device in FIG. 1, FIG. 9 is a flowchart for explaining error correction operation by the timing controller, FIG. 10 FIG. 11 is a characteristic diagram showing interval change characteristics with respect to speed changes in each divided section, and FIG. 12 is a diagram showing the relationship between measurement section values and errors. 1...Motor, 2...Speed generator, 6
...Channel selector, 6...Programmable voltage source, 7...RAM, 15...
...Counter, 26...Power amplifier, 28.
...timing controller. Name of agent: Patent attorney Toshio Nakao and 1 other person No. 4
Figure <L) Figure 5 Figure 8 Figure 9 (C)
(Con EXT Figure 9 (e2 (child 2EX
I Figure 9
()l) EXT Figure 9 (t), C Figure 12 Mama - □

Claims (2)

[Claims] (1) A voltage source that generates at least two preset output voltages, and a voltage source that compares the output of the voltage source with the potential of an AC signal having speed information of a moving object, and then compares the potential of the AC signal that has speed information of the moving object during a half period of the AC signal. a comparator that generates an output signal twice or more; a counter that counts reference clock signals; a memory means that stores a count value of the counter at the time when the output signal of the comparator is generated; an arithmetic unit that calculates an output; a driving unit that supplies driving power to the movable body based on the error output; and an output signal of the comparator that is measured over at least half a cycle of the AC signal, and calculated from the measured value. The deviation amount of each section is calculated from the value of each section and the normal value, and the value of each section is the normal value for the deviation amount from the speed of the moving object at each measurement time and the normal value. A servo device comprising: an error output correction means for converting the speed into a value at which the moving body is operating, and using the value as a correction amount to cause the arithmetic unit to correct the error output at each measurement time. (2) Each time the comparator generates an output signal for at least half a cycle of the AC signal having speed information of the moving object,
a channel selector for updating an address of a memory means for storing a count value of a counter; and a channel selector for updating an address of a memory means for storing a count value of a counter; It is equipped with a timing controller that causes a subtraction to be performed from a numerical value, compares the subtraction result with a desired value prepared in advance, and causes an error output to be sent to the driving means according to the magnitude thereof, and when correcting the error output, the channel selector Each time the address update signal is sent out, the interval is measured and stored in the corresponding address of the memory means, and when the storage of the measured value of the interval corresponding to at least half the cycle of the AC signal is completed, the interval is measured and stored in the corresponding address of the memory means. 2. The servo device according to claim 1, wherein the timing controller is operated to correct the division error of the alternating current signal by a computing unit and store the correction value in the memory means.