JPS6226472B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a pattern display device that displays patterns of a plurality of characters, figures, symbols, etc. at arbitrary positions on a raster scan type display device. Conventionally, in order to display patterns such as characters and figures (including symbols) on a CRT (Cathode-Ray Tube) display device, etc., the CRT screen is divided into, for example, 28 x 28 pixels, and the X coordinate on the screen is A pattern name that specifies the type of pattern to be drawn at the pixel position specified by the Y coordinate, and color information of the pattern (normally, for color display, color signals of red, green, blue, and blue are used) ) etc. are read and stored in a writable memory (RAM) using a control device. Next, all pattern commands programmed in the position of picture elements that match the scanning lines to be displayed are read out of the program contents, and the brightness and brightness of the CRT pixels corresponding to the pattern of a series of picture elements are stored in the editing memory in scanning order. The desired pattern was displayed by assembling and editing color information and sequentially transmitting the CRT pixel brightness and color information to the display unit in synchronization with the operation of the scanning system. According to this method, for example, all the information to be displayed for one horizontal scanning line is sequentially stored in the editing memory. ), it was not possible to prioritize and display multiple different overlapping patterns. That is, when two or more patterns are displayed at the same position, a plurality of pattern data will be written to the same address as the editing memory, and only the data written the latest will be stored and retained. Therefore, other previously written pattern data is erased, and the display screen displays the data after scanning, but cannot display the data before scanning. On the other hand, as a means to avoid erasing previously written pattern data, the written data is returned from the output terminal to the input terminal, and the data returned at the input terminal is logically connected to the next input pattern data. A method for obtaining the sum is provided. According to this method, if the data written to an arbitrary address in the editing memory is at the information H level that forms part of a pattern, the data written next to the same address is at the information L level. However, the above-mentioned H level information is fed back and written again through the OR gate, making it possible to hold the data. However, although the inconvenience of previously written information being erased is eliminated, the two pieces of data input to the editing memory are both written via the OR gate. In this case, there is no problem if the brightness, hue, etc. of the patterns to be displayed are the same, but if they are different, it is not possible to format and display the desired pattern as described above, and it is necessary to specify the pattern for multiple patterns. No. 1
It is also impossible to give priority to one thing. Especially in recent years, there has been a trend to make displayed patterns clearer by using various colors or multi-gradation luminance signals, to draw more complex patterns, or to display three-dimensional patterns. It is in. Therefore, conventional pattern display methods have not been able to satisfy these requirements. Furthermore, if one pattern to be displayed is composed of 8 bits in the horizontal scanning line direction, these 8 bits
Since bit display data is serially read into the editing memory bit by bit, it takes 8 bits of time to store one pattern in the editing memory. Therefore, on a screen that can display 227.5 bits per scanning line, 227.5÷8=28.4, and the maximum number of patterns that can be displayed during one scanning line period is 28 patterns. Therefore, there is also a drawback that the patterns that can be displayed on one screen are limited. An object of the present invention is to provide a pattern display device that can clearly display a plurality of patterns by adjusting the brightness and color of each pattern even when the plurality of patterns are displayed in an overlapping manner. Another object of the present invention is to provide a pattern display device that makes it possible to increase the number of patterns displayed on one screen. The present invention extracts pattern information to be displayed on one scanning line from a memory that stores pattern information to be displayed, and based on this pattern information to be displayed, pixel information on the scanning line is extracted for each scanning line. In a pattern display device that stores pixel information in an editing memory in the order in which it should be displayed and displays pixel information from the editing memory on each pixel on a scanning line, the editing memory is stored in a first
The pixel information on adjacent scanning lines is edited and stored alternately in each memory part, and the stored pixel information is displayed with priority in each memory part. Information indicating whether the priority display The device is characterized in that pixel information is output from the memory section to the display section. Hereinafter, one embodiment of the pattern display method of the present invention will be described in detail with reference to the drawings. FIG. 1 is a block diagram of essential parts of a pattern processing apparatus showing an embodiment of the present invention. The pattern processing apparatus of this embodiment has the following four memory sections. The first is a program RAM 50 which receives address data from an address terminal AB by key operations or the like from an external control system and writes program data for pattern display into a designated address. RAM50 for this program
is for storing display pattern commands, and includes storage blocks Y, X, P, y, and C.
The Y block stores data indicating the Y coordinate of the pattern to be displayed, the X block stores data indicating the X coordinate, and the P block stores the pattern to be displayed. In addition, column position bit data in the Y coordinate (vertical) direction is written in the Y block, and priority display pattern information PR, red signal information R, green signal information G, and blue signal information B are written in the C block, respectively. The information that makes up the display pattern is RAM
50. Here, the Y-coordinate direction column position bit data stored in the y-block is the vertical position data of the display section forming one pattern, and is normally set to 0 in the initial state when programmed from outside. , are added by +1 by the adder according to the processing. Also, what is priority pattern information PR?
This is bit data indicating that a pattern for which an H level signal is set at this address position is displayed with priority over other patterns displayed at the same position on the screen. The second is pattern generation memory (ROM) 58
This ROM stores patterns of various symbols, characters, figures, etc., and programs
The data selector 92 is specified by an address that is a combination of the pattern name bit data read from the P block of the RAM 50 and the column position bit data in the Y coordinate direction read from the Y block.
is read out. In this embodiment, it is assumed that one pattern is composed of 8 bits x 8 bits. Therefore, two bits are read out in parallel four times to the data selector 92 from the pattern generation memory 58 by one address. Through these four read operations, eight horizontal bits forming one pattern are extracted. The third and fourth memories are editing memories 73 and 74
These devices each consist of a readable/writable memory (RAM) with the same structure. Each of these editing memories 7374 has four storage sections: a priority pattern storage section PR, a red signal storage section R, a green signal storage section G, and a blue signal storage section B. That is, the editing memories 73 and 74 store the program RAM 50 in accordance with the pattern information from the pattern generation memory 58.
PR, R, C, B read from C block of
Each bit data is input to the corresponding storage section via gate circuits 65-72. These four memories are program RAM50
The pattern display command data stored in the ROM is read out in address order and sent to the pattern generation ROM.
The pattern information from R, 58 is edited alternately in editing memories 73 and 74 for each scanning line.
Output terminal R as color serial signal information of G and B.
G and B are output, and a color pattern is displayed on a desired picture element using horizontal scanning lines. In this display method, for example, color serial signal information output from output terminals R, G, and B is converted into a color difference signal by a color signal conversion matrix, phase-modulated by a color width carrier wave, and sent to a receiving device together with a luminance signal. However, in order to simplify the explanation, the processing after the color information is output from the output terminals R, G, and B will be omitted here. Now, in explaining the operation of this embodiment, a method for interconnecting the four memories described above will be described below. Address data AB input from an external device is input to the program RAM 50 via the switching circuit 53. Connected to this switching circuit 53 is a data pointer register 51 that specifies read addresses in order from the smallest address value in which a display pattern is stored. Each time the RAM 50 is addressed, the data pointer register 51 is incremented by +1 by the +1 adder 52, and when all the display pattern programs in the RAM 50 are addressed, it is set to the initial value 0 again. The Y coordinate data of the pattern command read by addressing the data pointer register 51 is input to the adder 54. The adder 54 also inputs the column position bit data y in the Y coordinate direction of the pattern command. The Y coordinate bit data and the column position bit data y in the Y coordinate direction are added and input to the circuit 55. On the other hand, matching circuit 5
The output data from the adder 54 and the count output of the vertical counter Vc are input to 5, and when the two match, a match signal is output. This coincidence signal is input to the +1 addition circuit 57, which performs +1 addition to the value of the column position bit data y in the Y coordinate direction. Normally, the y block of the pattern code input from an external device to the program RAM as a program command is set to 0, and the Y block of the display pattern is set to 0.
An automatic addition operation of +1 is performed each time the coordinates match the contents of the vertical counter. In this embodiment, since the number of vertical bits forming one pattern is 8 bits, the above addition operation is performed 7 times.
form two patterns. On the other hand, the X coordinate data stored in the X block of the program command is input to the adder 91 and is input separately.
2, 4, 6) and is added to the editing memory 7.
3,74 write addresses are specified. The data from the P block in which the pattern name is stored is used together with the column position bit data y as address data for the pattern generation ROM 50.
The y bit data forms its lower address data. Addressed pattern generation ROM5
From 8 onwards, 8 bits of pattern information in the horizontal direction (H for picture elements where a pattern is formed,
For picture elements that are not formed, L) is output in parallel in two bits at a time via the data selector 92.
This 2-bit parallel data is sent to the
A total of 8 bits is input four times to either the editing memory 73 or 74 specified by the address created by the block data and the value of ΔX. The editing memory is selected by the switching circuit 63 in accordance with the least significant bit data H and L of the vertical counter 56. Pattern information input to the editing memory via the switching circuit 63 is first supplied to gate circuits 65-72. Each gate circuit has an editing memory 73, 74
It is provided corresponding to each of the memory blocks PR, R, G, and B constituting the memory block, and is composed of the following logic gate groups. The gates 65 and 69 have the same structure and have four input terminals D, E, I, and V as shown in FIG. is connected to the OR gate 82, and this
The output of OR gate 82 and signal V are AND gate 8
3, and the output of the AND gate 83 is connected to the PR memory of the editing memory. The gate circuit shown in FIG.
2 in PR memory (priority pattern information storage memory)
They are provided individually. This is because the pattern information read from the pattern generation memory 58 is output in two bits in parallel, and a gate circuit is required for each of the two bits. Furthermore, editing memory 7
3, 74 gate circuits 66 to 6 provided corresponding to each memory storing R, G, and B color information.
8, 70 to 72 are all composed of logic gate groups shown in FIG. 2b. The five input signals D, E, I, V, and F inputted in FIG.
and its positive output is connected to AND gate 8
8, the inverted output via inverter 86 is
It is input to AND gate 89. Signal V is input to both AND gates 88 and 89. Also, signal E is
To the AND gate 89, the signal F is input to the AND gate 88, and the outputs of the AND gates 88, 89 are supplied to the corresponding R, G, B memory via the OR gate 90. Two gate circuits each shown in FIG. 2b are provided for each of the R, G, and B memory blocks of the editing memory. Here, the input signals D, E, I, V, and F input to each logic gate group will be explained. Signal D is a signal fed back from priority pattern information storage memory PR and is commonly input to all gate circuits 65-68, 69-72. The signal E includes priority pattern information PR, red information R, green information G, and blue information B read out from block C of the program ROM 50, and is input to the corresponding memory blocks. Signal I is pattern information read from pattern generation memory 58, and is input four times with two bits per pattern.
The signal V is the lowest bit data of the vertical counter (Vc) 56, and is sent to the gate circuits 65 to 65 of the editing memory 73.
68 is supplied with a signal inverted by the inverter 64, while gate circuits 69 to 72 of the editing memory 74 are supplied with positive output signals, respectively. Therefore, when the lowest bit of the vertical counter (Vc) 56 is L, the editing memory 73 is selected, and when it is H, the editing memory 74 is selected.
is selected. That is, the editing memories are alternately selected for each scanning line in the vertical direction. Furthermore, the signal F is a signal that is input only to the gate circuits 66 to 68 and 70 to 72, and is input from the red, green, and blue color information storage memories R, G, and B of the editing memories 73 and 74 to the corresponding gate circuits, respectively. Two bits of the fed back color information signal are output and fed back in parallel. On the other hand, the X coordinate data input to the adder 91 is subjected to an addition operation of Δ×(0, 2, 4, 6,) and input to the switching gates 61 and 62. The count output from the horizontal counter (HC) 60 is also input to the switching gates 61 and 62, and the vertical counter VC56
The editing memory 73,
74 address specification. Here, the X coordinate data controls writing to the editing memory, and the horizontal counter controls reading. Editing memory 73, 74
The R, G, and B information signals edited in
In response to the least significant bit data of 6, one of the color information signals is transmitted through parallel-to-serial conversion registers 78, 79, and 80, which correspond to two bits each in parallel.
The red, green, and blue serial color signals are outputted to a color signal conversion matrix circuit that generates R-Y and B-Y color difference signals. The operation of the pattern display system of this embodiment using the pattern generator having such a configuration will be described in detail below. A display pattern program is written into the program RAM 50 having Y, X, P, y, and C memory blocks. This writing method involves inputting RAM address information from address input terminal AB and writing program data via a data bus (not shown). At this time, when the circuit block shown in FIG. 1 is formed on one chip and configured as a single element, various writing methods such as external key input operation and magnetic tape reading are possible. Furthermore, when configured as a one-chip microprocessor together with a normal microcomputer such as an ALU and a CPU, write operations can be executed within the chip by program control or the like. Address input switching gate 5 of the program RAM 50 in which the display pattern program is written
3 is switched, the contents of the data pointer register 51 are sequentially incremented by +1 from 0, and the address of the program RAM 50 is specified. That is,
The address specification by the data pointer register 51 is for one scanning line in the vertical direction.
All addresses of RAM 50 are specified. Now, if the vertical counter Vc56 is "0", the data pointer register 51 performs address designation in order from address "0" in the RAM 50, and searches for a program in which "0" is stored as Y coordinate data. For example, if Y coordinate data "0" is stored in address value "3" of the RAM 50, a match signal is output from the match circuit. This match signal opens the gate 59 of the pattern generation ROM 58 and transfers the pattern information addressed by the pattern name P set to the address value "3" of the program RAM 50 to the pattern generation ROM 58.
8 and write 2 bits at a time in parallel to the address value of the editing memory 73 specified by the X coordinate data. This 2-bit parallel data is processed by an adder 91 in which the X coordinate data is sequentially converted to △×0,
Addition operations of 2, 4, and 6 are performed, and based on the address data thus created, 2 bits each are written to the editing memory four times, so that a total of 8 bits of data is stored in the editing memory 73. Note that all data written to the editing memory 73 is sent to the program RAM via gate circuits 65 to 68.
Priority pattern information PR, red information R, green information G, blue information B read from C block 50
The logically operated data is stored in each corresponding memory block. In other words, address value 3 of the program ROM has X on the 0th vertical scanning line.
This means that a pattern to be displayed starting from the coordinates is programmed. When all of this pattern data is edited in the editing memory 73, an addition operation of +1 is performed on the column position bit y in the Y-coordinate direction of the program RAM 50, and a new value of "1" is added.
data is written to the y memory block.
Furthermore, the data in the data pointer register 51 is also +1.
It is added to designate the next address "4".
In this way, a match is detected for each count value indicated by the vertical counter Vc 56 with respect to all display pattern programs set in the program RAM 50. Therefore, as a result, the value "0" indicated by the Vc counter 56, that is, all the patterns to be drawn on the 0th scanning line in the vertical direction are stored in the editing program 73. Thus, when pattern editing on the 0th vertical scanning line is completed, the vertical counter Vc56 is incremented by 1, and a search for a pattern to be displayed on the next scanning line is started.
At this time, memory 74 is selected as the editing memory for storing pattern data. As mentioned above, this
Since the least significant bit of the Vc counter 56 becomes "1", the gate groups 69-72 of the editing memory 74 are opened, and the gate groups 65-68 of the editing memory 73 are closed. In response to the content "1" of this Vc counter 56, the data pointer register 5
1 specifies an address for the program RAM 50 starting from address 0. At this time, the Y coordinates of the program data that can be matched by the matching circuit 55 are the address where data "1" is stored and the address where the pattern to be displayed on the previous 0th vertical scanning line is stored. It is. That is, since the Y coordinate data Y and the column position bit y read out to the adder 54 from the address where data "1" is stored are "1" and "0", respectively, the data obtained by adding the two is becomes "1",
This matches the contents of the Vc counter 56. On the other hand, when the previous 0th vertical scanning line, that is, the Vc counter 56 was "0", the Y coordinate data of the address value (address value "3" in the above example) that was matched was "0".
However, data “1” added by +1 is written to the column position bit, so the data input from the address value “3” to the addition 54 is the Y coordinate data “0” and the column position bit. Both data y and "1" are input, the output data from the adder 54 matches the contents of the Vc counter 56, and the pattern data is written into the editing memory 74. At this time, the pattern generation ROM58
The address designation is performed by the sum of the pattern name data from the P block and the column position bit y to which an addition operation of +1 has been performed. As a result, edit
The 8-bit data displayed on the first vertical scanning line is edited in the ROM 74 according to the pattern program. Further, the y block of the program in the program RAM 50, that is, the column position bit data to be edited as pattern information in the editing ROM 74, is added with +1 and written to the address value. In the above example, the data "2" is written to the Y block with the address value "3", and the program with the address value "3" is written to the editing memory 73 even when the Vc counter 56 changes to "2".
To 1 pattern vertically 3rd horizontal 8
Edit and store bit pattern data.
In this embodiment, since the number of bits in the horizontal and vertical directions forming one pattern is set to 8 bits each, the addition operation for column position bit y is 7 bits.
It is circulated. Therefore, by searching the program RAM 50 eight times using the data pointer register 51, one pattern of data can be edited. That is, one complete pattern can be displayed using the 0th to 7th vertical scanning lines. It is clear from the above description that even if other pattern information is included in this vertical scanning line, that pattern can be displayed. In this way, when the editing for the 0th to 7th vertical scanning lines is completed, the y block data of the address value whose column position bit y value is "7" is set to the initial value, and the y block data of the address value whose column position bit y value is "7" is set to the initial value, Editing of pattern information is executed continuously. This operation
By performing the same operation on the data counted and output by the Vc counter 56, one screen's worth of display is performed. Therefore, the counting range of the Vc counter 56 only needs to be able to count the vertical scanning line of the screen.
Note that, for example, the pattern information (R, G, B color information) edited in the editing RAM 73 is stored in the editing RAM 74.
When the pattern data on the next scanning line is being edited, 2 bits are read out in parallel by the count address of the horizontal counter HC60 via the output stage switching gates 75 to 77, and the parallel to serial conversion register is read out. 78 to 80, it is converted into a series of R, G, and B serial signals and outputted from the R, G, and B output terminals. Here, a method for editing display pattern data for one scanning line to be edited in the editing memory will be described in more detail below using a specific example. Now, a method for editing the display pattern to be displayed on the K-th vertical scanning line will be described with reference to FIG. At this time, the content of vertical counter Vc56 is "K"
Therefore, the data pointer register 51 is set to the initial address value "0". RAM for program
50 is determined by this data pointer register 51.
The program data is sequentially addressed starting from address 0, and the program data whose Y coordinate data is "0" is searched.
Now, when an address value in which Y coordinate data "0" is stored is specified as pattern a, the matching circuit 55 outputs a matching signal with the Vc counter 56. At this time, data "0" is set in the Y block. The above match signal is from the pattern generation ROM
The output gate 59 of 58 is opened. Pattern generation
The pattern data stored in the address specified by the pattern name of the P block is outputted from the ROM 58 in parallel, two bits at a time. This data is the data set in the X block.
Write data to that address value as the address for writing to. Let the X coordinate data currently stored in the X block be "i". Vc counter 5
Since the least significant bit of 6 is "0", edit
73 is selected as the RAM, and display pattern data is written sequentially from the i-th address to 8 bits, that is, address i+7. This display pattern data is 8-bit pattern data read from the pattern generation ROM 58, and is further read out from the editing RAM 7 along with PR, F, G, and B information set in the C block of the program RAM 50.
Written in 3. That is, the pattern data shown in FIG. 3a is the address value i to i+7 of the editing memory 73.
written to the address. Thereafter, the patterns shown in b, c, and d of the figure are written into the editing RAM 73 in 8-bit units starting from each X-cosi line. As is clear from the figure, when four different patterns a, b, c, and d are programmed for the Kth vertical scanning line, these four patterns are displayed superimposed on the same picture element. This results in a combination of patterns that cannot be displayed using conventional pattern display methods. In this embodiment, as shown in Table 1, the program RAM 50 is used for each pattern a, b, c, d.
PR, R, G, and B commands are specified in the C block.

[Table] As shown in FIG. 3A, the pattern a command read from the program RAM 50 becomes 8-bit data of "10111001", and is sent to the gate group in parallel 2 bits at a time via the AND gate 59. It is supplied to I terminals 65 to 68.
On the other hand, if the least significant bit of the Vc counter 56 is "0", an inverted signal "1" is applied to the V terminal of each gate group via the inverter 64, and as is clear from FIGS. gate output stage
Open AND gates 83, 88, 89. The signal fed back from the PR memory of the editing memory 73 is added to the D input terminal of the gate, and now this PR
It is assumed that a signal "0" is output from the memory. (Here, it is assumed that in the initial state of each editing RAM 73, 74, all memory elements are reset and set to "0".) Therefore, PR
If the signals input to the input terminals E and I are "1", the editing memory 7 is input to the memory gate (Fig. 2a).
3 is written in the PR memory at addresses i and i+1, but as is clear from FIG. 3a, the pattern data at addresses i and i+1 are "1, 0", respectively. On the other hand, for programs
Since PR, R, G, and B are "1, 1, 1, 0" respectively as shown in Table 1, the data read from the C block of the RAM 50 is i, i of the PR memory.
“1, 0” are written to the +1 address, respectively. Furthermore, for each memory of R, G, and B, each i, i
At address +1, "1, 0" is input to the R memory, "1, 0" to the G memory, and "0, 0" to the B memory. Thereafter, addresses are added based on the Δx information (2, 4, 6) input to the adder 91, and addresses “1, 4, 6” are added to addresses i+2 to i+7 of the editing memory 73.
1, 1, 0, 0, 1” priority bit data red,
Green color information data and “0, 0, 0, 0,
0, 0,'' blue information data is written into each memory. Next, the contents of the data pointer register 51 are added and when the program of pattern b shown in FIG. Two bits are read out in parallel from the generation ROM 58 and applied to the I input terminals of the gate groups 65-68. On the other hand, this pattern b data “1,
0, 1, 1, 1, 1, 1, 1” is the editing RAM 73
The data will be written to addresses i+2 to i+9, but among these addresses, data of pattern a has been previously written to addresses i+2 to i+7, and this data of pattern a will be written to addresses i+2 to i+9. The program is set so that it is displayed with priority. Therefore, gate group 6
Pattern b input to each I input terminal from 5 to 68
As is clear from FIG. 2, the output gate 89 is closed by the PR data of signal "1" fed back from the priority pattern PR memory to the D input terminal, and the R, G,
Each color information of B is not written to the editing RAM 73, and the previously written data of pattern a is rewritten from the input terminal F via the AND gate 88. However, at addresses i+5 and i+6 where the priority bit data of pattern a is not written, data of pattern b, that is, color information of G and B shown in Table 1 is written. From the above explanation, in this embodiment, when two different patterns are displayed on the same pixel, the pattern for which priority display is specified may be erased by another pattern or displayed at the same time as the other pattern. You can see that it is clearly displayed without any Note that the address i+8, i where the data of pattern b exists
At address +9, "1" is written in the G and B memories, respectively. Therefore, three-dimensional display is also possible. Next, when the data pointer register 51 searches for the program of pattern C, i+
The pattern data shown in FIG. 3C is written in addresses 6 to i+13, and as is clear from Table 1, this pattern C is designated as a priority pattern display. That is, addresses i+8 to i+
Until address 13, data of pattern C is written to the corresponding R memory unless a priority pattern display has been performed before, but since pattern a priority display is stipulated for address i+7 forming pattern C. For example, even if pattern C is a priority pattern, information on previous pattern a is retained. On the other hand, pattern b has been written at address i+b, but since pattern b is not a priority display pattern, the information of pattern b is erased and data of pattern C is newly written. Next, for the data of pattern d, since this pattern has no priority display designation, address i+
Data in the form of pattern d is written only to addresses 2 to i+7 where no priority pattern is written. At this time, for example, information of pattern b without priority designation is set at address i+5, but in this case, data of pattern d input later is written. This is to avoid mixing and changing the displayed colors if different patterns that do not have priority designation are displayed on the same picture element and both are displayed. FIG. 4 shows the state of pattern data edited for one vertical scanning line K in this manner. As shown in the figure, when patterns a, b, c, and d are edited sequentially at addresses i to i+13 on one vertical scanning line K, the data written to addresses i to i+13 of the editing RAM 73 are as shown in FIG. become that way. The display pattern data on the K-th vertical scanning line edited as shown in FIG. 5 is addressed by the horizontal counter HC60 via the gates 75 to 77 in FIG. Circuit 78~
80 and is input to terminals RG, B as a serial color signal.
Based on the edited data shown in Figure 5 that is output to the color conversion matrix circuit, etc., the colors actually displayed on the screen are yellow, background color, yellow, yellow on the i to i+13 , yellow, green, red, yellow, red, green,
The order is red, background color, red, red. Here, the background color refers to picture elements on which no pattern is formed, i.e., i+1, i
This is the background color of the pattern for address +11, and is created as background color information from the background color display control system. In this way, according to this embodiment, by providing a priority display command and controlling the color pattern data input to the editing RAM using this command,
Even when different patterns are formed overlapping each other, patterns can be displayed preferentially according to a preset program. That is, even if a non-priority or priority pattern is input after the priority pattern has been edited, the previously written priority pattern will not be erased. Furthermore, when non-priority patterns are input, the pattern input later is displayed. Further, when a priority pattern is input after a non-priority pattern, the previously input non-priority pattern is erased and the priority pattern is displayed. Therefore, when displaying a pattern using this embodiment, for example, when a moving object passes over an obstacle, it is possible to pass in front of the obstacle or to hide behind the obstacle and pass behind it. , more complex patterns can be clearly displayed. Furthermore, in this embodiment, when writing pattern data into the editing RAMs 73 and 74, two gate circuits are installed in each of the two gate circuits shown in FIG. 2 so that two bits can be written in parallel.
Although the configuration in which each pattern is provided has been proposed, the number of patterns that can be edited in the editing RAM during one scanning line period can be doubled compared to the conventional method. That is, in a method of editing pattern data to be displayed on the next scanning line while displaying in one scanning line period, it is possible to display more pattern information by increasing the writing speed of editing data. Become. Therefore, if eight gate circuits are provided each, eight times as many patterns as before can be displayed. That is, in this embodiment, if the reading/writing frequency of the editing data in the editing RAMs 73 and 74 is 3.58 MHz, the clock frequency applied to the parallel-to-serial conversion registers 78 to 80 may be doubled to 7.16 MHz. At this time, the writing frequency per pattern is
3.58MHz ÷ 4 = 895KHz, and if one scanning line frequency is 15.75KHz, 895KHz ÷ 15.75KHz = 56.8
becomes. Therefore, in this embodiment, a maximum of 56 8-bit x 8-bit patterns can be displayed on one scanning line. Also, the number of display patterns per screen is
3.58MHz ÷ 15.75KHz = 227.3, and if the number of display patterns per screen is P and the number of display patterns per scanning line is A, then from the relational expression 4A + (P - A) = 227, P = 227 - 3A. Become. Therefore, if 20 patterns are displayed in one scanning line, 167 patterns can be displayed on one screen. Furthermore, as mentioned above, when writing edit data in 8-bit parallel to RAM, it is sufficient to prepare an 8-bit configuration register as a parallel-to-serial conversion register. 91 becomes unnecessary. Here, increase the frequency at which pattern data is read from the editing RAM by 8 times.
If the frequency is 28.64MHz, a maximum of 227 patterns can be displayed on one scanning line. Also, the display frequency band at this time is 14.3MHz. By increasing the number of display patterns in this manner, the movement pattern can be displayed with a finer movement resolution, so that more natural movements and shapes can be obtained. In this embodiment, the program RAM 50
The pattern generation ROM 58 can also be provided with a control program area for specifying coordinate change, pattern change, pattern deletion, color change, game progress, etc., and these control programs are read out during the vertical scanning blanking period. It is clear that process control can be achieved. In addition, program RAM, pattern generation ROM, editing memory
The memory that constitutes RAM may be either static memory or dynamic memory, and in particular, editing memory RAM is read out every scanning line.
After being read, for example, the priority bit data PR
Since the memory is set to a reset state by setting 0 to 0, there is no need to refresh even if a dynamic memory is used as long as this write or read period is shorter than the memory refresh period. Further, in this embodiment, the priority bit command is included in the program RAM 50, but the priority bit command may be configured to be supplied to the editing memory separately, or the pattern data may be stored in the program RAM. If the pattern generation ROM is included, the pattern generation ROM is not required.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the main parts of a pattern information generation circuit showing one embodiment of the pattern display device of the present invention, FIG. 2 is a logic block diagram of a gate circuit used in the pattern information generation circuit, and FIG. The figure is a data diagram showing pattern information displayed on one scanning line, and Figure 4 a, b, c, and d are state transition diagrams when the pattern information shown in Figure 3 is written into the editing memory. FIG. 5 is a diagram of pattern data written in the editing memory. 50...RAM for program, 51...Data pointer register, 52, 57...+1 adder,
54, 91... Adder, 55... Matching circuit, 56
... Vertical counter, 58 ... Pattern generation
ROM, 59...AND gate, 60...Horizontal counter, 61, 62, 53, 63, 75, 76, 7
7, 80, ... switching gate, 64, 85, 86,
...Inverter, 65-72...Gate circuit group,
73, 74...Editing memory RAM, 78, 79,
80...Parallel-serial conversion register, 92...Data selector, 81, 83, 88, 89,...
AND gate, 82, 90...OR gate, 87...
...NAND gate.

Claims (1)

[Claims] 1 Extract the pattern information to be displayed on one scanning line from the memory that stores the pattern information to be displayed, and edit the pixel information on the scanning line for each scanning line based on this pattern information to be displayed. In a pattern display device that stores pixel information in a memory in the order to be displayed and displays pixel information from an editing memory on each pixel on a scanning line, the editing memory is divided into a first and a second memory section, and each pixel information is stored in a memory section. The pixel information on adjacent scanning lines is edited and stored alternately, and information indicating whether or not the stored pixel information is to be displayed with priority is stored in each memory section, and paired with the pixel information. and stores pixel information from the other memory section to the display section while writing/non-writing pixel information to one memory section based on information indicating the priority display. A pattern display device characterized by: