JPS62264343A - Storing device for action information history and performance measurement information - Google Patents

Abstract

PURPOSE:To obtain the action information history and the performance measurement information via the same memory means by adding a counting means for performance measurement information, a counting means for reference signals, a selecting means for replacement signals, a selecting means for replacement stop request signals, etc. CONSTITUTION:An input information selecting means 402 selects the action information side and a replacement stop request signal selecting means 404 selects the fault detecting signal side. The a replacement signal selecting means 407 selects the 2nd reference signal side. Under such conditions, the action information histories of a fixed past period are always stored in a memory means 400. While the means 402 is set to select the side of a counting means 401 together with the means 404 set to select the side of an address means 403 and the means 407 set to select the side of a reference signal counting means 406 respectively. At the same time, a replacement enable display means 405 is set by the replacement start request signal. Then the performance measurement information is stored in the means 400.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a device that stores information in an information processing device on a 1Mi basis, and particularly relates to an operation information history and information processing device useful for analyzing the cause of a failure in the information processing device. The present invention relates to an apparatus for storing performance measurement information useful for performance measurement of an information processing apparatus using a common storage means.

[Conventional technology]

When an information processing device goes down due to a failure, in order to make it easier to analyze the cause of the failure, information on each part of the information processing device, such as register information, has been stored for a predetermined period of time. A history of operating information for a certain period in the past is left in the storage means by storing it in a storage means as operation information every time a failure occurs, and stopping the storage process when a failure occurs.

In addition, performance evaluations of information processing devices are performed during development evaluations before shipment of information processing devices, and at that time, information useful for performance measurement, such as the number of cache miss hints in cache memory, may be collected. It is being done.

Conventionally, the storage of the operation information history and the collection of performance measurement information have been carried out as follows.

[Storage of operation information history] FIG. 3 is a block diagram of a conventional operation information history storage device, which includes an information history storage means 300, and operation information to be input into the information history storage means 300 from among a plurality of pieces of operation information. an input information selection means 301 for selecting an input information selection means 301 and an address means 302 for supplying a write address of the information history storage means 300;
, an update start requesting means 303 , a failure detection means 304 for detecting a failure of the information processing apparatus, and an update start requesting means 30
updatable display means 305 that is set by the output of No. 3 and reset by the failure detection output of the failure detection means 304;
An update control means 306 controls the address means 302 and the information history storage means 300 each time a reference signal arrives according to the output contents of the updatable display means 305, and reads out the operation information history stored in the information history storage means 300. It is composed of a reading means 307.

When an update start request is issued from the update start request means 303 with the input information selection means 301 selecting a group of input information necessary for troubleshooting the information processing device, the update possible display means 305 is set, and the update control means 306, the address means 302 and the information history storage means 300 are updated each time a reference signal arrives. That is, the address means 302 is updated to point to the next address,
The input information selection means 3016 output is the information history storage means 30
A write to 0 operation is performed on each arrival of the reference signal.

Since the address means 302 is updated so that when it points to the final address, it returns to the first address, the information history storage means 300 constantly stores the history of operating information within a certain period of time. become.

If a failure occurs in the information processing apparatus while the above operations are being performed, this is detected by the failure detection means 304, and the updatable display means 305 is reset. As a result, the update control means 306 stops updating the address means 302 and the information history storage means 300. Therefore, the information history storage means 300 stores operating information for a certain period of time from the time when the failure was detected. The history will remain stored. Therefore, by reading out the contents of this information history storage means 300 by the reading means 307 and analyzing it, it is possible to grasp the operation of the information processing apparatus up to the time of occurrence of the failure.
Effective fault search becomes possible.

[Collection of performance measurement information] On the other hand, as shown in FIG. 4, to collect performance measurement information of the information processing device, a dedicated performance measurement device 401 is installed separately from the information processing device 400, and the performance measurement information is collected in the operating state. The output terminal 402 from which the information processing VT device 400 can be taken out
By connecting the input terminal 403 of the performance measurement dedicated device 401 to the output terminal 402 with a cable or the like, the performance measurement dedicated device 401 collects and stores performance measurement information.

[Problem that the invention seeks to solve]

In this way, in the past, storing operating information history and collecting performance measurement information were performed using separate devices, and in particular, collecting performance measurement information required special equipment such as a device dedicated to performance measurement. . However, in general, performance measurement dedicated devices are expensive because they cannot correctly collect performance measurement information unless they have performance comparable to or higher than the target information processing device. In addition, recently, the performance and degree of integration of information processing devices have improved significantly, so it has become difficult to obtain dedicated performance measurement equipment that can handle this. It is also becoming difficult to prepare.

The present invention has been made in view of these circumstances,
The purpose is to add some hardware to a conventional performance information history storage device so that the storage device can also collect performance measurement information.

[Means for solving problems]

The present invention was made with the focus on the fact that there is extremely little need to simultaneously accumulate operating information history and collect performance measurement information, and in order to achieve the above object, the principle diagram shown in FIG. As shown, a storage means 4 including a plurality of storage units
00, a counting means 401 for counting performance measurement information, and an input information selection means 402 for selecting input information to the storage means 400 by receiving the operation information and the output of the counting means 401 as inputs.
and an address means 403 that sequentially updates the write address within a predetermined address range and adds it to the storage means 400 each time an update signal is applied, and a signal indicating that the address means 403 has generated a predetermined address and an information processing device. an update stop request signal selection means 404 which takes the failure detection signal as an input, selects one of the inputs and outputs it as an update stop request signal, and is set by the update start request signal;
Updatable display means 4 reset by an update stop request signal output from update stop request signal selection means 404
05, a reference signal counting means 406 that notifies a signal indicating that when a predetermined number of first reference signals have been counted, and a second reference signal and a notification signal from the reference signal counting means 406, Update signal selection means 407 that selects and outputs one of the inputs, and update possible display means 40
5 is set, the update signal selection means 407
The update control means 408 applies the output of 1 to the address means 403 as an update signal and also to the storage means 400 as a write instruction signal, and the reading means 409 reads out the contents of the storage means 400.

[Effect]

Input information n3! When the i selection means 402 selects the operation information side, the update stop request signal selection means 404 selects the fault detection signal side, and the update signal selection means 407 selects the second reference signal side, the main storage The device accumulates the operation information history. That is, when the update enable display means 405 is set by the update start request signal, the contents of the address means 403 are updated at the timing when the second reference signal arrives, and the update is started. A write instruction signal is output from the control means 408 to the storage means 400, the operation information is stored in the area of the storage means 400 corresponding to the address generated by the address means 403, and when the second reference signal appears again next time, The operation information at that time is stored in the next address generated by the address means 403, and by continuously performing such operations, the operation information H history of a certain past period is always accumulated in the storage means 400. .

When a failure occurs in the information processing device vi, the updatable display means 405 is reset by the failure detection signal, so the update control means 408 no longer sends a write instruction signal to the storage means 400, and the storage means 400 The operation information history from the time of failure to a certain period in the past remains accumulated.

On the other hand, the input information selection means 402 selects the counting means 401 side, the update stop request signal selection means 404 selects the address means 403 side, and the update signal selection means 407 selects the reference signal counting means 406 side. Then, when the update enable display means 405 is set by the update start request signal, the zero MM1 device collects performance measurement information.

That is, each time performance measurement information is generated, it is counted by the counting means 40.
1, the first reference signal is counted by the reference signal counting means 406, and when a predetermined number of first reference signals are counted, the address means 40 is counted by an update signal from the update control means 408.
3 is updated, and the write instruction signal is sent to the storage means 4.
Served at 00. Therefore, when the output of the counting means 401 is stored in the area of the storage means 400 corresponding to the address generated by the address means 403, and the first reference signal is counted a predetermined number by the reference signal counting means 406 again, The output of the counting means 401 at that time is stored in the next address generated by the address means 403, and by continuing this operation, the memory means 400
The outputs of the counting means 401 are sequentially accumulated. Then, the generated address of the address means 403 is stored in the storage means 40, for example.
When the predetermined value indicating the final address of 0 is reached, a signal indicating this is selected by the update stop request signal selection means 404, the updatable display means 405 is reset, and the storage means 400
Further memory to is stopped. The content related to the performance measurement information stored in the storage means 400 can be read by the reading means 409 to, for example, an information storage device (not shown). Then, if it is insufficient to collect the storage capacity of the storage means 400, an update start request signal is generated again.
Operations similar to those described above are repeated.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 2 is a block diagram of an embodiment of the present invention, showing a configuration provided in an information processing device.

In the figure, a counter circuit 1 constitutes a reference signal counting means, and counts a first reference signal applied to a terminal 111, and when an overflow occurs, a carry-out No. 13
61 is output.

Counter circuits 21 to 24 constitute a counting means for performance measurement information, and count performance measurement signals applied to terminals 121 to 124, respectively, and output count signals 221 to 224.

The memory circuit 3 is composed of, for example, a static random access memory or a register file group having n memory units, and the write enable signal 1 applied to the terminal
31 is on, the contents of the write and data signals 151-154 applied to terminal -0 are stored in the address indicated by the write address signal 141 applied to terminal -8. Also,
For example, when the write enable signal 131 is off, the terminal R
The memory contents of the address indicated by the read address signal 132 applied to A are read out, and a read data signal 133 is outputted from the 8 terminals.

The counter circuit 4 constitutes an address means, and the update signal 14
Each time 2 is added, the contents are incremented. The counter value of this counter circuit 4 is inputted to the storage means 3 as a write address signal 14'1. When the counter circuit 4 is incremented sequentially from the first address to the last address of a plurality of storage units in the storage means 3, it overflows and a carry-out signal 17 is generated.
Generates 1.

The selector circuits 51 to 54 constitute input information selection means, and input the operation data of the terminals 251 to 254 to which the contents of registers of each part of the information processing device are added, and the counter circuits 21 to 2.
One of the four count signals 221 to 224 is selected and outputted to the storage means 3 as write data signals 151 to 154.

The selector circuit 6 constitutes update signal selection means, and the terminal 16
2 and the carried signal of the counter circuit 1, and outputs it as an update signal 163.

The selector circuit 7 constitutes update stop request signal selection means,
A fault detection signal applied to the terminal 172 from a fault detection means (not shown) and a carry-out signal 171 of the counter circuit 4
One of these is selected and outputted as an update stop request signal to the flip-flop 10 constituting the updatable display means.

The update start request circuit 9 generates a signal requesting the start of updating of the counter circuit 4 and the memory circuit 3. The flip-flop 10 is set by the signal from the update start request circuit 9, and the flip-flop IO is set by the signal from the update start request circuit 9, and the update from the selector circuit 7 is started. Reset by stop request signal.

The output of the flip-flop 10 is applied to one input terminal of an AND circuit 11 constituting update control means, and the update signal 163 from the selector circuit 6 is applied to the other input terminal of the AND circuit 11. Therefore, AND circuit 11
An update signal 142, which is the same as the update signal 163, appears at the output of the flip-flop 10 only during the period when the flip-flop 10 is set. This becomes a set signal to the flip-flop 12 that generates 131.

The continuation unit 8 includes a read address counter circuit 13, a data register circuit 14, and their control circuits (not shown), and sends a read address signal 132 from the read address counter circuit 13 to the tα circuit 3. However, the read data 133 from the storage circuit 3 is received by the read data register circuit 14.

The information storage section 15 is composed of a magnetic disk device, a magnetic tape device, a floppy disk device, or the like, and has a larger storage capacity than the storage circuit 3. Information storage section 15
1 receives and stores data from the read data register circuit 14 of the read section 8, and is provided with a read circuit and a control circuit for this purpose, although not shown.

Next, the operation of this embodiment will be explained by case.

[Accumulation of operation information history] When storing the history of operation data signals indicating the contents of registers of each part of the information processing device in the storage means 3, selector circuits 51 to 54 are connected to terminals 251 to 2 to which the operation data signals are applied.
54 side, the selector circuit 7 to the failure detection signal 172 side,
The selector circuits 6 are respectively set on the terminal 162 side to which the second reference signal is applied.

In the above state, update start request signal 1 is sent from update start request circuit 9.
When 91 is generated, the flip-flop 1O is set, and the AND circuit 11 is opened to enable updating. Further, at this time, the counter circuit 4 is reset. After that, when the second reference signal appears, the AND circuit 114:1ll
The contents of the counter circuit 4 are incremented by 1 to become "i", and the flip-flop 12 is set and a write enable signal 131 is generated in the memory circuit 3. Therefore, the operation data from the selector circuits 51 to 54 are stored at address "i" in the storage circuit 3. This operation is performed every time the second reference signal is generated as long as the flip-flop 10 is set. When the operating data is written to the final address of the memory circuit 3, the counter circuit 4 overflows and outputs a carry-out signal 171, the count value becomes the initial value again, and the operating data is written to the starting address of the memory circuit 3 again. It will be written sequentially from Note that when accumulating the operation information history, the selector 7 is set to failure detection (No. 3 172 side), so the update will not be stopped by the carry-out signal 171.
The reading unit 8 also does not perform the operation described below due to the carry-out signal.

When a fault in the information processing device is detected by fault detection means (not shown in FIG. 10 is reset and AND circuit 11 is closed. Therefore, the update signal 142 is no longer output from the AND circuit 11 after this point, and a history of operation data from the time of failure to a certain period in the past is left in the memory circuit 3.

[Collection of performance measurement information] Various types of information can be considered as performance measurement information of the information processing device, such as the number of cache misses, T
LB (Translation 1ook-asi
de buffer), the number of misses, and the appearance frequency of a certain type of instruction (hereinafter referred to as instruction A), which serves as a guide to the performance.

To collect such performance measurement information, for example, terminal 1
A cache miss hint detection signal is connected to terminal 121, a TLB miss detection signal is connected to terminal 122, and terminal 1
The instruction A decode signal is connected to the terminal 23, and other performance measurement information, if any, is connected to the terminal 124. In addition, the first reference (No. 3) connected to terminal Ill is
An instruction execution end signal is used.

When collecting performance measurement information, selector circuits 51 to
54 is set on the counter circuits 21 to 24 side, the selector circuit 7 is set on the carry-out signal 171 side, and the selector circuit 6 is set on the carry-out signal 161 side. and,
After the information processing device executes typical processing, the update start requesting means 9 generates an update start request signal 191.

When the update start request signal 191 is generated, the flip-flop IO is set and the AND circuit 11 is opened. Further, at this time, the counter circuits 134.degree. 21-24 are each reset. Therefore, from that point on, the counter circuit 21 starts counting the number of appearances of the cache mishit detection signal, the counter circuit 22 starts counting the number of appearances of the TLB miss detection signal, and the counter circuit 23 starts counting the number of appearances of the TLB miss detection signal. Start counting.

Each time an instruction is executed in the information processing device, the counter circuit 1 is counted up, and when the instruction is executed a number of times determined by its capacity, the counter circuit 1 overflows and a carry-out signal 161 is output. This carry-out signal 161 is selected by selector circuit 6, passes through AND circuit 11 in an open state, and is applied to counter circuit 4 and flip-flop 12 as update signal 142. When the update signal 142 is added to the counter circuit 4, the contents thereof are increased by, for example, 1 to "i", and the flip-flop 12 is set to output a write enable signal 131 to the memory circuit 3. Therefore, the counter circuits 21 to 21 selected by the selector circuits 51 to 54 at that time
24 count signals 221 to 224 are written to address “i” of memory circuit 3. In this case, the counter circuit l is N
If it is a bit counter, the number of cache misses, the number of TLB misses, and the number of instruction A executions that occurred during the execution of 21 instructions will be stored.

When the counter circuit 1 generates the carry-out signal 161 again next time, the contents of the counter circuit 4 become "i+lJ", and the counted values of the counter circuits 21 to 24 at that time are written to the area of the address ri+IJ of the memory circuit 3.

Performance measurement information is stored in the last address of the storage circuit 3 as described above, and when the counter circuit 4 overflows, the carry-out signal 171 is output. This carry-out signal 171 is selected by the selector 7 and resets the flip-flop 10. Therefore, since the AND circuit 11 is closed after that, even if the carry-out signal 161 is output from the counter circuit 1, the counter circuit 4 is not updated, the flip-flop 12 also remains in the off state, and the memory circuit No new data will be written to 3.

As described above, when the carry-out signal 171 is output from the counter circuit 4 in the performance measurement information collection process, the reading unit 8 successively reads out all the contents accumulated in the storage circuit 3 due to the seven outputs of the carry-out signal 171. The data is then transferred to the information storage unit 15, and the information storage unit 15 stores it. This means that a series of performance measurement information corresponding to the capacity of the storage circuit 3 can be collected. Further, when the above-mentioned transfer processing by the reading unit 8 is completed, if multiple samplings have been instructed, the update start request circuit 9 requests the update start again in response to the transfer end signal 180 from the continuous output unit 8, for example. give a signal. Therefore, the same operation as above is started again, and performance measurement information can be collected by mvt. Note that one sampling process is completed when the contents of the storage circuit 3 are transferred to the information storage unit 15, and the next sampling is performed when the update start request generation circuit 9 is activated by a command from the operator, for example. You can also do it.

In the above embodiment, the instruction end signal is used as the first reference signal applied to the terminal Ill, but if the reference clock signal is used instead, the count value of the performance measured signal is calculated every 2N reference clock cycles. If a memory request signal to the cache memory or main storage device is used, it is possible to collect the count value every 2N request cycles, and various signals can be used as the first reference signal. Can be done. Further, the selectors 6, 7, 51 to 54 can be replaced with input/output terminals and cables.

〔Effect of the invention〕

As explained above, the present invention adds a performance measurement information counting means, a first reference signal counting means, an update signal selection means, an update stop request signal selection means, etc. to the conventional operation information M history storage 'j device. By simply adding a small amount of hardware, you can use the same storage means to not only accumulate operating information history but also collect performance measurement information in the environment where the information processing device is actually operating. There is. Therefore, there is no need to install an expensive dedicated performance measurement device, and even if it is difficult to provide a terminal for extracting performance measurement information on the information processing device side, it is possible to collect one performance measurement report.

[Brief explanation of drawings]

Fig. 1 is a diagram of the principle of the present invention, Fig. 2 is a block diagram of an embodiment of the present invention, Fig. 3 is a block diagram of a conventional operation information history storage device, and Fig. 4 is a block diagram of conventional performance measurement information. It is an explanatory diagram of a collection method. In the figure, 1.4.21 to 24...counter circuit,
3... Memory circuit, 6, 7. 51-54... Selector, 8... Continuation unit, 9... Update start request circuit, 10
．． 12... Flip-flop, 11... AND circuit, 13... Read address counter, 14... Read data register, 15... Information storage section, 111...
・Terminals to which the first reference signal is applied, 121 to 124...
Terminal to which performance measured data is added, 142...Update signal, 161, 171...Carry-out signal, 162...
...Terminals to which the second reference signal is applied, 251 to 254...
・Terminal to which operation data is added, 400...Storage means, 4
01... Counting means, 402... Input information selection means,
403... Update stop request signal selection means, 405...
Updatable display means, 406...Reference signal counting means, 4
07... Update signal selection means, 409... Reading means.

Claims (1)

[Scope of Claims] Storage means including a plurality of storage units; Counting means for counting performance measurement information; Input for receiving operation information and the output of the counting means and selecting input information to the storage means. information selection means; address means for sequentially updating write addresses within a predetermined address range and adding them to the storage means each time an update signal is applied; and a signal and information processing indicating that the address means has generated a predetermined address. update stop request signal selection means that receives a device failure detection signal and selects one of the inputs and outputs it as an update stop request signal; Updatable display means that is reset by an update stop request signal output from the selection means; reference signal counting means that notifies a signal indicating that when a predetermined number of first reference signals have been counted; and a second reference signal. update signal selection means that receives the signal and the notification signal from the reference signal counting means and selects and outputs one of the inputs; and during the period when the updatable display means is set, the It is characterized by comprising an update control means for applying the output of the update signal selection means to the address means as an update signal and to the storage means as a write instruction signal, and a reading means for reading out the contents stored in the storage means. A storage device for operating information history and performance measurement information.