JPS62263531A - Decimal arithmetic system - Google Patents

Abstract

PURPOSE:To decrease the number of branching instructions, to decrease the number of program steps and to improve object efficiency by making a decimal adding instruction and a subtracting instruction into one instruction, and using an equal operator derived from codes of the two calculation and the operator as the operator of the instruction. CONSTITUTION:An equal arithmetic deriving instruction 1 guides the equal calculation from two code and operator of the number of calculation and executes the processing to determine an operator from this. A decimal adding/ subtracting instruction 2 makes a decimal adding instruction and subtracting instruction into one instruction. An arithmetic circuit 4 is composed of an arithmetic logical arithmetic device ALU and plural registers. A special register 3 sets a flag specified by the equivalent operator determined by the equal arithmetic deriving instruction 1. By the decimal adding/subtracting instruction 2, an arithmetic action to execute an arithmetic circuit 3 receives the control by the value of the flag set to a special register 4 and executes the equal calculation. Thus, adding and subtracting can be executed by one adding/subtracting instruction and it is not necessary to branch conditions by the value of the equal operator.

Description

[Detailed description of the invention] A valence operator is configured to be used as an operator for this instruction, thereby reducing branch instructions, reducing the number of program steps, and improving object efficiency. did.

[Industrial Application Field] The present invention relates to a decimal number arithmetic system, and particularly to improving the efficiency of signed decimal number addition/subtraction instructions.

U. Prior Art] FIG. 5 is a flowchart showing signed decimal operation processing according to a conventional example.

FIG. 6 is a diagram illustrating equivalent operations and equivalent operators that are completely equivalent to addition and subtraction of signed decimal numbers and have simplified signs.

FIG. 7 is a diagram showing the range of code display in C0DOL.

The conventional addition and subtraction processing of signed decimal numbers (for example, R1 and R2) will be explained with reference to FIGS. 5, 6, and 7 as follows.

(L) First, determine the validity of the sign part (positive or negative) of each of R1 and R2, that is, whether the sign value is between "A'~"Fo (see Figure 7), and whether the sign is positive or negative. Make a judgment.

(2) Next, as shown in FIG. 6, the relationship between operations (addition or subtraction 'n) between R1 and R2 is investigated, equivalent operations are identified, and the equivalent operator is determined.

(3) Using the determined equivalent operator, in the next instruction, R
It is determined whether the operation between 1 and R2 is performed by addition or subtraction, and the program branches to the respective program for addition or subtraction.

(4) Perform calculations using the addition or subtraction processing program at the branch destination.

The equivalent operator shown in Figure 6 can be found as follows, with the positive sign represented by 0°, the negative sign represented by “1”, addition by “0”, and subtraction represented by “1゛”. Here,
XOR indicates exclusive OR.

(Equivalent operator) = (RI) sign) XOR (sign of R2) XOR (original operator) (Example) R1+ (-R2') = R1-R2R
Find the XOR of the sign of 1 °0゛, the sign “lo” of R2, and the original operator “0゛, 'O'XOR'1'XOR'O' = '1'
Since the result is "lo", the equivalent operator is subtraction.

FIG. 8 is a diagram showing the flow of data in a conventional signed decimal operation.

The data flow in FIG. 8 corresponding to each step is shown on the right side of the flowchart in FIG. 5.

[Problems to be Solved by the Invention] As explained above, the conventional addition and subtraction of signed decimal numbers requires conditional branching and increases the number of program steps for processing.

The present invention aims to provide a new decimal calculation method that solves the problems of the prior art.

Means for Solving Problems] FIG. 1 is a block diagram showing the principle of the decimal calculation method of the present invention.

In FIG. 1, 1 is an equivalent operation derivation instruction, which performs a process of calculating an equivalent operation from the signs and operators of two operands and determining the equivalent operator from this.

This may be performed using a multi-step program routine as in the conventional example, or a single equivalent operation derivation/subtraction instruction may be used as one instruction.

4 is an arithmetic circuit, which is an arithmetic logic unit (hereinafter referred to as A L
(abbreviated as U) and multiple registers.

3 is a special register, and the operation of setting a flag determined by the equivalent operator determined by the equivalent operation exclusive instruction 1 is controlled by the value of the flag set in the special register 4.
Performs an equivalent operation.

[Operation] With the above configuration, addition and subtraction can be performed with one addition/subtraction instruction, and there is no need for conditional branching depending on the value of an equivalent operator.

This reduces the number of program steps and reduces processing time.

[Example] The present invention will be described in more detail below with reference to Examples shown in FIGS. 2 to 4.

FIG. 2 is a diagram showing an instruction control signal generation circuit in one embodiment of the present invention.

Indicates a register.

The equivalent operator determined by the equivalent operation output command is “O゛” for addition, and “1°” for subtraction, and the ALU41
The flag is output from the FS and set as the FS (function select) flag of the special register 30.

It can be set using the signal (2) from the ALU in the conventional example.

When an instruction is set in the instruction register 42, its operation code part is decoded by the decoder 43, and if it is an addition/subtraction instruction (for example, code 1010),
“1” is set on the signal ■.

The signal ■ from the decoder 43 and the signal ■ from the FS flag of the special register 30 are put into the register 44, and if the value is 10゛, it is considered as addition, and if the value is 11゛, it is considered subtraction. A command control signal ■ that controls the operation is output.

When the values of the register 44 are "00" and 01', it is assumed that the instruction is not an addition/subtraction instruction, and no instruction control signal is output.

FIG. 3 is a diagram showing the configuration of an addition/subtraction instruction in an embodiment of the present invention, and is shown in comparison with an instruction in a conventional example.

The individual instructions shown in FIG. 3 and their functions are as follows.

ADC --- Decimal sign addition instruction ADC
E - Decimal carry addition instruction (add carry) SDC - Decimal signed subtraction instruction 5DCE
... Decimal borrow subtraction instruction (subtract borrow) DC - - Instruction that combines ADC and SDC DCE ---- Instruction that combines ADCE and 5DCE Conventional technology (left side) ), after extracting the equivalent operator, if the operator is addition, a condition judgment is made to branch to the addition program 8Pc, and then the subtraction program sPc is entered.

In spc, first, subtraction SDC with the number of digits is performed, and when the number of digits in the operation number is large, then digit borrow subtraction 5DCE is performed, and this is performed as many times as necessary depending on the number of digits.

Next, if a borrow does not occur as a result of subtracting the number of digits, a condition judgment is set to branch to NEXT, and after this,
Complement subtraction SDC, 5 which inverts the sign of the result and takes the complement.
Provide DCE for the number of digits.

Next, a branch to NEXT is placed, and after that, ADC and ADCE are provided for the number of digits as the addition program APC.

Finally, write the address to the next process as NEXT.

In contrast, the addition/subtraction instructions (on the right) of the present invention (1) do not require conditional branching depending on the type of equivalent operator after extracting the equivalent operator; (The equivalent operator is FS
(controlled by flags).

(2) Conventional SDC, 5DCE, and DC and DCE in which ADC and ADCE are integrated are provided for the number of digits.

(Addition or subtraction is controlled by the FS flag).

(3) It is the same as the conventional technology to determine the condition as to whether it is necessary to take a complement and to provide computations DC and DCE for the complement for the number of digits.

(4) It is also the same as the prior art that NEXT is provided to instruct the next process.

As shown in comparison with FIG. 3, there are fewer branches and a much smaller number of program steps than in the prior art.

FIG. 4 is a diagram showing the format of a decimal forward/subtract instruction in an embodiment of the present invention.

FIG. 4(A) shows a decimal sign addition/subtraction instruction DC, and FIG. 4(B) shows a carry or borrow addition/subtraction instruction DCE.

■Operation code (DC or DCE) is included in the command.
), ■Data size (SIZE), ■Arithmetic result storage register (Rd), 1st operation number storage register (R3I), ■
It has a column for a second arithmetic operation storage register (Rs2).

The data size (SIZE) specifies the size of the data to be operated on. "oo" is a byte (2 decimal digits), '0
1' specifies a half word (4 digits), and "10" specifies a word (8 digits).

In the DC instruction shown in FIG. 4(A), I
``When the S flag is 0'', the contents of register Rsl and the contents of register Rs2 are added in signed decimal, and the result is added to Rd.
Store in the register indicated by .

When the FS flag is 1, the content of register Rsl and the content of register Rs2 are subtracted in signed decimal, and the result is
? Store in the register indicated by d.

In the DCE instruction shown in FIG. 4(B), the special register F
When the S flag is 0, the contents of Rsl and Rs2 are added in unsigned decimal form, a carry is added, and the result is stored in the register indicated by Rd.

When the FS flag is °1", subtract the contents of Rsl and Rs2 in unsigned decimal, further subtract Polo,
Store the result in the register indicated by Rd.

In the operation example of the signed decimal operation instruction shown in FIG. 4(A),
Word width (DCW), halfword width (DCIIW), and byte width (DCB) when the FS flag of the special register is O° and “1”, respectively.
) is shown with an example.

Here, C and D indicate signs, C indicates positive, and D indicates negative.

When FS=1, that is, when the borrow becomes "1" during subtraction, the sign of the result is inverted and the data is made into a complement.

The same applies to the calculation example using the unsigned decimal carry 7-digit borrow calculation instruction shown in FIG. 4(B).

Here, C indicates a carry or borrow from a lower order.

When FS=1, that is, when pollo becomes "1" during subtraction, the complement of the resulting data is taken.

[Effects of the Invention] As described above, according to the present invention, object efficiency can be improved by reducing the number of branch instructions and the number of program steps, and its practical effects are extremely large.

[Brief explanation of drawings]

FIG. 1 is a block diagram of the principle of the present invention; FIG. 2 is a diagram showing an instruction control signal generation circuit in an embodiment of the invention; FIG. 3 is a diagram illustrating an addition/subtraction instruction in an embodiment of the invention; 4 is a diagram showing the format of the addition/subtraction instruction in the embodiment of the present invention, FIG. 5 is a flowchart showing signed decimal operation according to the conventional example, FIG. 6 is a diagram explaining equivalent operators, and FIG. The figure shows the range of sign display, and FIG. 8 shows the flow of data in signed decimal arithmetic in a conventional example. In the drawing, ① is an equivalent operation derivation instruction, 2 is a decimal addition/subtraction instruction, and 3.
30 is a special register, 4 is an arithmetic circuit, 茵 is an instruction control register, 41 is an ALU, 42 is an instruction register,
43 indicates a decoder. R1+R2 Principle block diagram of the present invention Figure 1 Conventional example Inventive vinegar
: 0C---1Mo1Shiben2-Rd Diagram showing the format of the addition/subtraction instruction (DC) in the embodiment of the present invention @4
Diagram (A) Operation: DCE---Rsl±Rs2±
Carry -Rd operation example 2 Figure 4 (B) showing the format of the addition/subtraction instruction (DCE> in the embodiment of the present invention) Flowchart showing signed decimal operation according to the conventional example Diagram explaining equivalent operators Figure 6

Claims (1)

[Scope of Claims] Equivalent operation deriving means (1) for deriving an equivalent operation from the signs and operators of both operands and determining the equivalent operator in addition and subtraction of signed decimal numbers; An addition/subtraction instruction (2) that combines an addition instruction and a subtraction instruction, and controls the operation performed by the addition/subtraction instruction (2) using the equivalent operator determined by the equivalent operation deriving means (1). A decimal arithmetic method characterized by being configured to perform.