JPS62262102A - Diagnosis processing system for digital control device - Google Patents
Diagnosis processing system for digital control deviceInfo
- Publication number
- JPS62262102A JPS62262102A JP61104920A JP10492086A JPS62262102A JP S62262102 A JPS62262102 A JP S62262102A JP 61104920 A JP61104920 A JP 61104920A JP 10492086 A JP10492086 A JP 10492086A JP S62262102 A JPS62262102 A JP S62262102A
- Authority
- JP
- Japan
- Prior art keywords
- digital control
- control device
- memory section
- abnormality
- abnormality information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000003745 diagnosis Methods 0.000 title 1
- 230000005856 abnormality Effects 0.000 claims abstract description 28
- 238000003672 processing method Methods 0.000 claims description 11
- 238000004092 self-diagnosis Methods 0.000 claims description 7
- 230000009977 dual effect Effects 0.000 claims description 4
- 238000010586 diagram Methods 0.000 description 3
- 230000000694 effects Effects 0.000 description 2
- 238000004891 communication Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
Landscapes
- Testing And Monitoring For Control Systems (AREA)
- Safety Devices In Control Systems (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、ディジタル制御装置の自己診断処理方式に
関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a self-diagnosis processing method for a digital control device.
第２図は２重系構成をとっている従来のディジタル制御
装置の゛代表的な構成を示すブロック図であって、１は
一方の系、２は他方の系、１ａ、２ａは６系１，２の中
央処理装置（以下、ＣＰＵとい５）、１ｂ、２ｂは６系
１，２のリードオンリーメモリ部（以下、ＲＯＭ部とい
う）、１ｃ、２Ｃは６系１．２のランダムアクセスメモ
リ部（以下、ＲＡＭ部という）である。FIG. 2 is a block diagram showing a typical configuration of a conventional digital control device having a dual system configuration, in which 1 is one system, 2 is the other system, 1a and 2a are 6 systems, 1 , 2 central processing units (hereinafter referred to as CPU 5), 1b and 2b are read-only memory units (hereinafter referred to as ROM units) of 6-systems 1 and 2, and 1c and 2C are random access memory units of 6-system 1.2. (hereinafter referred to as the RAM section).
次に上記ディジタル制御装置による自己診断処理方式に
つｂて説明する。ディジタル制御装置の６系１，２のＣ
ＰＵ１ａ、２ａは、周期的ＶＣソフトウェア及びハード
ウェアの診断を行ない、異常を検出した場合、各々自系
のＲＡ Ｍ部１ｃ 、２ｃに異常情報をセットし、エラ
ー情報出方及び２１ｉ系切換等の処理を行なう。Next, the self-diagnosis processing method by the digital control device will be explained. 6 systems 1 and 2 C of digital control equipment
The PUs 1a and 2a periodically diagnose the VC software and hardware, and when an abnormality is detected, set abnormality information in the RAM sections 1c and 2c of their own system, and determine how the error information is output and the 21i system switching. Process.
従来のディジタル制御装置による自己診断処理方式は以
上のようＩ／ｃ構成されているので、ディジタル制御装
置の一方の系に異常が発生し、その系のＣＰＵが停止し
た場合、該ＣＰＵが自系−のＲＡＭ部にセットした異常
情報を、通信関係のプログラムも停止したり、或いはシ
ステムをリセットすると異常情報がクリアされる等の理
由により、通常のツールで読み出すのが困難であるとい
う問題点があった。Since the conventional self-diagnosis processing method for digital control devices has the I/C configuration as described above, if an abnormality occurs in one system of the digital control device and the CPU of that system stops, that CPU will - The problem is that it is difficult to read out the abnormality information set in the RAM section using normal tools because the abnormality information is cleared when the communication-related program is stopped or the system is reset. there were.
この発明は上記のような問題点を解消するためになされ
たもので、ディジタル制御装置の一方の系に異常が発生
した場合、その異常情報を通常のツールで読み出すこと
ができるディジタル制御装置の自己診断処理方式を得る
ことを目的とする。This invention was made in order to solve the above-mentioned problems, and when an abnormality occurs in one system of the digital control device, the abnormality information can be read out using ordinary tools. The purpose is to obtain a diagnostic processing method.
この発明に係るディジタル制御装置の自己診断処理方式
は、２重化された各基を２ポ一トメモリ部で相互に接続
し、自系の異常情報を自系の２ポートメモリ部にセット
すると共に正常な他方の系の２ポートメモリ部を経て該
他方の系のＣＰＵに伝えて読み出すものである。The self-diagnosis processing method of a digital control device according to the present invention connects each duplicated unit to each other through a two-port memory section, sets abnormality information of the own system in the two-port memory section of the own system, and The data is transmitted to the CPU of the other system via the normal two-port memory section of the other system and read out.
〔作 用〕
この発明におけるディジタル制御装置の自己診断処理方
式は、ディジタル制御装置の一方の系に異常が発生した
場合、その異常情報を２ポ一トメモリ部経由で、他方の
正常な他方の系から通常のツールで読み出すことができ
る。[Operation] In the self-diagnosis processing method of the digital control device according to the present invention, when an abnormality occurs in one system of the digital control device, the abnormality information is transmitted to the other normal system of the digital control device via the two-point memory section. It can be read out using normal tools.
以下、この発明のディジタル制御装置の自己診断処理方
式を実施する２重系構成のディジタル制御装置の一例を
第１図にて説明する。図において、１．２．１ ａ 、
２ａ 、１ ｂ 、２ｂ 、Ｉ Ｃ，２Ｃは前述した従
来技術を示す第１図と同一、又は相当部分である。ｌｄ
、２ｄは各基１，２にそれぞれ設けられていて異常情報
をセットする２ポ一トメモリ部、３はこれら２ポートメ
モリ部１ｄ、２ｄを相互に接続しているバスである。Hereinafter, an example of a digital control device having a dual system configuration that implements the self-diagnosis processing method for a digital control device of the present invention will be explained with reference to FIG. In the figure, 1.2.1 a,
2a, 1b, 2b, I.sub.C, and 2C are the same or corresponding parts as in FIG. 1 showing the prior art described above. ld
, 2d are two-port memory sections provided in each of the bases 1 and 2 to set abnormality information, and 3 is a bus interconnecting these two-port memory sections 1d and 2d.
次Ｋ、この実施例のディジタル制御装置の診断処理方式
について説明する。例えば、２重系の内の一方の系１で
異常が発生した場合、該一方の系１のＣＰＵ１ａは、該
一方の系１の２ポ一トメモリ部１ｄに自系の異常情報を
書き込む。Next, the diagnostic processing method of the digital control device of this embodiment will be explained. For example, when an abnormality occurs in one of the two systems 1, the CPU 1a of the one system 1 writes the abnormality information of the own system into the two-point memory section 1d of the one system 1.
該一方の系１の２ポートメモリ部１ｄは、他方の系２の
ＣＰＵ２ａとバス３で接続されてお夛、一方の系１のＣ
ＰＵ１ａがセットした該一方の系１の異常情報を正常に
動作している他方の系２のＣＰＵ２ａ経由で読み出すこ
とができる。The 2-port memory unit 1d of one system 1 is connected to the CPU 2a of the other system 2 via a bus 3, and the C
The abnormality information of the one system 1 set by the PU 1a can be read out via the CPU 2a of the other system 2 which is operating normally.
他方の系２で異常が発生した場合にも、同様にして一方
の系２のＣＰＵ １ａ経由で読み出すことができる。Even if an abnormality occurs in the other system 2, the data can be read out via the CPU 1a of one system 2 in the same manner.
以上のように１この発明によれば、２重系構成をしてい
るディジタル制御装置の一方の系に異常が発生した場合
、その異常情報を正常な他方の系から通常のツールで読
み出すことができる効果がある。As described above, 1. According to the present invention, when an abnormality occurs in one system of a digital control device having a dual system configuration, the abnormality information can be read out from the other normal system using a normal tool. There is an effect that can be done.
第１図はこの発明のディジタル制御装置の診断処理方式
を実施する２］ｉ系構成のディジタル制御装置を示すブ
ロック図、第２図は従来の２重系構成のディジタル制御
装置を示すブロック図である。
１．２・・・系、１ａ 、 ２ａ・−・ＣＰＵ、ｉ ｂ
、 ２ｂ−−・ＲＯＭ部、ｌ ｃ 、 ２ｃｍＲＡＭ
部、１ｄ、２ｄ・・・２ポ一トメモリ部。
なお、図中、同一符号は同一、又は相当部分を示す。
特許出願人 三菱電機株式会社
ｊＣτ了−・
代理人 弁理士 １）澤 博 昭 １（外２名）−
”FIG. 1 is a block diagram showing a digital control device with an i-system configuration that implements the diagnostic processing method for a digital control device according to the present invention, and FIG. 2 is a block diagram showing a conventional digital control device with a dual-system configuration. be. 1.2...system, 1a, 2a...CPU, i b
, 2b--ROM section, lc, 2cmRAM
part, 1d, 2d...2 point memory part. In addition, in the figures, the same reference numerals indicate the same or equivalent parts. Patent applicant: Mitsubishi Electric Corporation jCτryo Agent: Patent attorney 1) Hiroshi Sawa 1 (and 2 others)
”
Claims (1)
、ランダムアクセスメモリ部を備えて２重系構成となっ
ているディジタル制御装置の診断処理方式において、前
記各系をそれぞれ２ポートメモリ部を介して相互に接続
し、一方の前記系の前記中央処理装置が自己診断を行い
、異常が検出された際に異常情報を該一方の系の前記２
ポートメモリ部にセットして該２ポートメモリ部と正常
な他方の前記系の前記２ポートメモリ部を介して該他方
の系の前記中央処理装置に伝えて読み出すことを特徴と
するディジタル制御装置の診断処理方式。In a diagnostic processing method for a digital control device in which each system is equipped with a central processing unit, a read-only memory section, and a random access memory section and has a dual system configuration, each system is interconnected via a two-port memory section. The central processing unit of one of the systems performs self-diagnosis, and when an abnormality is detected, the abnormality information is transmitted to the central processing unit of the one system.
The digital control device is set in a port memory section and transmitted to the central processing unit of the other system via the 2-port memory section and the normal 2-port memory section of the other system for reading. Diagnostic processing method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61104920A JPS62262102A (en) | 1986-05-09 | 1986-05-09 | Diagnosis processing system for digital control device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61104920A JPS62262102A (en) | 1986-05-09 | 1986-05-09 | Diagnosis processing system for digital control device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62262102A true JPS62262102A (en) | 1987-11-14 |
Family
ID=14393539
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61104920A Pending JPS62262102A (en) | 1986-05-09 | 1986-05-09 | Diagnosis processing system for digital control device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62262102A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04352008A (en) * | 1991-05-29 | 1992-12-07 | Mitsubishi Electric Corp | Failure diagnostic device and diagnostic item setting device |
| WO2000062134A1 (en) * | 1999-04-09 | 2000-10-19 | Mitsubishi Denki Kabushiki Kaisha | Cpu unit of programmable controller and operation proxy control method |
| JP2006092061A (en) * | 2004-09-22 | 2006-04-06 | Meidensha Corp | Duplex system of programmable controller |
-
1986
- 1986-05-09 JP JP61104920A patent/JPS62262102A/en active Pending
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH04352008A (en) * | 1991-05-29 | 1992-12-07 | Mitsubishi Electric Corp | Failure diagnostic device and diagnostic item setting device |
| WO2000062134A1 (en) * | 1999-04-09 | 2000-10-19 | Mitsubishi Denki Kabushiki Kaisha | Cpu unit of programmable controller and operation proxy control method |
| US6760863B1 (en) | 1999-04-09 | 2004-07-06 | Mitsubishi Denki Kabushiki Kaisha | CPU unit and run alternative control method of programmable controller |
| DE19983595B3 (en) * | 1999-04-09 | 2011-12-01 | Mitsubishi Denki K.K. | CPU unit and run alternative control method of a programmable controller |
| JP2006092061A (en) * | 2004-09-22 | 2006-04-06 | Meidensha Corp | Duplex system of programmable controller |
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