JPS62259285A - Address specifying system for memory device - Google Patents

Abstract

PURPOSE:To specify the element array of '1' and the storage elements of '1' in the element array by address signals, to increase the storage capacity and to reduce the delay of addresses by laminating plural storage element arrays to which plural storage elements are arrayed like a grating. CONSTITUTION:Plural storage element arrays 11 arraying plural storage elements 12 like a grating are formed in an address specification system and arranged as layer structure. The 1st and 2nd address control means 13, 16 are arranged with respect to the arrays 11 having the layer structure. The means 13 specifies an array 11 in accordance with the combination of the inputs of the 1st address signal 14 to address signal lines 15 and specifies the X coordinate of one element 12 in the array 11. Similarly, the means 16 specifies an array 11 in accordance with the combination of inputs to signal lines 18 and specifies the Y coordinate of the element 12 in the array 11. Thus, the X and Y coordinates of the element 12 can be specified.

Description

[Detailed description of the invention] [Conventional technology] FIG. 4 shows a storage device according to the prior art.

In the figure, 1 indicates a memory element array. The storage element array 1 includes a plurality of storage elements 2.2. - and are arranged in a grid in the same plane. Each memory element 2
is the coordinate (X, Y) in the memory element array 1
Identified by

Further, 3 indicates an X decoder. The address signal 4 from the X decoder 3 specifies the X coordinate within the storage element array 1. Further, 5 indicates a Y decoder. The address signal 6 from the Y decoder 5 specifies the Y coordinate within the storage element array 1. Therefore, according to the address signal 4.6, 1 located at the coordinates (X, Y)
storage element 2 is specified.

[Problem that the invention seeks to solve]

However, since the storage device according to the prior art was configured as described above, there were the following problems.

That is, in order to increase the storage capacity, it was necessary to increase the number of storage elements 2 by making the storage elements 2 smaller or by increasing the size of the entire device. However, in this case, the number of memory elements 2 connected to one address signal line increases, and as a result, delays in the address signals 4 and 6 become a problem, or However, there were problems such as the need for a large driver.

Therefore, the present invention has been made in view of the above circumstances.

[Means for solving problems]

The present invention configures a memory device by arranging a plurality of memory element arrays in a layered manner, each of which is a plurality of memory element arrays each having a plurality of memory elements arranged in a lattice pattern. One storage element within the storage element array is specified.

[Effect]

The address signal allows designation of the above-mentioned one storage element array and designation of one storage element within the storage element array.

〔Example〕

Embodiments of the present invention will be described below with reference to FIGS. 1 to 3. Note that FIG. 1 shows a first embodiment.

Reference numeral 11 denotes a memory element array, and in this embodiment, four memory element arrays 11 are arranged in a four-layer structure, and one memory element is arranged according to coordinates (X, Y). 12 is specified.

13 indicates first address control means. The first address control means 13 includes a decoder circuit for decoding the first address signal 14, a sense amplifier, and an output buffer. Here, the first address signal 14 is
Four address signal lines 15.15. It is determined by the combination of signals input from -. However, the signal "0. or 1" is input from the address line 15 of each address 43. Therefore, the first address signal 1
4 is rO, 0, 0, OJ, ro, o.

0, IJ, ---, and there are 16 combinations.

Therefore, the four storage element arrays 11 . 11. - It is possible to select any one memory element array 11 among the memory element arrays 11 and to select the X coordinate within the memory element array 11.

Note that the sense amplifier is an amplifier used for reading information.

Further, 16 indicates second address control means. The second address control means 16 includes a decoder circuit for decoding the second address signal 17, a sense amplifier, and an output sofa. Here, the second address signal 17
is determined by a combination of signals input from two address signal lines 18 and 18. However, a signal "0. or l" is input from each signal line 18. Therefore, the second address signal 17 is "0°0", r
Four combinations are possible: O, IJ, rl, OJ, ri, and IJ. Therefore, the second address signal 17
The Y coordinate within one memory element play 11 is specified by.

Thus, the above 1. The second address signal 14°17 allows selection of one storage element array II and selection of coordinates (X, Y) within the storage element array 11,
As a result, l in the storage element array 11 of the above-mentioned 1
The storage elements 12 are designated.

Next, the effect will be explained.

First, assume that the first address signal 14 is input.

Then, according to the first address signal 14, the l storage element array 11 is specified, and the X coordinate within the storage element array 11 is specified.

On the other hand, the Y coordinate within the first storage element array 11 is specified by the second address signal 17. As a result, the coordinates (X, Y) in the memory element array 11 mentioned above are
This means that one memory element 12 located at is specified.

Further, FIGS. 2 and 3 show a second embodiment of the present invention, with FIG. 2 showing a plan view and FIG. 3 showing a perspective view, respectively.

Thus, the storage device 21 in this embodiment is layered. Thus, in the following embodiments, each memory element 22 . 22. - are arranged in a lattice pattern, and each memory element 22 has a memory element 2 as shown in FIG.
Information successive output means 23 for reading information from 2 is provided. Each information successive means 23 is designated by coordinates (1,1), (1,2), (2,1), (2,2) as shown in FIG. Each of the above-mentioned information successive means 23 is the N-MO
It is composed of a pair of S-type transistors 24 and 25.

Here, the transistors 24 and 25 are composed of a channel region 26, a pair of source S and drain D facing each other across the channel region 26, and a pair of gates G and a back gate. The back gate t is common to all transistors 24, 25 in each layer. Here, when the gate G is at ground potential and the back gate is at positive potential, these transistors 24 and 25 have sources S,
The drain D is non-conductive, while the source S and drain D are conductive when the gate G is at a positive potential and the back gate is at ground potential.

The source S of one of the transistors 24 constituting the information successive means 23 is connected to each of the storage elements 22, and the gate G is connected to either the χ coordinate selection signal line XI or X2, Furthermore, the back gate t is connected to the layer selection signal line Z.
1. Z2. Z3 or Z4, and the drain D is connected to the source S of the other transistor 25. The gate G of the transistor 25 is connected to either Y coordinate selection signal line Yl or Y2, and the drain D is connected to the information output line 26.

Next, the effect will be explained.

First, all memory elements 22.22. -... is not selected. In this case, all layer selection signal lines Zl, Z2 .
Z3. A positive voltage is applied to Z4, a zero voltage is applied to the X coordinate selection signal lines XI and X2, and a zero potential is applied to the Y coordinate selection signal lines Yl and Y2. In this case, all the transistors 24 and 25 of the information outputting means 23 become non-conductive, so that the information in the storage element 22 is not outputted from the information output line 26.

Next, a case will be described in which the memory element 22 at the coordinates (1, l) of the A layer is selected.

In this case, zero voltage is applied to the layer selection signal line Z1, and further,
A positive voltage is applied to the X coordinate selection signal line X1, and a positive voltage is applied to the Y coordinate selection signal line Y1. In this case, since both transistors 24 and 25 are conductive, the storage element 22
The information within is output from the information output line 26 via both transistors 24 and 25.

Note that the selection of memory elements 22 at other coordinates is the same as described above, so the explanation will be omitted.

In addition, in the embodiment, four layers of 4×4 memory element arrays are stacked, but it is sufficient to have a plurality of these values, and the structure of the memory element may be dynamic RAM or static RAM. , ROM, EPROM,
Any device such as EEFROM that can be selected by conventional X and Y addresses can be used.

〔Effect of the invention〕

As explained above, according to the present invention, a memory device is configured by arranging a plurality of memory element arrays in a layered manner, which are formed by arranging a plurality of memory elements in a lattice shape. Since the element array is specified and one memory element within the memory element array is specified, the following effects are achieved.

That is, since the multilayer structure is adopted, the storage capacity can be increased and the delay of the address signal can be reduced.

[Brief explanation of drawings]

Figures 1 to 3 relate to the present invention; Figure 1 is a configuration diagram showing the first embodiment, Figure 2 is a plan view of the second embodiment, Figure 3 is a perspective view, and Figure 4 is a diagram showing the configuration of the first embodiment. FIG. 2 is a configuration diagram of a conventional technique. 11...Storage element array, 12.22...Storage element. Agent: Masuo Oiwa (and 2 others) Figure 4: Procedural amendment G card case display Japanese Patent Application No. 61-103602 2 Addressing system for the invention name storage device 3 Relationship with the amended person case Patent applicant representative Moriya Shiki 4, agent 5, date of amendment order July 29, 1985 6, column of drawing subject to amendment. 7. Details of amendments (1) The drawings and Figure 2 will be amended as shown in the attached sheet. (Rejuvenation 1; λ Nirishi) Procedural amendment (spontaneous 20 Name of invention Stacked semiconductor memory device 3, Person making the amendment Representative Moriya Shiki 4, Agent 1.1.-1-11..S. Columns for the title of the invention to be amended, claims, and detailed description of the invention. 6. Contents of the amendment (1. The title of the invention, "addressing system for storage device," is replaced with "stacked semiconductor storage device." (2. Amend the claims as shown in the attached sheet. (3) In the 13th line of page 1 of the specification, the phrase "This invention relates to an improvement in the addressing method of a storage device" should be replaced with " (4) On page 3, line 4 of the same book, the phrase ``memory device address assignment method'' has been changed to ``improvement of the arrangement of storage device elements and the addressing method.'' (5) In the 11th and 12th lines of page 3 of the same book, the phrase ``designation of...'' has been changed to ``designation of It is possible to obtain a device with a large storage capacity and a large storage capacity.
and correct it. 2. Claims: A storage device is configured by arranging a plurality of storage element arrays in a layered manner, each of which is formed by arranging a plurality of storage elements in a lattice pattern.
33′ ta address

Claims (1)

[Claims] A storage device is configured by arranging a plurality of storage element arrays in a layered manner, each of which is formed by arranging a plurality of storage elements in a grid,
1. An addressing method for a storage device, characterized in that the address signal specifies one storage element array and one storage element within the storage element array.