JPH08148572A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To achieve a semiconductor integrated circuit for propagating the signal of a logic circuit into a memory without going around the memory for a wiring for signal and without limiting a wiring layer used for the memory. CONSTITUTION: Both edge sides of each bit line BL are extended and connected to the signal input/output edges of logic circuits 2-1 and 2-2 as wires 11-1 and 11-2 for signal and NMOS transistors N1-N4 are provided in parallel with the wire 11-1 for signal at one edge side of each bit line BL and between the output of a write buffer WB and the input of a sense amplifier SA. Then, a column selector CSL where these gates are connected to the control line of a column decoder CDC is provided and at the same time a memory control circuit 12 is provided to output a prohibition signal S12 for prohibiting the drive (activation) of all word lines WL of a memory array MA to a row decoder RDC when a transfer enable signal LG1E or LG2E is received.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit in which a logic circuit and a memory are mounted together.

[0002]

2. Description of the Related Art In a semiconductor integrated circuit of this type, when a signal of a logic circuit is transmitted to a logic circuit arranged on the opposite side of a memory, a signal transfer wiring method for this logic circuit is generally used. In addition, the following two methods are adopted.

The first method is, as shown in FIG. 9, two logic circuits 2-1 and 2-2 arranged with a memory region 1 interposed therebetween.
This is a method of arranging the signal line 3 connecting between 2 and 2 while bypassing the memory area 1.

In the second method, as shown in FIG. 10, a wiring layer 4 other than the wiring layer used for the memory, for example, a third metal wiring layer is used to perform wiring on the memory region 1 and to perform both logics. This is a method of connecting between the circuits 2-1 and 2-2.

[0005]

However, in the above-mentioned first method, for example, in a semiconductor integrated circuit for performing image processing, it becomes necessary to mount a large-scale memory, and the signal line 3 is largely detoured. This leads to an increase in area. Further, the second method has a disadvantage that the wiring layer of the memory needs to be limited and the memory operation becomes slow.

The case of a general semiconductor integrated circuit has been described above. Further, with respect to this problem, JP-A 1-2
The sequential video processor system described in Japanese Patent No. 58184 will be described as an example. FIG. 11 is a block diagram showing this sequential video processor system, which is mainly configured to process scanning line image data. In such a configuration, the image data DI of the scanning line is sequentially input to the data input register (DIR) and transferred to the RAM 6 during the blanking period of the scanning line (serial-parallel conversion). When the transfer is completed, the next scan line data is input to the data input register 5, and the data transferred at the same time undergoes a predetermined arithmetic processing in the RAM 6, the work register 7, and the 1-bit full adder / subtractor 8. Be seen. After the calculation is completed, the data held in the RAM 9 is transferred to the data output register (DOR) 10 and serially output as the output data DO from the data output register 10.

This sequential video processor system has N
While the Nth scanning line is being input to the data input register 5, the N-1th scanning line is processed to obtain N
The data output register 10 outputs the data after the operation of the -2nd scanning line in a three-stage pipeline configuration.

However, in this system configuration, even if the data calculated by the 1-bit full adder / subtractor 8 is used to control the data input register 5 and the data output register 10, a large amount of 1024 bits is required. Bypass the control signal wiring of RAM6,9, or
There is no choice but to wire on the wiring layers 6 and 9 different from the memory data wiring layer. Therefore, bypassing the data lines of 1024 bits increases the area considerably, and using another wiring layer limits the wiring layer of the memory cell.

The present invention has been made in view of the above circumstances, and an object thereof is to eliminate the need for circumventing the memory with respect to the signal wiring and to provide the logic in the memory without restricting the wiring layer used for the memory. It is to provide a semiconductor integrated circuit capable of propagating a signal of the circuit.

[0010]

In order to achieve the above object, the present invention provides a semiconductor integrated circuit in which a logic circuit and a memory are mixedly mounted, wherein the logic circuit is connected to a memory wiring and a signal transfer command of the logic circuit is provided. It has a circuit for deactivating the memory when receiving the signal, and when the memory is inactive, the logic circuit signal is propagated through the memory wiring.

Further, in the semiconductor integrated circuit of the present invention, the memory wiring is wired to the outside of the memory area, and the external wiring is connected to the logic circuit. Further, the semiconductor integrated circuit of the present invention has a selector which operatively connects the memory wiring and the signal output line of the logic circuit in accordance with the signal transfer instruction. Further, in the semiconductor integrated circuit of the present invention, the signal transfer between the drive circuit having at least two input ends for driving the memory wiring, one input end of the drive circuit and the signal output line of the logic circuit is performed. A selector which is operatively connected according to an instruction is provided, and a signal for memory internal is propagated to the memory wiring when the memory is active, and a signal of the logic circuit is propagated when the memory is inactive.

Also, in the semiconductor integrated circuit of the present invention, the memory wiring is a bit line, and has first and second logic circuits connected to both ends of the bit line, respectively. The signal output from is input to the input buffer of the memory, the signal is propagated through the bit line and input to the second logic circuit.

[0013]

According to the semiconductor integrated circuit of the present invention, the memory is inactivated when the signal transfer command of the logic circuit is issued. Then, during a time period when the memory is not activated, signal transfer of the logic circuit is performed using the memory wiring, for example, the bit line, the word line, or the decode line. Further, for example, when the write data to the memory cell is input to the drive circuit of the memory wiring and the signal transfer instruction is not issued, the memory is in the activated state,
Data writing is performed. When the signal transfer command is issued, the memory is inactivated, and one input end of the drive circuit and the signal output line of the logic circuit are connected by the selector, and the signal of the logic circuit is input to the drive circuit.
A signal is transferred through the memory wiring.

[0014]

[Embodiment 1] FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor integrated circuit according to the present invention. The same components as those in FIGS. 9 and 10 showing a conventional example are represented by the same reference numerals. . That is, 1 is a memory area, 2-1 (LG1), 2
2 (LG2) is a logic circuit, 11-1 and 11-2 are signal wirings, and 12 is a memory control circuit.

The memory area 1 includes a memory array MA, a row decoder RDC, a column decoder CDC, a column selector CSL, a sense amplifier SA and a write buffer WB.
It consists of. The memory array MA includes a plurality of word lines WL driven by the row decoder RDC, a plurality of bit lines BL arranged in a direction orthogonal to the wiring direction of the word lines WL, the bit lines BL and the word lines WL. And memory cells MC connected in a matrix and arranged in a matrix. In FIG. 1, the number of word lines WL, bit lines BL and memory cells MC is omitted for simplification of the drawing. Then, both ends of each bit line BL are extended, and the signal wirings 11-1 and
11-2 are connected to the signal input / output terminals of the logic circuit 2-1 and the logic circuit 2-2, respectively. The column selector CSL is an n-channel MOS (NMOS) arranged in parallel with the signal line 11 between one end of each bit line BL, the output node of the write buffer WB, and the data input node of the sense amplifier SA. The gates of the NMOS transistors N1 to N4 are respectively connected to the control lines of the column decoder CDC.

When the memory control circuit 12 receives a transfer enable signal LG1E or LG2E which is an inter-logic signal transfer instruction from a control system (not shown), the memory array M.
The inhibition signal S12 for inhibiting the driving (activation) of all the word lines WL of A, that is, for inactivating the memory is output to the row decoder RDC. Normally, the transfer enable signal LG1E or LG2E is not issued when the enable signals CE and WE, which are control signals peculiar to the memory, are active. Row decoder RDC
Does not drive the word line WL when receiving the inhibition signal S12. For example, the word line WL is not driven even when the enable signals CE and WE, which are control signals peculiar to the normal memory, are active.

Next, the operation of the above configuration will be described with reference to the timing chart of FIG. In FIG. 2, of the data written in the bit line BL portion, WDT is the data written in the memory cell MC, SDT
DT represents signal data transferred to the logic circuits 2-1 to 2-2 or the logic circuits 2-2 to 2-1 respectively.

First, in a state where the transfer enable signal LG1E or LG2E, which is an inter-logic signal transfer instruction, is not issued (maintained at the low level), the enable signal CE is switched from the low level to the high level, so that the memory The region 1 is activated, and the word line WL selected by the address signal is activated by the row decoder RDC. At this time, when the enable signal WE is switched from the low level to the high level, the write buffer W is written to the bit line BL selected by the column selector CSL.
Write data W input to B as input data DI
DT is written in a predetermined memory cell MC. Further, in this case, since the transfer enable signal LG1E or LG2E which is the inter-logic signal transfer instruction is not issued, the signal transfer of the logic circuits LG1 and LG2 is not performed.

Next, when the transfer enable signal LG1E or LG2E is issued by a control system (not shown), the memory control circuit 12 causes all the word lines W of the memory array MA.
An inhibition signal S12 for inhibiting the driving (activation) of L, that is, for inactivating the memory is generated and output to the row decoder RDC. As a result, the word line WL is not driven and the memory array MA is held in the inactive state. In this case, the enable signals CE and WE, which are control signals peculiar to the memory, are normally switched to the low level as shown in FIG. Then, a signal is transferred from the logic circuit 2-1 or the logic circuit 2-2, and this signal is transferred to the logic circuit 2-2 or the logic circuit 2-1 via the bit line BL. At this time, since the word line WL is in the inactive state, the data in the memory cell MC is not destroyed.

As described above, according to the first embodiment, both ends of each bit line BL are extended and the signal wiring 1 is provided.
Reference numerals 1-1 and 11-2 are respectively connected to signal input / output terminals of the logic circuit 2-1 and the logic circuit 2-2, and one end side of each bit line BL, an output node of the write buffer WB, and a data input of the sense amplifier SA. A column selector CSL is provided between the nodes, which is composed of NMOS transistors N1 to N4 arranged in parallel with the signal wiring 11-1 and whose gates are connected to the control lines of the column decoder CDC, respectively. Transfer enable signal LG1E or LG2 which is a signal transfer instruction between logics
When receiving the E, the memory control circuit 12 that outputs the inhibition signal S12 that inhibits the driving (activation) of all the word lines WL of the memory array MA to the row decoder RDC is provided. Therefore, it is necessary to bypass the memory for the signal wiring. It is possible to propagate the signal of the logic circuit in the memory without any limitation and without limiting the wiring layer used for the memory.
In addition, data with a bit line width equal to the number of bit lines is set to 1
It is possible to transfer every time.

In this embodiment, as the signal wiring, the case where the bit line BL wired to the outside of the memory is used as it is has been described, but other signal lines are connected to the bit line BL. Various other modes are possible.
Further, in the present embodiment, the case where the bit line is used as the signal transfer wiring has been described as an example, but the present invention is not limited to this, and the present invention can be applied even when a word line or a decode line is used. It goes without saying that it can be applied. However, when the word line is used, the memory cell MC needs to be a non-destructive memory cell.

[0022]

Second Embodiment FIG. 3 is a circuit diagram showing a second embodiment of the semiconductor integrated circuit according to the present invention. The difference of the second embodiment from the above-described first embodiment is that a signal line 11-1 is connected to a signal input / output line of the logic circuit 2-1 and one end side of each bit line BL by a transfer enable signal LG1E. A selector 13-1 composed of NMOS transistors operatively connected according to the level of
2, the signal input / output line of the logic circuit 2-2 and each bit line B
This is because there is provided a selector 13-2 composed of an NMOS transistor that is operatively connected to the other end of L according to the level of the transfer enable signal LG2E.

FIG. 4 is a timing chart showing the operation of the circuit of FIG. In this timing chart, the transfer enable signals LG1E and LG2E are the selectors 13-1,
13-2, the signal control is performed in the same manner as in the first embodiment, so the timing is the same as in FIG.

According to the second embodiment, in addition to the effects of the first embodiment described above, the load on the bit line is increased by the selector 1.
Only the parasitic capacitances of the transistors forming the transistors 3-1 and 13-2 are provided, the load capacitance can be reduced, and the reduction in the operating speed of the memory can be prevented. Also, the selectors 13-1, 13-2
The increase of the area due to the addition of is smaller than that of bypassing the signal wiring of the logic circuit.
Since it is sufficient to add only the desired number of -1 and 2-1 to be connected, it can be almost ignored.

[0025]

Third Embodiment FIG. 5 is a circuit diagram showing a third embodiment of the semiconductor integrated circuit according to the present invention. The third embodiment differs from the second embodiment described above in that one signal input / output terminal of the logic circuit 2-1 and one input terminal of the two input terminals of the write buffer WB are Transfer enable signal LG
There is provided a selector 14 composed of an NMOS which is operatively connected according to the level of 1E.

This circuit is applicable, for example, when the transfer width of the bit width of the input / output of the memory is sufficient, and the write buffer WB also serves as a buffer for transmitting the signal of the logic circuit 2-1. This has the advantage that the circuit scale can be reduced. However, in the case of this circuit, signals can be transferred only from the logic circuit 2-1 to the logic circuit 2-2. Further, the write buffer WB and the column selector CSL are activated even when the memory is inactivated.
For example, the enable signal CE or WE is held at the high level, and the inhibition signal S12 by the memory control circuit 12 is held.
By this, control such as deactivating the memory is performed. Further, for example, as shown in the timing chart of FIG. 6, the enable signal WE and the transfer enable signal LG1
Alternatively, the logical product of E and LG2E may be obtained to activate the write buffer WB and the column selector CSL.

[0027]

Fourth Embodiment FIG. 7 is a circuit diagram showing a fourth embodiment of the semiconductor integrated circuit according to the present invention. In the fourth embodiment,
It is configured to input the signal of the logic circuit 2-1 from the input buffer DIN of the memory.

In this circuit, the input buffer DIN, the write buffer WB and the column selector CSL are activated even when the memory is inactivated. WDB indicates a write data bus. For example, the enable signal CE or WE is held at a high level, and control such as inactivating the memory is performed by the inhibition signal S12 by the memory control circuit 12. Further, for example, as shown in the timing chart of FIG. 7, the logical product of the enable signal WE and the transfer enable signals LG1E and LG2E may be obtained to activate the input buffer DIN, the write buffer WB and the column selector CSL. .

[0029]

As described above, according to the semiconductor integrated circuit of the present invention, it is not necessary to bypass the memory for the signal wiring, and the wiring layer used for the memory is not restricted in the memory. The signal of the logic circuit can be propagated. Further, by applying the present invention to the bit lines in the memory, it is possible to transfer data having a bit width equivalent to the number of bit lines at one time.

[Brief description of drawings]

FIG. 1 is a circuit diagram showing a first embodiment of a semiconductor integrated circuit according to the present invention.

FIG. 2 is a timing chart for explaining the operation of the circuit of FIG.

FIG. 3 is a circuit diagram showing a second embodiment of the semiconductor integrated circuit according to the present invention.

FIG. 4 is a timing chart showing an operation example of the circuit of FIG.

FIG. 5 is a circuit diagram showing a third embodiment of the semiconductor integrated circuit according to the present invention.

6 is a timing chart showing an operation example of the circuit of FIG.

FIG. 7 is a circuit diagram showing a fourth embodiment of the semiconductor integrated circuit according to the present invention.

8 is a timing chart showing an operation example of the circuit of FIG.

FIG. 9 is a diagram for explaining a method of wiring a signal line that connects two logic circuits arranged with a memory region interposed therebetween, bypassing the memory region.

FIG. 10 is a diagram for explaining a method of connecting between two logic circuits by wiring on the memory region by using a wiring layer other than the wiring layer used in the memory.

FIG. 11 is a configuration diagram showing a sequential video processor system for explaining a conventional problem.

[Explanation of symbols]

 1 ... Memory area MA ... Memory array RDC ... Row decoder CDC ... Column decoder CSL ... Column selector SA ... Sense amplifier WB ... Write buffer DIN ... Input buffer 2-1 and 2-2 ... Logic circuit 11 ... Signal wiring 12 ... Memory Control circuit 13-1, 13-2, 14 ... Selector

Claims (5)

[Claims] 1. A semiconductor integrated circuit in which a logic circuit and a memory are mounted together, wherein the logic circuit is connected to a wiring for the memory, and the circuit has a circuit for deactivating the memory when receiving a signal transfer command of the logic circuit. A semiconductor integrated circuit in which a signal for a logic circuit is propagated through a wiring for a memory when the circuit is inactive. 2. The semiconductor integrated circuit according to claim 1, wherein the memory wiring is wired to the outside of the memory area, and the external wiring is connected to the logic circuit. 3. The semiconductor integrated circuit according to claim 1, further comprising a selector that operatively connects the memory wiring and the signal output line of the logic circuit according to the signal transfer command. 4. A drive circuit having at least two input ends for driving the memory wiring, and one input end of the drive circuit and a signal output line of the logic circuit are operated according to the signal transfer command. 3. The semiconductor integrated circuit according to claim 1, further comprising a selector that is electrically connected to the memory wiring, wherein a signal for internal memory is propagated to the memory wiring when the memory is active, and a signal of a logic circuit is propagated when the memory is inactive. circuit. 5. The memory wiring is a bit line and has first and second logic circuits respectively connected to both ends of the bit line, and a signal output from the first logic circuit is stored in the memory. 5. The semiconductor integrated circuit according to claim 1, wherein the signal is input to an input buffer, the signal is propagated through a bit line and input to a second logic circuit.