JPS6225816A - Input circuit for protection relay - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an input circuit for a digital protection relay.
In particular, it relates to a sample-and-hold type input circuit when converting a large number of analog inputs into digital.

[Background of the invention]

The conventional digital protection relay is published in Japanese Patent Application Laid-Open No. 57-3652.
As shown in Publication No. 8, after inputting the system voltage and current through an auxiliary transformer and removing harmonic components using a filter, all voltage and current information is sampled and held at the same sampling time. The sampled and held signals were converted into digital quantities by - number of A/D converters by switching sequentially. However, this method has the disadvantage that when the number of input signals increases, sample and hold circuits corresponding to the number of input signals are required, which increases the size of the input circuit and increases the cost.

[Purpose of the invention]

SUMMARY OF THE INVENTION It is an object of the present invention to provide an input circuit for a digital protection relay that samples and holds input signals using two or less sample and hold circuits and A/D converts them despite a large number of input signals.

[Summary of the invention]

The present invention selects and samples only the signals that require simultaneous sampling from the multiple inputs of a digital protection relay, and then samples the signals that form a set of these signals.

Switch sequentially and sample at the same time.

The sample-and-hold circuit can be configured with only the number of signals that require simultaneous sampling.

[Embodiments of the invention]

In Fig. 1, IA~IN are voltage filters, 2A~
2N is a current filter, 3 and 4 are multiplexers, 5
and 6 is a sample hold, 7 is a multiplexer, 8 is an analog/digital conversion circuit (A/D), 9 is a buffer memory, and 10 is a microcomputer that performs fault detection calculations.

FIG. 2 shows the timing of the present invention.

(a) is a sample hold command given to the sample hold circuits 5 and 6, (b) to (a) are A/D conversion commands (A/D conversion is performed during labeling), and (f) is a , shows an example in which A/D converted input signals are stored in the buffer memory 9 of FIG.

(g) shows the sampling time and the processing outline of the 10 microcomputers shown in FIG.

That is, in the present invention, in FIG. 1, multiplexers 3 and 4 sample and hold in response to a sample and hold command that requires simultaneous sampling.

Next, the multiplexer shown in Fig. 1 is used to sequentially switch the A/D
Convert. This timing is shown in (b) and (c) in Figure 2.
In this embodiment, vl and 11 are sampled at the same time, and A/D conversion is performed in the order of 1 and Io.

Next, the select signals of multiplexers 3 and 4 in FIG. 1 are switched, and the sample hold command (n2
time) to simultaneously sample the input signal that requires other simultaneous samples. In the example, as shown in FIG. 2(f), v2 and 2 are simultaneously sampled at time n2, and v
2 and I2 in order, and buffer memory 9 in FIG.
An example is shown in which the file is stored in .

That is, within the sampling period T, input signals that require simultaneous sampling are sequentially switched in combination. For power protection relays, for example, it is easy to guess that the same processing as conventional methods can be performed by simultaneously sampling the A-phase voltage and A-phase current, B-phase voltage and current, and C-phase voltage and current. can.

Next, an outline of the processing contents of the first @ microcomputer 10 is shown in FIG. In step a, data is acquired at time N, for example, in part (f) of FIG. 2, and in step b
Now, using this data, an accident detection calculation for the power system is performed, and in step C, it is compared with a predetermined value, and if it is determined that an accident has occurred.

Proceeding to step d, a shutdown command for the new year is issued. Exactly the same process is repeated at the next sample time.

The embodiment shown in FIG. 2 describes an example in which the voltage is v1 to v5 and the current is 11 to v5. And V, and 1. V2 and I2. V3 and I3. ■4, I41v5, and Engineering describe examples where simultaneous sampling is required due to the characteristics of the protection relay.

〔Effect of the invention〕

According to the present invention, even if the number of inputs is large, it can be configured with only two sample and hold circuits, so a simple input circuit can be configured, and high reliability and cost reduction can be achieved.

[Brief explanation of drawings]

FIG. 1 is a block configuration diagram of a digital protection relay input circuit of the present invention, FIG. 2 is a timing example diagram of the present invention, and FIG. 3 is an example diagram of an accident detection calculation of a processing device (microcomputer). 5.6...Sample hold.

Claims (1)

[Claims] 1. For digital protection relays, which regularly import system information sampled at regular time intervals, perform protection relay calculations, and compare the calculation results with preset values to determine accidents, An input circuit for a protective relay, characterized in that only signals that require simultaneous sampling are selected, and these signal groups are sequentially switched and simultaneously sampled, and sequentially converted into digital signals.