JPS62257218A - Phase locked loop - Google Patents

Abstract

PURPOSE:To reduce a pull-in time by providing a frequency dividing ratio change means changing the frequency division ratio of a frequency divider in response to the comparison output from a phase comparator. CONSTITUTION:When the phase locked loop is in the asynchronizing state and in the process of a pull-in state, a frequency division ratio controller 5 changes minutely the frequency dividing ratio of the frequency divider 4 from a normal value. A phase comaprator 1 detects the frequency error of two input signals and controls a voltage controlled oscillator 3 in a direction decreasing the frequency difference. Similarly, the operation above is repeated sequentially and the output signal of the voltage controlled oscillator 3 causes the sweeping state with respect to the input reference signal. When the frequency is approached much and a phase error detector 6 detecting the phase error of the phase comaprator 1 detects that the frequency is within the range of the specified phase error, the frequency division ratio controller 5 is controlled so as to restore the frequency division ratio of the frequency divider 4.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a phase locked circuit that outputs a stable frequency signal that is phase synchronized with a reference input signal.

(Prior Art) As a conventional phase synchronization circuit, the one shown in FIG. 2 is known. In the conventional example shown in FIG. 2, when the phase locked circuit is a narrow band loop, in other words, the sensitivity of the voltage vs. frequency characteristic of the voltage controlled oscillator 3 that controls the oscillation frequency according to the input control voltage is low, or the voltage A frequency divider 40 for dividing the output signal frequency of the controlled oscillator 3 and feeding it back to the phase comparator 51. When the frequency division ratio is large, the voltage controlled oscillator 3
Output fOH? Since it takes a considerable amount of time to synchronize, the sweep oscillator 8 outputs one sweep control voltage based on the signal output of the phase error detector 6, as shown in Fig. 8J2.
and an adder 7 are provided, and the output of the sweep generator 8 is added to the comparative output of the phase comparator 1 obtained via the loop filter 2, and the result is sent to the voltage fill generator 3. I will briefly discuss the time required to achieve this, that is, the synchronization pull-in time.

(Problems to be Solved by the Invention) The conventional example shown in FIG. 2 requires an adder 7 and a sweep starting device 8, resulting in an increase in cost.

1. Even if the phase error between the reference input frequency fin and the output frequency fotfr is reduced by starting synchronous control, depending on the direction of sweep and the sweep control voltage of the beating sweep generator 8, the sweep period will increase by an additional 1 sweep period. The drawback was that it took several minutes.

The present invention has been made in view of the above problems, and it is an object of the present invention to provide a phase-locked circuit that can shorten synchronization pull-in time with a simple circuit configuration without increasing the cost of the device.

(Means for Solving the Problems) Means provided by the present invention in order to solve the aforementioned problems and achieve the above objects inputs a reference frequency signal and a frequency-divided output signal of a frequency divider, The voltage controlled oscillator is equipped with a phase comparator that detects the phase difference between the two, and a voltage controlled oscillator that controls the oscillation frequency according to the output voltage of the phase comparator obtained through a loop filter for removing noise. The phase synchronization circuit feeds back an output signal to the frequency divider and extracts a phase synchronization signal from the voltage controlled oscillator, and the phase synchronization circuit is configured to feed back an output signal to the frequency divider and take out a phase synchronization signal from the voltage controlled oscillator, and according to the comparison output from the phase comparator, The present invention is characterized in that a frequency division ratio changing means for changing the frequency division ratio is provided.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention.

First, the configuration will be described. Reference numeral 1 denotes a phase comparator, which compares the input signal of the reference frequency fin and the divided output of the frequency divider 4, and detects the phase difference between the two. 2 is a loop filter that removes unnecessary harmonic components and noise, and the comparison output from the phase comparator 1 is given to the voltage controlled oscillator 3 via the loop filter 2. The voltage controlled oscillator 3 controls the oscillation frequency according to the comparison output. The output signal of this voltage controlled oscillator 30 frequency foffT is fed back to the frequency divider 4. The frequency division ratio of the frequency division 54 is set to a constant value n, and is changed to a value smaller than n in accordance with the control output of the frequency division ratio changing means, thereby improving the phase synchronization pull-in characteristic.

Specifically, the frequency division ratio changing means includes a phase error detector 6 that detects a phase error based on the comparison output of the phase comparator 1, and a frequency division ratio that changes the frequency division ratio according to the detection output of the phase error detector 6. It consists of a branch ratio controller that sends a command to change the ratio. In addition, the phase error detector 6 is set with a threshold value for determining whether the value of the phase error is within a specified range, and when it is determined that the phase error is within the specified range, the frequency division The ratio controller 5 is instructed to send a reset signal to reset the frequency division ratio n to the normal frequency division ratio.

I will briefly explain the operation. The output of the voltage controlled oscillator 3 is frequency-divided by a frequency divider 4, and this frequency-divided signal is used as an input reference signal f. A phase comparator IK is also provided. The phase comparator 61 detects the phase difference between the two input signals and generates an error of 1 pressure according to the phase difference. After unnecessary harmonic components and noise are removed from this error bottom pressure by a loop filter 2, it is supplied to a voltage controlled oscillator 3 to perform frequency control and reach a phase synchronized state.

When the phase-locked circuit is in an asynchronous state and is in the process of locking in, the division ratio controller 5 changes the division ratio of frequency division R<4 by a slight amount from the normal value. The phase comparator 1 detects a frequency error between two input signals, and controls the voltage controlled oscillator 3 in a direction to reduce the frequency difference. This is repeated sequentially in the same way, and the output signal of the voltage controlled oscillator 3 produces a sweep state with respect to the input reference signal. When the frequencies become quite close and the phase error detector 6 detects the phase error of the phase comparator l detects that it is within the specified phase error range, the frequency is divided to return the division ratio of the frequency divider 4 to the original value. Controls the ratio controller 5. That is, in the synchronous pull-in process, the frequency division ratio is slightly controlled to give a frequency error and accelerate the frequency control. When the value of the phase error falls within a predetermined range, the frequency division ratio of the frequency divider 54 is controlled to a normal value. The actual phase error detector 6 simply detects the point at which frequency error changes to phase error control in the phase comparator 1 that has a frequency discrimination function.
(Effects of the Invention) As explained above, according to the present invention, there is provided a phase comparator that inputs a reference frequency signal and a divided output signal of a frequency divider and detects the phase difference between the two, and a noise removal loop. and a voltage controlled oscillator that controls the oscillation frequency in accordance with the output voltage of the phase comparator obtained via a filter, the output signal of the voltage controlled oscillator is fed back to the frequency divider, and the phase is output from the voltage controlled oscillator. In the phase-locked circuit configured to take out the synchronization signal, by providing a frequency division ratio changing means for changing the frequency division ratio of the frequency divider according to the comparison output from the phase comparator,
With a simple circuit configuration, the synchronization pull-in time of the phase synchronized circuit can be shortened without increasing costs, and phase synchronization can be reliably achieved.

[Brief explanation of drawings]

FIG. 1 is a block diagram 1 showing an embodiment of the present invention,'@
FIG. 2 is a block diagram showing a conventional example. l... Phase comparator, 2... Loop filter, 3...
・Voltage controlled oscillator, 4... Frequency divider, 5... Frequency division ratio controller, 6... Phase difference detector, 7... Addition device, 8
...Sweep firing device.

Claims (1)

[Claims] A phase comparator that receives a reference frequency signal and a frequency-divided output signal of a frequency divider and detects the phase difference between these two signals, and the above-mentioned phase comparison obtained through a loop filter for noise removal. a voltage controlled oscillator that controls the oscillation frequency according to the output voltage of the oscillator, the output signal of the voltage controlled oscillator is fed back to the frequency divider, and a phase synchronized signal is extracted from the voltage controlled oscillator. A phase synchronized circuit, characterized in that the circuit further comprises a frequency division ratio changing means for changing the frequency division ratio of the frequency divider according to a comparison output from the phase comparator.