JPS62256155A - Bus competition system - Google Patents

Abstract

PURPOSE:To mount many circuit blocks on one substrate with a good efficiency in area by adjusting a bus request from the plural circuit blocks disposed on the same substrate by an internal common bus competition circuit part and performing the competition of an external busy by an external common bus competition circuit. CONSTITUTION:Only one of the circuit blocks 141-14n in the substrate 10 outputs the bus request. At this time, the competition is not generated, but the circuit block uses the internal common bus 12 and further the circuit block competes with the circuit block on other substrate for the external common bus 1 through the external common bus competition circuit 11. Then, when the plural circuit blocks of the circuit blocks 141-14n in the substrate 10 output the bus request, only the highest order one of the internal common bus competition circuits, for instance, of the circuit block having the request of the internal common bus competition circuits 131-13n obtains the priority, uses the internal common bus, uses the internal common bus competition circuit 11 and competes the internal common bus 1.

Description

[Detailed Description of the Invention] [Object of the Invention] (Field of Industrial Application) The present invention provides an I! It is used when a large number of circuit components are connected to a bus.

(Prior art) A bus is used as a common signal path for collectively transmitting parallel information from multiple signal sources to multiple destinations with corresponding inputs, and is usually an address bus for address data. , a data bus for general data, and a control bus for system control.

The bus connection in the conventional device will be explained with reference to FIG.

According to the figure, substrates 21, 22 . . . each have circuits that operate asynchronously. . . . , 2o are provided for each board as bus contention circuits 31, 32, . . .

It is connected to the external common bus 1 via 3n.

Here, bus contention circuit 3.32. ......, 3o receives a bus use request from the corresponding circuit, checks whether the external common bus is open, and authorizes the connection between the bus and the circuit. However, if there are other requests to use the bus, contention will take place with other bus contention circuits such that the one that has issued a bus use request with a higher priority will use the bus preferentially. The adjustment of contention is called bus arbitration, and the priority order of the right to use the bus is determined by a parallel priority method or a serial priority method based on various signals.

In such conventional technology, the target of bus contention is the circuit connected to the bus contention circuit, so it is possible to operate asynchronously with each other on a single board by taking steps in circuit technology and component technology such as LSI. When a plurality of circuit blocks are formed, each circuit block must be provided with a contention circuit for the external common bus. However, providing a plurality of external common bus contention circuits on the same board reduces implementation efficiency.

[Problem that the invention seeks to solve]

As described above, in the conventional bus contention system, circuit blocks that operate asynchronously with each other require dedicated bus contention circuits, and there is a problem in that it is difficult to form a plurality of circuit blocks on the same board.

The present invention has been made to solve such problems, and an object of the present invention is to provide a bus contention system that allows a plurality of circuit blocks formed on the same board to compete for an external common bus.

[Structure of the invention]

(Means for solving the problem) According to the bus contention system according to the present invention,
A plurality of circuit blocks that perform IvJ operations and independently generate bus use requests, an internal common bus provided for these circuit blocks, and a circuit provided between the internal common bus and the plurality of circuit blocks. a plurality of internal common bus contention circuit units that select a circuit block with a high priority from a plurality of bus usage requests generated from the blocks and connect it to the internal common bus;
An external common bus contention circuit unit connected between an internal common bus and an external common bus is provided on one board, and a plurality of boards are connected to the external common bus, and bus When there is a request for use, the internal common bus contention circuit section first selects the internal common bus, and then the external common bus contention circuit section contests the external common bus.

(Function) In this bus contention method, the internal common bus contention circuitry contests for the internal common bus based on bus use requests from multiple circuit blocks provided on the same board, and then the external common bus contention circuitry contests for the internal common bus. Since the bus contention circuit section contests the external common bus, there is no need to provide an external common bus contention circuit for each circuit block, and it is possible to form multiple asynchronous operation circuit blocks on one board. It becomes possible.

(Embodiment) FIG. 1 is a block diagram showing a bus contention system according to the present invention.

There are a plurality of circuit blocks 14 within the board 10, each of which operates asynchronously and can independently contend for an external common bus. 14
, . . . , 14o and an internal common bus 12 are formed. This internal common bus 12 and each circuit block 14. 142. .......

14, internal common bus contention circuit units 13, 13□, . . . , 13o are connected for each circuit block, and these internal common bus contention circuit units are connected in a daisy chain. Of course, each internal common bus contention circuit 1
31,132. . . . A line 15 for transmitting a request is inputted at 13°, and m-connections are connected in a chain so that the output thereof becomes an input to the next circuit.

Further, the internal common bus 12 includes an external common bus contention circuit 11.
This circuit is connected to an external common bus 1 outside the board 10.

Next, the operation in such a configuration will be explained.

First, the circuit block 141 in the board 10. .

Assume that only one of 14, . . . , 14o outputs a bus request. At this time, there is no other circuit block outputting bus requests, so no contention occurs.
That circuit block will use the internal common bus 12, and furthermore, that circuit block will compete for the external common bus 1 with a circuit block on the other board via the external common bus contention circuit 11. .

Next, the circuit block 14 in the board 10. 142°...
. . , 14 output bus requests, the internal common bus contention circuit 13 . 13
, . . . , 13o, for example, among the internal common bus contention circuits of the requested circuit block, only the highest one obtains priority and uses the internal common bus, and the external common bus contention circuit 11 can be used to contest the external common bus 1.

In this embodiment, multiple circuit blocks use daisy-chained internal bus contention circuits to gain priority over an internal common bus, but the circuits compete according to a certain algorithm. Any control may be used as long as it performs control such as determining bus usage priority of blocks.

(Effects of the Invention) As described above in detail based on the embodiments, according to the present invention, bus use requests from a plurality of circuit blocks provided on the same board are adjusted by the internal common bus contention circuit section. Since the external common bus contention circuit is used to contest the external bus, there is no need to provide an external common bus contention circuit for each circuit block that operates asynchronously, and it is possible to use many circuit blocks on one board with area efficiency. It can be installed well.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration used in the bus contention system according to the present invention, and FIG. 2 is an explanatory diagram showing the selection of a conventional external common bus. 1... External common bus, 2.10... Board, 3.11
... External common bus contention circuit, 12... Internal common bus, 13... Internal common bus contention circuit, 14... Circuit block. Applicant's agent: Ichi Sato 1 Figure 2 Figure

Claims (1)

[Scope of Claims] 1. A plurality of circuit blocks that operate asynchronously with each other and independently generate bus usage requests; an internal common bus provided for these circuit blocks; the internal common bus and the a plurality of internal common bus contention circuit units that are provided between the plurality of circuit blocks and select the circuit block with a high priority from a plurality of bus use requests generated from the circuit blocks and connect the circuit block to the internal common bus; an external common bus contention circuit connected between an internal common bus and an external common bus on one board, a plurality of boards connected to the external common bus;
When a bus use request is received from the circuit block in the board, the internal common bus is first contested by the internal common bus contention route, and then the external common bus is contested by the external common bus contention circuit. A bus competition system that allows for competition. 2. The bus contention system according to claim 1, wherein the internal common bus contention circuit units are connected in a daisy chain.