JPS62256047A - Spurious fault generating system - Google Patents

Spurious fault generating system

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Publication number
JPS62256047A
JPS62256047A JP61099994A JP9999486A JPS62256047A JP S62256047 A JPS62256047 A JP S62256047A JP 61099994 A JP61099994 A JP 61099994A JP 9999486 A JP9999486 A JP 9999486A JP S62256047 A JPS62256047 A JP S62256047A
Authority
JP
Japan
Prior art keywords
input
pseudo
fault
output control
spurious fault
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP61099994A
Other languages
Japanese (ja)
Inventor
Satoshi Koizumi
小泉 訓
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP61099994A priority Critical patent/JPS62256047A/en
Publication of JPS62256047A publication Critical patent/JPS62256047A/en
Pending legal-status Critical Current

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  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE:To enable a spurious fault to be reset at an optional time in the process of a retrying process, and a detailed evaluation of the retrying process, by permitting the designation of the generating number of times of the spurious fault. CONSTITUTION:The program executes an expanded decor instruction based on a physical channel exceptional data. A spurious fault setting data is embedded in a firmware within an input/output control device 4 by the instruction, and simultaneously, a spurious fault generation counter 41 is zero-cleared, but in the state, a physical channel exception is not generated. Afterwards, when a control is handed to an operating system, and a channel command is executed for the data write request from another application job to a peripheral device 61 at an access bus, the value of the spurious fault generation counter 41 is compared with the designated number of times of the generation of the spurious fault, and when they coincide, no spurious fault is generated, and an input/output operation is terminated normally.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、演算処理装置と、該演算処理装置に接続され
た入出力制御装置と、該演算処理装置に接続された主記
憶装置とを含む情報処理システムで用いられる擬似障害
発生方式に関し、特に入出力制御装置に対する擬似障害
発生方式に関する。
Detailed Description of the Invention [Industrial Field of Application] The present invention provides an arithmetic processing device, an input/output control device connected to the arithmetic processing device, and a main storage device connected to the arithmetic processing device. The present invention relates to a pseudo-failure generation method used in an information processing system including, in particular, a pseudo-failure generation method for an input/output control device.

〔従来の技術〕[Conventional technology]

従来、この種の擬似障害発生方式では、発生回数を指定
して擬似障害を生じさせることは不可能であった。
Conventionally, with this type of pseudo-failure generation method, it has been impossible to specify the number of occurrences and cause a pseudo-fault to occur.

〔発明が解決しようとする問題点〕[Problem that the invention seeks to solve]

上述した従来の入出力制御装置に対する擬似障害発生方
式では、同一チャネルに対して再び入出力動作を行なっ
ても同一の擬似障害が永続的に発生してしまい、動作が
正常に終了するという再試行成功の処理を評価できない
という欠点がある。
In the above-mentioned conventional pseudo-failure generation method for input/output control devices, even if input/output operations are performed on the same channel again, the same pseudo-failure will permanently occur, and the operation will end normally. The drawback is that successful processing cannot be evaluated.

c問題点を解決するための手段〕 本発明の擬似障害発生方式は、主記憶装置内に格納され
、入出力制御装置番号と物理チャネル番号と論理チャネ
ル番号と擬似障害発生回数の指定情報を含む擬似障害設
定データと、前記擬似障害設定データに含まれる擬似障
害情報を入出力制御装置に設定する擬似障害設定手段と
、前記擬似障害が発生した回数を記憶する手段と、指定
された前記入出力制御装置番号、物理チャネル番号、論
理チャネル番号を有するチャネルへの入出力動作の回数
と設定された前記擬似障害発生回数とを比較する手段と
、比較結果に基き前記入出力制御装置に設定された前記
擬似障害を発生させる手段を有している。
Means for Solving Problem c] The pseudo-failure generation method of the present invention is stored in the main storage device and includes designation information of the input/output control unit number, physical channel number, logical channel number, and number of pseudo-failure occurrences. pseudo-fault setting means for setting pseudo-fault setting data and pseudo-fault information included in the pseudo-fault setting data in an input/output control device; means for storing the number of times the pseudo-fault has occurred; means for comparing the number of input/output operations to a channel having a control device number, a physical channel number, and a logical channel number with the set number of pseudo failure occurrences; It has means for generating the pseudo failure.

したがって、再試行処理過程の任意の時点で。Therefore, at any point during the retry process.

擬似障害をリセットでき、再試行処理の木目細かな評価
が行なえる。
Pseudo failures can be reset and retry processing can be evaluated in detail.

〔実施例〕〔Example〕

次に1本発明の実施例について図面を参照して説明する
Next, an embodiment of the present invention will be described with reference to the drawings.

第1図は本発明の擬似障害発生方式が適用された情報処
理システムの一実施例を示す構成図である。
FIG. 1 is a block diagram showing an embodiment of an information processing system to which the pseudo fault generation method of the present invention is applied.

主記憶装置1.演算処理装置3.入出力制御装置4はシ
ステム制御装置2に接続され、周辺制御装置5は入出力
制御装置4に、周辺装置131.82゜・・・、6nは
周辺制御装置5に接続されている。主記憶装置1内に格
納されている擬似障害設定データ!lは擬似障害情報指
定領域01を有している。また、入出力制御装置4は擬
似障害発生カウンタ41を有している。
Main storage device 1. Arithmetic processing unit 3. The input/output control device 4 is connected to the system control device 2, the peripheral control device 5 is connected to the input/output control device 4, and the peripheral devices 131, 82°, . . . , 6n are connected to the peripheral control device 5. Pseudo failure setting data stored in main storage device 1! 1 has a pseudo failure information designation area 01. Further, the input/output control device 4 has a pseudo failure occurrence counter 41.

第2図は第1図の主記憶装置l内に格納された擬似障害
発生プログラム(図示していない)により障害が発生し
、2度目のアクセスは正常終了する再試行成功フローの
一部を示す図である。
Figure 2 shows a part of a successful retry flow in which a failure occurs due to a pseudo failure program (not shown) stored in the main memory shown in Figure 1, and the second access ends normally. It is a diagram.

今、入出力制御装置番号「Q」、物理チャネル番号「l
」 、論理チャネル番号rlJを有する周辺装置61に
対するアクセスで、物理チャネル例外を起こさせる場合
を考える。不図示のオペレーティングシステム(以後、
O8と略す)下で1つのジョブとして起動をかけられた
擬似障害発生プログラムは、擬似障害情報指定領域11
1に対し擬似障害種別指定を物理チャネル例外に定め、
さらに、入出力制御装置指定領域、°周辺制御装置指定
領域、開通装置指定領域、擬似障害発生回数指定領域に
、各々入出力制御装置番号「O」、物理チャネル番号「
l」 、論理チャネル番号「1」 。
Now, the input/output controller number is "Q" and the physical channel number is "l".
'', a case will be considered in which a physical channel exception is caused by accessing the peripheral device 61 having the logical channel number rlJ. Operating system (not shown) (hereinafter referred to as
The pseudo-failure generation program that is started as one job under (abbreviated as O8) is
For 1, specify the pseudo failure type as a physical channel exception,
Furthermore, the input/output control device number "O" and the physical channel number "
l”, logical channel number “1”.

擬似障害発生回数「l」を書込む(処理21)0次に、
本プログラムは、この物理チャネル例外データをもとに
拡張デコール命令を実行する(処理22)、この命令に
より、入出力制御装置4内フアームウエアに擬似障害設
定データが埋め込まれる(処理23)、また、これと同
時に、擬似障害発生カウンタ41をゼロクリアする。(
処理20゜この状態では、物理チャネル例外は発生しな
い。
Write the number of pseudo failure occurrences “l” (process 21) 0 Next,
This program executes an extended decall instruction based on this physical channel exception data (processing 22), and this instruction embeds pseudo failure setting data in the firmware in the input/output control device 4 (processing 23). , At the same time, the pseudo failure occurrence counter 41 is cleared to zero. (
Process 20: In this state, no physical channel exception occurs.

その後、O5に制御が渡り、別のアプリケーションジ3
ブからの前記周辺装置81へのデータ書込要求に対して
前記アクセスバスにてチャネルコマンドを実行した(処
理25)時に、擬似障害発生カウンタ4!の値を処理2
1で設定された擬似障害発生指定回数と比較しく処理2
B)、これよりも小さいので物理チャネル例外が発生し
く処理27)、擬似障害発生カウンタ41はl”加算さ
れる(処理28)。
Control then passes to the O5 and another application
When a channel command is executed on the access bus in response to a data write request from the bus to the peripheral device 81 (process 25), the pseudo failure occurrence counter 4! Process the value of 2
Processing 2 compared to the specified number of pseudo failure occurrences set in 1.
B), since it is smaller than this, a physical channel exception will occur; process 27), and the pseudo failure occurrence counter 41 is incremented by l'' (process 28).

入出力動作が異常終了したので、O5は同一チャネルに
対して再びアクセスを行なうが(処理29)。
Since the input/output operation has ended abnormally, O5 accesses the same channel again (process 29).

擬似障害情報カウンタ41の値と処理21で設定された
擬似障害発生指定回数を比較しく処理30)、その結果
等しくなるので擬似障害は発生せず、入出力動作は正常
終了する(処理31)、同様に、処理21でn回の擬似
障害発生回数が指定されれば、n回の入出力動作でn回
の擬似障害が発生し、(n+1)回目からは入出力動作
は正常終了することは容易に類推できる。
Compare the value of the pseudo-failure information counter 41 and the designated number of pseudo-failure occurrences set in process 21 (process 30), and as the result becomes equal, no pseudo-failure occurs and the input/output operation ends normally (process 31); Similarly, if the number of pseudo failure occurrences of n times is specified in process 21, n pseudo failures will occur during n input/output operations, and input/output operations will not end normally from the (n+1)th time onward. It is easy to make an analogy.

〔発明の効果〕 以上説明したように本発明は、擬似障害発生回数を指定
できるようにすることにより、再試行処理過程の任意の
時点で擬似障害をリセットできるため、再試行処理の木
目細かな評価を行なえる効果がある。
[Effects of the Invention] As explained above, the present invention allows the pseudo failure to be reset at any point in the retry processing process by allowing the number of pseudo failure occurrences to be specified. It has the effect of allowing evaluation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の擬似障害発生方式が適用された情報処
理システムの一実施例を示す構成図、第2図は再試行成
功のフローの一部を示す図である。 1・・・主記憶装置、  2・・・システム制御装置。 3・・・演算処理装置、 4・・・入出力制御装置、5
・・・周辺制御装置、  81〜6n・・・周辺装置、
11・・・擬似障害設定データ、 111・・・擬似障害情報指定領域。 41・・・擬似障害発生カウンタ。 Jl’!1図
FIG. 1 is a block diagram showing an embodiment of an information processing system to which the pseudo failure generation method of the present invention is applied, and FIG. 2 is a diagram showing a part of the flow of a successful retry. 1... Main storage device, 2... System control device. 3... Arithmetic processing device, 4... Input/output control device, 5
...Peripheral control device, 81-6n...Peripheral device,
11... Pseudo fault setting data, 111... Pseudo fault information specification area. 41...Pseudo failure occurrence counter. Jl'! Figure 1

Claims (1)

【特許請求の範囲】 演算処理装置と、該演算処理装置に接続された入出力制
御装置と、該演算処理装置に接続された主記記憶装置と
を含む情報処理システムにおいて、 前記主記憶装置内に格納され、入出力制御装置番号と物
理チャネル番号と論理チャネル番号と擬似障害発生回数
の指定情報を含む擬似障害設定データと、前記擬似障害
設定データに含まれる擬似障害情報を入出力制御装置に
設定する擬似障害設定手段と、 前記擬似障害が発生した回数を記憶する手段と、 指定された前記入出力制御装置番号、物理チャネル番号
、論理チャネル番号を有するチャネルへの入出力動作の
回数と設定された前記擬似障害発生回数とを比較する手
段と、 比較結果に基き前記入出力制御装置に設定された前記擬
似障害を発生させる手段を有する擬似障害発生方式。
[Scope of Claims] An information processing system including an arithmetic processing device, an input/output control device connected to the arithmetic processing device, and a main storage device connected to the arithmetic processing device, comprising: The simulated failure setting data that is stored in the input/output control unit and includes designation information of the input/output control unit number, physical channel number, logical channel number, and number of simulated failure occurrences, and the simulated failure information included in the simulated failure setting data are sent to the input/output control unit. a pseudo-fault setting means for setting; a means for storing the number of times the pseudo-fault has occurred; and setting the number of input/output operations to a channel having the specified input/output control device number, physical channel number, and logical channel number. and means for generating the pseudo fault set in the input/output control device based on the comparison result.
JP61099994A 1986-04-28 1986-04-28 Spurious fault generating system Pending JPS62256047A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61099994A JPS62256047A (en) 1986-04-28 1986-04-28 Spurious fault generating system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61099994A JPS62256047A (en) 1986-04-28 1986-04-28 Spurious fault generating system

Publications (1)

Publication Number Publication Date
JPS62256047A true JPS62256047A (en) 1987-11-07

Family

ID=14262186

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61099994A Pending JPS62256047A (en) 1986-04-28 1986-04-28 Spurious fault generating system

Country Status (1)

Country Link
JP (1) JPS62256047A (en)

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