JPS6225526A - Clock transmission system - Google Patents

Abstract

PURPOSE:To eliminate the effect of leakage between signal lines sending a clock by using a pair lines to send clock opposite in phase to each other and separating them at the reception side. CONSTITUTION:An output of a clock generating section 6 is branched into two, one is fed directly to a clock line 9 and the other is fed to a clock line 10 via an inverter 11. The clock lines 9, 10 constitute a pair line, which is separated at reception sections 7, 8. The clock sent through the clock line 9 is inputted as it is to the reception section 7 and the clock sent through the clock line 10 is inputted to the reception section 8 after being inverted by an inverter 12. Thus, the leaked component of the clock lines 9, 10 is cancelled, then the effect of crosstalk is prevented.

Description

[Detailed Description of the Invention] [Summary] In order to eliminate the influence of leakage between signal lines that transmit clocks, reversely transmitted clocks are transmitted using paired wires.

[Industrial application field]

The present invention relates to a clock transmission method used for distributing clocks in PCM transmission devices and the like.

As shown in FIG. 3, when data is transmitted between stations A and B, each station extracts a clock from the received data and supplies it to each device making up the station.

That is, as shown in FIG. 4, one housing 6 houses a clock distribution section 1 and a multiplexing/demultiplexing section 2.3.4, and the clock extracted by the clock distribution 1 is sent to each multiplexer using the clock line 5. Distribute to heavy fist distribution section 2.3.4.

[Prior art]

Conventionally, when distributing this clock, the waveform of the clock deteriorates significantly due to crosstalk between wires, so generally, as shown in Fig. 5, an unbalanced to balanced conversion circuit T is used to convert it into a -balanced signal, transmit it, and receive it. is converted into an unbalanced signal by a balanced to unbalanced conversion circuit T on the side.

[Problems with conventional technology]

As mentioned above, conventionally, unbalanced to balanced conversion circuits and balanced to unbalanced conversion circuits are used, which has the problem of large circuit scale.

[Means to solve the problem]

In the present invention, therefore, as shown in FIG.

The clock lines 9 and 10 constitute a pair of lines, and the receiving section 7
, 8. The clock transmitted by the clock line 10 is then inverted by the inverter.

[Effect]

According to the present invention, clocks having opposite phases are transmitted using a pair of wires, so that leakage components are canceled, so that the influence of crosstalk can be eliminated.

〔Example〕

The present invention will be explained in detail with reference to FIG.

In the figure, 20 is a clock generation section, 21 to 24 are multiple tube separation sections, 25, 26t, 27, 28 are clock lines, 29.3
1, 32.33 is a line driver, 34.3637.
39 is a line receiver, and 30, 35, and 38 are inverters.

The clock lines 25 and 26 and the clock lines 27 and 28 constitute a pair of lines, respectively.The clock line 25 is connected to a line driver 29, and the clock line 26 is connected to an inverter 30.
Since the clock from the clock generator 20 is supplied via the line driver 31, the clock lines 25 and 26 are supplied with clocks having mutually opposite phases.

In addition, the clock line 27 is connected via a line driver 27.
An inverter 30 and a line driver 3 are connected to the clock line 28.
3, clocks of opposite phases are supplied respectively.

The clock transmitted by the clock @25 is sent to the multiplexing/separating section 21, the clock transmitted via the clock line 26 is sent to the multiplexing/separating section 22, the clock transmitted via the clock line 27 is sent to the multiplexing/separating section 23, and the clock is sent to the multiplexing/separating section 21. The clock transmitted through line 28 is supplied to multiplexer/demultiplexer 24 .

Diagram showing Yoshida Ono Kaya 3 diagram Blood field Yoshino) Show field 4pm ward IAjime apitching・ding・zuzu Planned 5 countries

Claims (1)

[Claims] A clock transmission method characterized by transmitting clocks having opposite phases to each other using a pair of wires, and separating the pair of wires on the receiving side.