JPS62254455A - Pinless package and mounting method thereof - Google Patents

Pinless package and mounting method thereof

Info

Publication number
JPS62254455A
JPS62254455A JP9853386A JP9853386A JPS62254455A JP S62254455 A JPS62254455 A JP S62254455A JP 9853386 A JP9853386 A JP 9853386A JP 9853386 A JP9853386 A JP 9853386A JP S62254455 A JPS62254455 A JP S62254455A
Authority
JP
Japan
Prior art keywords
package
circuit
bonding agent
particles
terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP9853386A
Other languages
Japanese (ja)
Other versions
JP2572570B2 (en
Inventor
Kenji Itaya
賢二 板谷
Taro Yamazaki
太郎 山崎
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Osaka Soda Co Ltd
Original Assignee
Osaka Soda Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Osaka Soda Co Ltd filed Critical Osaka Soda Co Ltd
Priority to JP61098533A priority Critical patent/JP2572570B2/en
Publication of JPS62254455A publication Critical patent/JPS62254455A/en
Application granted granted Critical
Publication of JP2572570B2 publication Critical patent/JP2572570B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/321Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives
    • H05K3/323Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by conductive adhesives by applying an anisotropic conductive adhesive layer over an array of pads

Landscapes

  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Electric Connection Of Electric Components To Printed Circuits (AREA)

Abstract

PURPOSE:To form the pitch between terminals in a microscopic manner by a method wherein a pick-up terminal with which an electric connection is performed with a circuit substrate, is provided on the mounting surface of the main body of the title package, and they are connected using an insulative bonding agent. CONSTITUTION:A package and a printed wiring substrate are electrically connected by interposing a bonding agent between them and by performing positioning and pressure-welding operations. They can be pressurewelded by coating anisotropic conductive bonding agent on the whole surface of the connecting part of a circuit. As for conductive particles it is desirable to use abrasive grain like particles, because they produce an anchor effect on the surface of the opposing circuits. Pertaining to the method of adhesion, metal-plating in which conductive superhard material grains are misced is performed on the circuit of the circuit substrate or the pick-up terminal of the pinless package opposing to said circuit, and they are pressure-welded through the intermediary of an insulative bonding agent. As said particles are in an abrasive granular state and they have a high degree of hardness, they break the insulative bonding agent when the pressure-welding work is performed, they cut into the pick-up terminal of the package and the circuit of the circuit substrate and an electrical continuity is performed.

Description

【発明の詳細な説明】 (発明の技術的分野) 本発明は電子回路用素子を搭載する回路基板の高度なも
のを用意して、その上に異方導電性接着剤等で回路素子
を搭載するのに自動化できる高密度回路素子形態をとる
ピンレスパッケージに関する。
[Detailed Description of the Invention] (Technical Field of the Invention) The present invention involves preparing an advanced circuit board on which electronic circuit elements are mounted, and mounting the circuit elements thereon using an anisotropic conductive adhesive or the like. The present invention relates to a pinless package in the form of a high-density circuit element that can be automated for processing.

(従来の技術と問題点) 従来、電子機器のプリント配線板等の回路基板に各種部
品を実装するのは、主としてはんだ付は接続によってい
た。今日電子部品の軽薄短小化。
(Prior Art and Problems) Conventionally, various components have been mounted on circuit boards such as printed wiring boards of electronic devices mainly by soldering. Today, electronic components are becoming lighter, thinner, and smaller.

実装コストの低減や信頼性の向上を自損して、はんだ付
けもリフロー的手段による平面実装の時代に入ろうとし
ている。このため基板に装着される部品素子はチップ化
され、自動装着に適したものへ、またはんだもこれに適
した高性能なものへと改良されてきている。
At the expense of lowering mounting costs and improving reliability, we are entering an era of planar mounting using reflow soldering methods. For this reason, the component elements mounted on the board have been made into chips and have been improved to be suitable for automatic mounting, and the solder has also been improved to have high performance suitable for this purpose.

しかしながら、はんだ付は接続に頼る限りパッケージ本
体等の部品の熱損傷は避けられず、モールド及びリード
フレームではんだ付は時の熱吸収により半導体保護の働
きもしている。そのためパッケージ本来の大きざの20
〜150倍になって小型化できない理由の1つとなって
いる。またLSI等ピンのピッチが狭小なものは、ピン
数が多いためリフロー後の接続不良あるいは過剰はんだ
のブリッジによるピン間のショート等、種々の問題が生
じている。
However, as long as soldering relies on connections, heat damage to components such as the package body is unavoidable, and soldering on molds and lead frames also serves to protect the semiconductor by absorbing heat over time. Therefore, the original size of the package is 20
This is one of the reasons why it is not possible to downsize the size by ~150 times. In addition, devices such as LSIs with narrow pin pitches have a large number of pins, resulting in various problems such as poor connections after reflow or short circuits between pins due to bridging of excessive solder.

(発明の目的) 本発明の目的は、上記の問題点に鑑みモールドと母体よ
り大きいリードフレームを除き、機能性を持つ受動素子
、キャビネット、コンデンサー。
(Object of the Invention) In view of the above-mentioned problems, the object of the present invention is to provide a functional passive element, cabinet, and capacitor, excluding a mold and a lead frame larger than the mother body.

コイルチップそのもの、ダイオード、トランジスタ、I
Cの裸に近いチップ状ではんだ付は等を不要ならしめて
プリント回路板上に異方導電性接着剤等にて接合できる
ピンレスパッケージを提供することにある。
Coil chip itself, diode, transistor, I
The object of the present invention is to provide a pinless package that can be bonded to a printed circuit board using an anisotropic conductive adhesive or the like, with C in the form of an almost bare chip, making soldering unnecessary.

(発明の構成) 本発明はすなわち、電子回路用素子として実装に供する
パッケージにおいて回路基板と電気的接続を行う取り出
し端子を上記パッケージ本体の実装面上に設けてなるピ
ンレスパッケージと、このピンレスパッケージの回路基
板への実装方法である。
(Structure of the Invention) The present invention relates to a pinless package in which a takeout terminal for electrically connecting to a circuit board is provided on the mounting surface of the package body in a package to be mounted as an electronic circuit element, and the pinless package. This is a method for mounting a package on a circuit board.

図面により本発明を説明すると、第2図は従来のパッケ
ージ例を示し、パッケージ(1)には内蔵する回路に相
当するピッチ(2)が多数取り付けられており、プリン
ト配線基板(3)には上記ピッチ(2)に対応する接続
部の回路パターン(4)がはんだメッキあるいはクリー
ムハンダで印刷されており、パッケージ(1)を仮に接
着してはんだ付等の方法で(2)(4)が接続される。
To explain the present invention with reference to the drawings, Fig. 2 shows an example of a conventional package, in which the package (1) is equipped with a large number of pitches (2) corresponding to the built-in circuits, and the printed wiring board (3) is equipped with a number of pitches (2) corresponding to the built-in circuits. The circuit pattern (4) of the connection part corresponding to the pitch (2) above is printed with solder plating or cream solder, and (2) and (4) are made by temporarily bonding the package (1) and soldering. Connected.

第1図(イ) (ロ) (ハ)は本発明パッケージを例
示し、第1図(ニ)は本発明パッケージが実装されるプ
リント配線基板を示す。
FIGS. 1(a), (b), and (c) illustrate the package of the present invention, and FIG. 1(d) shows a printed wiring board on which the package of the present invention is mounted.

角型フラットパッケージ(5)、FPタイプ円型フラッ
トパッケージ(6)には、それぞれプリント配線基板(
1)の回路接続部パターン(8’)(9’)に対応する
接続部パターン(8)(9)が設けられている。第1図
(イ) (ロ)の回路接続部パターンは、いずれもパッ
ケージ本体に印刷されているが、第1図(ハ)のごとく
パッケージに外縁部(10)を設け、これに回路接続部
パターン(9)を印刷してもよい。
The square flat package (5) and the FP type circular flat package (6) each have a printed wiring board (
Connection part patterns (8) and (9) corresponding to the circuit connection part patterns (8' and 9') of 1) are provided. The circuit connection patterns in Figures 1 (A) and (B) are both printed on the package body, but as shown in Figure 1 (C), the outer edge (10) is provided on the package, and the circuit connection patterns are printed on the package body as shown in Figure 1 (C). Pattern (9) may also be printed.

パッケージを搭載するプリント配線基板はセラミックガ
ラス、ガラスエポキシ、ガラストリアジン、ガラスジア
リルフタレート、ポリフェニレンオキシド、ポリエステ
ルフィルム等用途に合わせて挿々の材質が選ばれる。そ
してプリント配線基板、パッケージの回路接続部分く取
り出し端子)の材質は従来と同種のものが利用できる。
The printed wiring board on which the package is mounted is made of ceramic glass, glass epoxy, glass triazine, glass diallyl phthalate, polyphenylene oxide, polyester film, and other materials selected depending on the application. The same materials as conventional ones can be used for the printed wiring board and the circuit connection part of the package (extracting terminals).

すなわちガラスエポキシ、ガラストリアジン、ガラスジ
アリルフタレート等の基板に銅箔等の金属箔あるいはポ
リフェニレンオキシド、ポリエステル、ポリカーボネー
トフィルムに導電性インキで印刷したもの、あるいはセ
ラミック板またはガラス板にグレーズ皮膜を形成したも
の等いずれも用いられる。
In other words, a substrate made of glass epoxy, glass triazine, glass diallyl phthalate, etc., printed with conductive ink on a metal foil such as copper foil, or a polyphenylene oxide, polyester, or polycarbonate film, or a glaze film formed on a ceramic plate or glass plate. etc. are all used.

これらパッケージとプリント配線基板との電気的接続は
、両者の間に接着剤を介在させ位置合わせして圧着する
The electrical connection between these packages and the printed wiring board is achieved by interposing an adhesive between the two, aligning them, and pressing them together.

すなわち従来は回路接続部パターンに導電性接着剤を塗
布して圧着する方法が通常知られているが、電極端子の
ピッチ間隔が狭いため塗布が困難である。本発明におい
ては回路接続部全面(端子以外の部分を含めて)に異方
導電性接着剤を塗布して圧着することができる。
That is, conventionally, a method of applying a conductive adhesive to a circuit connection pattern and crimping it is known, but the application is difficult because the pitch of the electrode terminals is narrow. In the present invention, an anisotropic conductive adhesive can be applied to the entire surface of the circuit connection part (including parts other than the terminals) and the circuit can be crimped.

異方導電性接着剤中の導電性粒子としては砥粒状の粒子
、すなわち多数の突起、突稜の如き表面形状を有する例
えば多面体状、金米糖状の粒子が対向回路面にアンカー
効果をもたらすので好ましい。
As the conductive particles in the anisotropic conductive adhesive, abrasive-like particles, such as polyhedral or sugar-like particles having a surface shape such as a large number of protrusions or ridges, are preferable because they provide an anchoring effect on the opposing circuit surface. .

このような砥粒状の導電性粒子としてはカルボニル法で
つくられるニッケル、コバルト、鉄等の砥粒状金属粒子
、又はアトマイ法あるいはスタンプ法によるこれらの金
属の合金の砥粒状金属合金粒子、又は砥粒状超硬材料粒
子、あるいはこれらの表面又は砥粒状の金属酸化物粒子
の表面をニツケル、銅、銀、金、白金、ロジウム、ルテ
ニウム。
Such abrasive conductive particles include abrasive metal particles of nickel, cobalt, iron, etc. produced by the carbonyl method, abrasive metal alloy particles of alloys of these metals produced by the atomization method or stamp method, or The surface of superhard material particles or these or abrasive metal oxide particles is made of nickel, copper, silver, gold, platinum, rhodium, or ruthenium.

オスミウム、パラジウム等の高導電性金属でメッキした
砥粒状導電性粒子が挙げられる。上記砥粒状の導電性超
硬材料粒子としては周期律表第1VB族、第VB族、第
VIB族の炭化物、ホウ化物、ケイ化物、及びランタン
のホウ化物の粒子が挙げられる。その粒径は通常的0.
3〜50μmである。具体的にはチタン、ニオブ、タン
タル、クロム、モリブデン、及びタングステンの炭化物
、ホウ化物。
Examples include abrasive conductive particles plated with highly conductive metals such as osmium and palladium. Examples of the abrasive conductive superhard material particles include carbides, borides, and silicides of Group I, VB, and VIB of the periodic table, and particles of lanthanum borides. Its particle size is usually 0.
It is 3 to 50 μm. Specifically, carbides and borides of titanium, niobium, tantalum, chromium, molybdenum, and tungsten.

ケイ化物、ホウ化ランタレ等の粒子とコロイド員金属粉
を主成分としたペーストを塗布して圧着する。この際、
絶縁性接着剤を介在させてもよい。
A paste mainly composed of particles of silicide, lanthale boride, etc. and colloidal metal powder is applied and pressed. On this occasion,
An insulating adhesive may be used.

接着方法としてはこのような導電性超硬材料粒子を回路
基板の回路あるいはこれに対向するピンレスパッケージ
の取り出し端子に混入したメッキを行い、絶縁性接着剤
を介して圧着することもできる。又は回路上あるいは端
子上に導電性超硬材料を混入したペーストの塗布膜を形
成し、絶縁性接着剤を介して圧着することもできる。
As an adhesion method, such conductive superhard material particles may be mixed into the circuit of the circuit board or the lead-out terminal of the pinless package facing the circuit board and plated, and then crimped with an insulating adhesive. Alternatively, it is also possible to form a coating film of a paste containing a conductive superhard material on the circuit or the terminal, and press the paste with an insulating adhesive.

これらの粒子は砥粒状でかつ硬度が大であるため、圧着
時に絶縁性接着剤層を破り、パッケージの取り出し端子
及び回路基板の回路に喰込んで電気的導通が行われる。
Since these particles are abrasive-like and have a high hardness, they break the insulating adhesive layer during crimping and bite into the take-out terminals of the package and the circuits of the circuit board, thereby establishing electrical continuity.

この場合は回路接続部分以外の表面部分も絶縁性接着剤
により接着してもよい。パッケージの製造工程及びそれ
を回路基板上に搭載する工程に取り入れるためには従来
のボンディング、はんだ付けの工程と同程度の時間で処
理できなければならない。そこで通常絶縁性接着剤とし
ては、シアノアクリレート系の°“瞬間接着剤″や(メ
タ)アクリレート系の“嫌気性接着剤パ“カプセル硬化
型接着剤”等速硬性接着剤が好ましい。場合により特性
上、工程上支障がなければエポキシ樹脂系接着剤、シリ
コン樹脂系接着剤も使用し得る。
In this case, surface portions other than the circuit connection portions may also be bonded with an insulating adhesive. In order to incorporate it into the package manufacturing process and the process of mounting it on a circuit board, it must be possible to process it in the same amount of time as conventional bonding and soldering processes. Therefore, as the insulating adhesive, it is usually preferable to use a cyanoacrylate-based "instant adhesive" or a (meth)acrylate-based "anaerobic adhesive" or "capsule curing adhesive" constant-speed hardening adhesive. Additionally, epoxy resin adhesives and silicone resin adhesives may also be used as long as they do not cause any problems in the process.

回路接続部分いわゆる端子はDIPで40ピン、超LS
Iのチップキャリアではそれ以上が一般的であり、その
接触面積が大きい程、接続抵抗が小さくなるが、あまり
大きくすると端子数の増加に伴い端子間ピッチが狭くな
り端子間の絶縁性確保が困難になる。逆に接触面積を小
さくするとパッケージと基板との端子同士の位置合わせ
に高精度が要求されることになって、超LSIのチップ
キャリアパッケージではピン数も増し、ピッチ30μm
のものを必要とするので実際の要求に応じて適切な端子
サイズを選択する。
The circuit connection part, so-called terminal, is DIP, 40 pins, super LS
It is common for I chip carriers to have more than this, and the larger the contact area, the lower the connection resistance, but if it is too large, the pitch between the terminals will become narrower as the number of terminals increases, making it difficult to ensure insulation between the terminals. become. Conversely, reducing the contact area requires high precision in positioning the terminals between the package and the board, and the number of pins increases in VLSI chip carrier packages, resulting in a pitch of 30 μm.
Select the appropriate terminal size according to the actual requirements.

パッケージ端子の高さは接着接続の結果に大きく影響す
るので注意が必要である。パッケージ本体と基板本体(
端子以外の部分にレジストがある場合はこれを含む)の
クリアランスは圧着接続後、約1履以内になっているこ
とが望ましい。本来接着の強さは接着層の厚みが小ざい
程大きく、接着剤の消費最も少量で済み、接着後の外観
も端正となる。このように端子の高さは接着状態に基づ
いて定めなければならないが、基本的にはこれらの端子
はパッケージ本体、基板本体と同一平面上にあることが
好ましい。但し、パッケージの端子は表面内にある程度
陥没した構造でも差支えなく、これは端子表面を保護す
るためにフィルムでシールしたり、あるいはテープキャ
リアタイプのパッケージとして取扱うような場合は便利
な構造である。上記の絶縁性接着剤を使用する場合は、
パッケージや基板表面の材質にもよるが、接着剤の種類
を適切に選定することにより、接着剤自身の界面張力の
作用で接着面の隅々にまで接着剤が行きわたるようにな
る。、逆に、この接着剤の界面張力を利用して両者の対
向する端子を位置合わせ後や、加圧時に接着剤の滴下を
行うことも可能である。
Care must be taken as the height of the package terminals greatly affects the results of adhesive connections. Package body and board body (
It is desirable that the clearance (including resist in areas other than the terminals, if any) is within about one shoe after crimping connection. The smaller the thickness of the adhesive layer, the greater the adhesive strength, which means that the least amount of adhesive is consumed and the appearance after adhesion is more attractive. As described above, the height of the terminals must be determined based on the bonding state, but basically it is preferable that these terminals be on the same plane as the package body and the substrate body. However, the terminals of the package may have a structure that is recessed to some extent within the surface, and this is a convenient structure when the terminal surface is sealed with a film to protect it or when it is handled as a tape carrier type package. When using the above insulating adhesive,
Although it depends on the material of the package and substrate surface, by appropriately selecting the type of adhesive, the interfacial tension of the adhesive itself will allow the adhesive to spread to every corner of the adhesive surface. Conversely, it is also possible to use the interfacial tension of the adhesive to drip the adhesive after aligning the opposing terminals or during pressurization.

この方法は接着剤のポットライフが短い場合に有利であ
る。
This method is advantageous when the pot life of the adhesive is short.

実施例1 第1図(イ)の如きフラットパッケージ(回路幅0.3
#1111.ピッチ0.658 >とプリント配線基板
として厚さ18μmの銅箔を張ったガラスエポキシ積層
板にパッケージと同様の回路幅ピッチ幅の総数100本
の回路を形成するようにエツチングしたものとを製作し
た。第1図(ニ)の(8′)の部分に下記ペーストを厚
さ約10μで塗布した(組成は重母部)。
Example 1 A flat package (circuit width 0.3
#1111. A glass epoxy laminate with a pitch of 0.658 and a printed wiring board covered with 18 μm thick copper foil was etched to form a total of 100 circuits with the same pitch width as the package. . The following paste was applied to the part (8') in FIG. 1(d) to a thickness of about 10 μm (composition is heavy matrix).

接着剤(A剤) (商品名ボンドコニ−ワン。Adhesive (A agent) (Product name: Bondcony-One.

コニシ社製>     ioo部 WSi2(粒径1〜6μ9日本新金属社製)20部 TiC(粒径8〜17μ、昭和電工社製)8部 また上記パッケージの接続部分には、上記接着剤のプラ
イマー成分(B剤)をうずく塗り、配線板上に乗せて位
置合わせを行い、上から約1ONgの圧力を約2秒間か
けた。
Manufactured by Konishi Co., Ltd. > ioo part WSi2 (particle size 1 to 6μ9, manufactured by Japan Shinkinzoku Co., Ltd.) 20 parts TiC (particle size 8 to 17μ, manufactured by Showa Denko) Component (Agent B) was applied in a tingling manner, placed on the wiring board, aligned, and a pressure of about 1 ONg was applied from above for about 2 seconds.

このようにして合計50点の回路接続間の抵抗値を測定
した。
In this way, resistance values between circuit connections at a total of 50 points were measured.

抵抗測定値(Ω) 70℃95%RH 初期値     2000時間処理後 平均   0.256     0.275最大   
0.303     0.361最小   0.237
     0.242また各端子間の絶縁抵抗値を測定
した。
Resistance measurement value (Ω) 70℃95%RH Initial value Average after 2000 hours treatment 0.256 0.275 Maximum
0.303 0.361 minimum 0.237
0.242 The insulation resistance value between each terminal was also measured.

端子間絶縁抵抗値(Ω) 10℃95%RH 初期値     2000時間処理後 平均   6X10128×1011 最大   24X10129×1012最小  1.8
X10123 XIO”得られたデータは、パッケージ
の接続が十分信頼できることを示している。
Insulation resistance value between terminals (Ω) 10℃95%RH Initial value Average after 2000 hours treatment 6 x 10128 x 1011 Maximum 24 x 10129 x 1012 Minimum 1.8
X10123

(発明の効果) 本発明のパッケージは、本体実装面に回路基板と電気的
接続を行う取り出し端子を設けてなり、異方導電性接着
剤を用いるか接合時に十分な導電性を得られるように加
工し、両者の接続を短時間で硬化する絶縁性接−着剤を
用いて強固に接続し得られることを特徴とする。それ故
、従来品のごとくパッケージ本体外部にピンを付設して
はんだ付けによる接続を行う必要はない。したがって接
続部分の端子間ピッチを極めて微細なものとすることが
でき、またピンの付設による余分な基板面積が省略でき
る。またはんだ付けによる熱ショックを考えないでよい
のでIC素子の選定幅が大で繁雑な工程を要せず、これ
による基板の損傷を避は得られる。ざらにはだかに近い
状態で基板に搭載できるので薄型、小形化、及び工程の
自動化に適合させることができる。
(Effects of the Invention) The package of the present invention is provided with a take-out terminal for electrically connecting to the circuit board on the mounting surface of the main body, and an anisotropic conductive adhesive or an anisotropic conductive adhesive is used to obtain sufficient conductivity during bonding. It is characterized in that it can be processed and firmly connected using an insulating adhesive that hardens in a short time. Therefore, unlike conventional products, there is no need to attach pins to the outside of the package body and connect them by soldering. Therefore, the pitch between the terminals of the connection portion can be made extremely fine, and the extra board area due to the provision of pins can be omitted. Furthermore, since there is no need to consider thermal shock due to soldering, there is a wide selection range of IC elements, no complicated processes are required, and damage to the board caused by this can be avoided. Since it can be mounted on a substrate in a nearly bare state, it can be made thinner, more compact, and suitable for process automation.

【図面の簡単な説明】[Brief explanation of drawings]

第1図(イ) (ロ) (ハ)は本発明ピンレスパッケ
ージの種々の態様を示す斜視図、第1図(ニ)は(イ)
 (ロ)のピンレスパッケージの回路接続部パターンに
対応する回路接続部パターンを設けたプリント配線基板
の斜視図である。第2図(イ)(ロ)は従来品パッケー
ジ及びプリント配線基板の斜視図である。 (1)・・・従来品パッケージ、(2)・・・ピッチ。 (5)(6)・・・ピンレスパッケージ、(7)・・・
プリント配線基板、(8)(9)・・・ピンレスパッケ
ージの回路接続部、(8’ >(9’ )・・・配線基
板の回路接続部 (Aン           (ロン        
   (/%](ニ)
Figures 1 (a), (b), and (c) are perspective views showing various aspects of the pinless package of the present invention, and Figure 1 (d) is (a).
FIG. 3 is a perspective view of a printed wiring board provided with a circuit connection pattern corresponding to the circuit connection pattern of the pinless package (b). FIGS. 2(a) and 2(b) are perspective views of a conventional package and a printed wiring board. (1)...Conventional product package, (2)...Pitch. (5)(6)...Pinless package, (7)...
Printed wiring board, (8) (9)...Circuit connection part of pinless package, (8'>(9')...Circuit connection part (A) of wiring board
(/%] (d)

Claims (4)

【特許請求の範囲】[Claims] (1)電子回路用素子として実装に供するパッケージに
おいて、回路基板と電気的接続を行う取り出し端子を上
記パッケージ本体の実装面上に設けてなるピンレスパッ
ケージ。
(1) A pinless package, which is used for mounting as an electronic circuit element, and has a lead-out terminal for electrically connecting to a circuit board on the mounting surface of the package body.
(2)回路基板と電気的接続を行う取り出し端子を本体
実装面上に設けたピンレスパッケージを異方導電性接着
剤を介して上記回路基板と圧着することを特徴とするピ
ンレスパッケージの実装方法。
(2) Mounting of a pinless package characterized in that a pinless package in which a lead-out terminal for electrical connection with a circuit board is provided on the mounting surface of the main body is crimped to the circuit board using an anisotropic conductive adhesive. Method.
(3)異方導電性接着剤中の導電性粒子として超硬材料
粒子を使用する特許請求の範囲第2項記載の実装方法。
(3) The mounting method according to claim 2, wherein superhard material particles are used as the conductive particles in the anisotropic conductive adhesive.
(4)回路基板と電気的接続を行う取り出し端子を本体
実装面上に設けたピンレスパッケージを上記回路基板と
電気的接続を行うに際し、上記回路基板の回路あるいは
上記ピンレスパッケージの取り出し端子に導電性超硬材
料粒子を混入したメッキを行うか、又は回路上あるいは
端子上に導電性超硬材料粒子を含有するペーストの塗布
膜を形成し、絶縁性接着剤を介して圧着することを特徴
とするピンレスパッケージの実装方法。
(4) When electrically connecting a pinless package that has a take-out terminal for making an electrical connection with the circuit board on the mounting surface of the main body with the circuit board, the circuit board or the take-out terminal of the pinless package should be connected to the circuit board. It is characterized by plating with conductive carbide material particles mixed in, or by forming a coating film of paste containing conductive carbide material particles on the circuit or terminal, and then press-bonding with an insulating adhesive. How to implement a pinless package.
JP61098533A 1986-04-28 1986-04-28 Pinless package mounting method Expired - Lifetime JP2572570B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61098533A JP2572570B2 (en) 1986-04-28 1986-04-28 Pinless package mounting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61098533A JP2572570B2 (en) 1986-04-28 1986-04-28 Pinless package mounting method

Publications (2)

Publication Number Publication Date
JPS62254455A true JPS62254455A (en) 1987-11-06
JP2572570B2 JP2572570B2 (en) 1997-01-16

Family

ID=14222313

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61098533A Expired - Lifetime JP2572570B2 (en) 1986-04-28 1986-04-28 Pinless package mounting method

Country Status (1)

Country Link
JP (1) JP2572570B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6411518B1 (en) 2000-02-01 2002-06-25 Mitsubishi Denki Kabushiki Kaisha High-density mounted device employing an adhesive sheet
WO2017149426A1 (en) * 2016-02-29 2017-09-08 Thin Film Electronics Asa Electronic device and method of making the same using surface mount technology and an anisotropic conductive adhesive useful in the method

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60140790A (en) * 1983-12-27 1985-07-25 ソニ−ケミカル株式会社 Coupling sheet
JPS60180189A (en) * 1984-10-29 1985-09-13 セイコーエプソン株式会社 Connecting structure for electric element
JPS60193353A (en) * 1984-03-15 1985-10-01 Hitachi Chem Co Ltd Connection of electronic parts

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60140790A (en) * 1983-12-27 1985-07-25 ソニ−ケミカル株式会社 Coupling sheet
JPS60193353A (en) * 1984-03-15 1985-10-01 Hitachi Chem Co Ltd Connection of electronic parts
JPS60180189A (en) * 1984-10-29 1985-09-13 セイコーエプソン株式会社 Connecting structure for electric element

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6411518B1 (en) 2000-02-01 2002-06-25 Mitsubishi Denki Kabushiki Kaisha High-density mounted device employing an adhesive sheet
WO2017149426A1 (en) * 2016-02-29 2017-09-08 Thin Film Electronics Asa Electronic device and method of making the same using surface mount technology and an anisotropic conductive adhesive useful in the method
CN109076706A (en) * 2016-02-29 2018-12-21 薄膜电子有限公司 Use the electronic device and its manufacturing method of anisotropy conductiving glue useful in surface mounting technique and this method

Also Published As

Publication number Publication date
JP2572570B2 (en) 1997-01-16

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