JPS6225382A - Image processor - Google Patents

Abstract

PURPOSE:To convert an image quickly with less memory capacity by providing a means holding boundary information on some area among a piece of image information and a means comparing and deciding whether or not a picture element lies in a designated area according to the boundary information held by the holding means. CONSTITUTION:Mask memories 12 and 13 have a bit length 14 each with respect to a subscan address 10a from a subscan counter 10, and hold boundary information on a mask area. A main scan address terminating clipping is stored in the mask memory 13, while a main scan address beginning to clip is stored in the mask memory 12. On the other hand, outputs 22 and 23 available from comparators 19 and 20 are inputted to a gate circuit 21, and are latched in a latch 15. Masking processing is executed with the aid of the output 15alpha '1' or '0' of the latch 15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image processing apparatus, and more particularly to an image processing apparatus capable of performing and reproducing masking processing to cut out an arbitrary area of image information.

[Prior Art] A conventional device of this type is equipped with a mask pattern memory having the same capacity as an image memory that stores a so-called bitmap mask pattern (cutout shape graphic pattern) corresponding to 0 pixel data and 1:1, Processing of image data - A device that reads this storage in synchronization with the transfer and performs predetermined processing.

(2) Apparatuses can be broadly classified into devices that use a method used in graphic display controllers, etc., in which an input image (memory) address is generated from an output image address by approximating a cutout mask pattern to a set of several rectangles.

Now, when extracting a part of the original image data shown in E7' An example will be explained in which a desired image, for example, the image shown in FIG. 2(C) is obtained.

In this case, the mask pattern for extraction or erasure is the third one.
This is the part 4 indicated by diagonal lines in the figure.

In the case of method (2), the mask pattern portions 4 in the original image area 5 shown in FIG. "1" is stored in the memory corresponding to the white area 5, and "0" is stored in the memory corresponding to the white area 5.The contents of this bitmap memory are read out in synchronization with the original image shown in FIG.
If "i" is valid, the image shown in FIG. 2 (CB) is obtained, and if °O'' is valid, the image shown in FIG. 2 (C) is obtained.

(FIG. 4 shows a block diagram of a conventional mask data generation unit that implements method D.

In FIG. 4, 8 is a bitmap memory, 10 is a sub-scanning counter, 11 is a main-scanning counter, 15 is a latch, and 1 is a latch.
6 is an image start signal, 17 is a main scanning start signal, and 18 is a pixel clock signal.

The sub-scanning counter 10 and the main-scanning counter 11 are reset by an image start signal 16 and a main-scanning start signal 17. The main scanning counter 11 is the pixel clock signal 1
8, and is counted up sequentially. Then, the main scanning address value indicated by the main scanning counter 11 of the bitmap memory 8 and the sub-scanning address indicated by the sub-scanning counter 1O (contents (mask bits) addressed by +ff are read out, latched in the latch 15, and outputted. be done.

Further, the sub-scanning counter 10 is incremented by the main-scanning start signal 17.

An example of holding the mask pattern shown in FIG. 3 in the conventional bitmap memory 8 is shown in the fifth field 11'.

In the bitmap memory 8, the sub-scanning address 10a
, and the memory cell selected by the main scanning address lla is read out. For example, if the content is °"0°', it is not copied;
If it is 1'', image copy processing is performed.

Next, the case where the images shown in FIGS. 2(B) and 2(C) are obtained by the method 2) will be explained.

In this case, a mask bit pattern with a one-to-one correspondence is not held; for example, region 4 in Figure 3 has a shape like a combination of triangles, but this is approximated to a set of rectangles and cut out. Process. FIG. 6 shows an example of a collection of approximate rectangular cutout patterns.

Here, the rectangular pattern is cut out using parameters (x,, Yt) and (x2) representing a set of rectangles.

Y2), (X3, Y3)...(xe, YB).

That is, the address (x, y) for the output pixel is (Xx≦
xkuX2) (Y1≦Y<Y2) or (X3≦X<
X4) and (Y3≦Y<Y4) or (X7≦X<X'a) Kak (Y7≦Y<Ye
), processing such as cutting out (or erasing) the pixel at the address position is performed. Image patterns processed using this method are shown in FIGS. 7(A) and 7(B). Here, FIG. 7(A) corresponds to FIG. 2(B), and FIG. 7(B) corresponds to FIG. 2(C).

Problems that E-issue 1 attempts to solve: In method ① mentioned above, a bitmap mask memory with the same capacity as the image data is required, and if the configuration is as shown in Fig. 5, 1024 dots x 1024 dots are required. In the case of dot pixels, a large capacity of 1 Mbit was required.

In addition, in the case of method (■), mask processing is performed as a rectangular figure, so there are restrictions on the shape of the cutout, and
It has been difficult to perform image conversion processing such as enlargement and rotation at the same time as this cutting processing. Moreover, it was inevitable that the cutout shape would be step-like.

c.Means for solving the problem] As a means for solving this problem, for example,
The image processing device of the embodiment shown in A has a mask memory 12.13 that holds boundary information of a partial area of image information, and pixels are Comparators 19 and 20 are provided to compare and determine whether or not the area is within the specified area.

[Operation] In the configuration shown in FIG. 1, the mask area can be determined according to the comparison results of the comparators 19 and 20.

Therefore, the memory capacity for holding mask information is small, and image conversion processing such as enlargement, reduction, rotation, etc. can be performed at high speed without any restriction on the cutout shape.

[Example] Hereinafter, an example according to the present invention will be described in detail with reference to the drawings.

"First Embodiment" FIG. 1 is a block diagram of an embodiment according to the present invention. In the figure, 10 is a sub-scanning counter, 11 is a main-scanning counter, and 15
16 is a latch, 16 is an image start signal, 17 is a main scanning start signal, and 18 is a pixel clock signal, which have the same structure as shown in FIG.

Furthermore, 12.13 is a mask memory A, B, 19 is a comparator A that compares the read value of the mask memory A12 and the main scanning counter 11 value, and 20 is a comparator A that compares the read value of the mask memory B13 and the main scanning counter 11 value. Comparator to compare 20.21
is a gate circuit.

FIG. 8 shows an example of the structure (held data) of the mask memories A and B (12, 13) for the masking pattern shown in FIG. 3.

Each sub-scanning address 10a from the sub-scanning counter 10 has a bit length of 14, and holds boundary information for the mask area. Mask memory A1
2 stores a main scanning address to start cutting out, and mask memory B13 stores a main scanning address to end cutting out. For example, the sub-scanning address "4" indicates that cutting begins at the main-scanning address "19" and ends at the main-scanning address "25". Assuming that the capacity of the memory containing the mask memory information of the bitmap shown in FIG. 5 is 1M bits, this boundary information can store similar mask information with a total capacity of 20 bits even if the bit length 14 is changed to 10 bits. , 50
1/1 capacity is sufficient.

In addition, an image obtained by resolving image information on A4 size paper at 16 tots/mm has 4752 x 3360 pixels, and the total amount of data in the hit map memory is about 16 Mbits, but according to this embodiment, the bit length per IJh is only 12 bits, and the total number of pixels is 4752 x 3360 pixels. In terms of capacity, only 114 bits is required. Therefore, the storage capacity is approximately 140 times smaller than that of a bitmap mask memory.

On the other hand, outputs 22 and 23, which are the results of the comparison by comparators A and B (19, 20), are input to the gate circuit 21, and the outputs are further latched into the latch 15. Here latch 1
The value latched to 5 is (mask memory A output value 12a) ≦ (main scanning counter value) Ka (mask memory B output value 13a) 〉 (main scanning counter value), which can also be expressed as follows. You can also do it.

(Cutout start main scan address) ≦ (main scan counter value) AND (cutout end main scan address) > (main scan counter value) Therefore, the masking process is executed by 1'' or °O''' of this latch 15 output 15a. This eliminates the need for a large-capacity bitmap memory, and can perform high-speed masking processing with quality comparable to that of a smooth bitmap mask memory with the addition of a small circuit configuration of two comparators and one gate circuit.

[Second Embodiment] Although the embodiment described above has the simplest configuration, other different embodiments according to the present invention will be described below.

In the embodiments shown in FIGS. 1 and 8, only one turn-on/off is allowed in the main scanning direction (for one sub-scanning), and it is not possible to deal with complex cut-out figures. .

For example, it is not possible to generate the same pattern as the bitmap mask shown in FIG.
This is because in the 5.26th position, on/off is repeated three times each.

= Generally, the configuration shown in FIG. 1 can only handle masks for convex areas. Therefore, in order to handle masks of arbitrary shapes, the mask memory is expanded by the necessary amount in the address direction and by 1 bit in the word length direction, as shown in FIGS. 10 and 11. The number of words equal to the number of times the on/off is repeated is assigned to the sub-scanning in which /off is repeated, and an extended 1 bit is assigned to indicate whether the subsequent word is for the - sub-scanning.

FIG. 10 is a block diagram of another embodiment according to the present invention, in which the same components as in FIG. 1 are given the same numbers.

The mask memory address counter 24 in FIG. 10 is different from the sub-scan counter 10 in FIG. 11 in that it outputs a mask memory address 24a that does not have a one-to-one correspondence with the sub-scan. In addition, as memories for mask data, along with mask memory A12 and mask memory B13, the subsequent mask memory A12
, and a flag bit memory 25 for distinguishing (determining) whether or not iJ of B13 are of the same sub-scanning. A gate circuit 28 is also added.

This mask memory A12. B13. FIG. 11 shows an example in which the mask pattern of the bitmap shown in FIG. 9 is stored in the flag bit memory 25.

When the mask memory address 24a is "24" or more γ, the mask area is turned on/off once, and the mask memory address counter 24 is incremented by one with each sub-scan (10a). However, main scanning counter 1
When the value of 1 becomes '0'' and the mask memory address 24a becomes the next 25'', each mask memory A12, B
13. The output of the flag bit memory 25 is "9°",
``18'', ``0'°.

Here, when the pixel clock signal 18 rises, the main scanning counter 11 is sequentially counted up. Then, when the value of the main scanning counter 11 becomes "9", the inputs A and B of the comparator AI9 become equal, and the output 22 becomes "1". At this time, the input A (13) of the comparator B20 is '13', input B is '9'°, and output 23 is '0'. Therefore, the output of the gate circuit 21 is '1°'. Therefore, the latch 15 is reset by the next pixel clock signal 18, the output becomes '1'°, and subsequent image data is permitted to be output.

Further, when the painting clock signal 18 reaches 8 times in a row, the value of the main scanning counter 11 becomes '18', and the comparator B2
Both inputs of 0 become equal and the output becomes "1". Therefore, both inputs of the gate circuit 21 become °l'', and at this time the gate circuit 28 is also satisfied, and the latch 15 is reset by the next pixel clock signal 18, notifying the end of masking.The mask memory address counter 24 also The count is increased by one. Thus, (f+ of the mask memory address counter 24 becomes '26', and the respective outputs of the mask memory A12, B13, and flag bit memory 25 are '19' and '21'.

″′ becomes 0.Then, in the same manner as above, the latch circuit 1
5 is "19'' of t scanning counter ll.

The mask memory address counter 24 is set/reset by the next pixel clock signal “21''.
is incremented.

Next, the value of the mask memory address counter 24 becomes '2.
7'', the corresponding mask memories A12, B13 .
Each of the flag bit memories 25 becomes 22°', 32'' and "1°', and the latch 15 stores the main scanning address value as "22°', 32'' and "1°'."
It is set at "22" and reset at "32", and the output is turned on/off accordingly, but the gate circuit 28 is not satisfied and the mask memory address counter 24 is not incremented. Then, it is incremented by 1 only when the next main scanning start signal 17 arrives.

The sub-scanning address lOa of this poem is "26", but the (force) of the mask memory address counter 24 is "28".
It becomes.

The above processing timing is shown in FIG.

By performing the above configuration and processing, the same effect as the bitmap mask shown in FIG. 9 can be obtained.

In the configuration of this embodiment, if the mask is turned on and off 134 times or less per sub-scan, complex masking processing can be executed with a smaller storage capacity than when a bitmap memory is used as the mask memory.

[Third Embodiment] Furthermore, in the above embodiments, since there is not a one-to-one correspondence between sub-scanning addresses and memory addresses, it is difficult to start processing from an arbitrary sub-scanning position. For this reason, FIG. 13 shows a configuration that allows the masking process to be easily executed from any sub-scanning position.

Components similar to those in FIG. 10 are given the same numbers.

In addition to the configuration shown in FIG. 10, a sub-scanning memory 29 having address values in one-to-one correspondence with sub-scanning is provided in front of the mask memory address counter 24, and the mask data is stored in two
It is memorized in two layers. The detailed structure of these mask data storage memories is shown in FIG.

The contents of the sub-scanning memory 29 are read out by the sub-scanning address 10 and inputted to the mask memory address counter 24, and taken into the mask memory address counter 24 by inputting the image start signal 16. The rest follows the same process as in the second embodiment shown in FIG. Therefore, mask data can be read out by any sub-scanning.

[Fourth Embodiment J In the mask pattern shown in FIG.
” has no mask part and the corresponding mask memory A12
．． The contents of B13 and flag bit memory 25 are also exactly the same throughout these areas. Also, although not shown in detail, the contents of each memory are exactly the same at sub-scanning addresses °"15" to °°21". Therefore, in order to reduce the storage capacity of this overlapping storage area, FIG. FIG. 15 shows an example in which the sub-scanning memory 29 shown in FIG. 15 is allowed to have duplicated storage contents in the sub-scanning direction, and is also allowed to be arranged out of ascending order. The circuit configuration in this case is shown in FIG. 16. In FIG. 16, a counter similar to the sub-scanning counter 10 shown in FIG. 1 is arranged in front of the sub-scanning memory 29 of FIG. 13.

Here, 30 is the sub-scanning start address. Since the contents of the sub-scanning memory 29 addressed by the sub-scanning counter 10 are loaded into the mask memory address counter 24 by the main-scanning start signal 17, the same mask memory A12. B13 and flag bit memory 25 are addressed.

Therefore, as shown in FIG. 15, for example, in the second and third embodiments, a memory capacity equivalent to the number of words in the sub-scanning memory was required, but this can be significantly reduced, and in the example shown in FIG. 25 words is enough. By the way, Figure 13,
In the embodiment shown in FIG. 14, a total capacity of 44 words was required.

In addition, by configuring as described above, when changing the mask pattern, it is only necessary to rewrite the stored contents of the mask memory, etc. in the corresponding sub-scanning direction, and even when the number of memory words increases, the data is not rewritten. Mask data can be added from the next address that does not exist.

Sub-scanning memory 29 when rewriting the mask pattern shown in FIG. 9 to create the mask pattern shown in FIG. 17
and mask memory A12. B13 and the contents of the flag bit memory 25 are shown in FIG.

Here, the contents of "14" to "21" in the sub-scanning memory 29 corresponding to the sub-scanning address whose mask pattern has been changed are rewritten, and the mask memories A12, B13. Each address of the flag bit memory 25 “25” to °“36”
All you have to do is input new mask pattern information. Therefore, the mask pattern can be changed to any desired mask pattern very easily and at high speed. When changing the mask pattern in the embodiment shown in FIG. 13, in addition to rewriting the sub-scanning memory,
Mask memory A12. B13. Flag bit memory 25
It was necessary to rewrite and shift everything after the start position of the change, which was time consuming and extremely troublesome.

All of the following four embodiments are capable of sending an image valid signal in synchronization with the image transferred to the raster, and are particularly useful for image processing devices that input input images as such raster data. It is valid.

In addition, since the memory capacity is extremely small, being less than a few sevenths of a minus, it is necessary to prepare the memory address value for the mask pattern down to the decimal point (or store the address value as a floating point number) in preparation for enlarging the image data. ), and when reading a normal mask pattern, it is read out as an address value with the decimal point cut off, and when image data, etc. is to be enlarged, this decimal point value can also be used as an interpolation parameter for the enlargement process. desirable.

Furthermore, in the sub-scanning direction, it is also possible to read out two adjacent sub-scans at a time and perform interpolation processing to obtain a smooth cutout boundary including the sub-scanning direction.

This can also be applied to the proposal of rotating two-dimensional data sent onto a rask while interpolating it using neighborhood calculations.

In this way, the part below the decimal point of the image memory read address is not used for accessing the image memory or mask memory in normal image processing, for example in enlargement processing! 4 adjacent images in the main scanning direction or 2 lines of image data in the sub-scanning direction are each read out a number of times according to the magnification, but at this time, the density of the image data with gradations is smoothly cropped using the value below the decimal point as a reference. Get boundaries. For example, if the number after the decimal point is n and 7, when doubling, the cutting boundary is the address n of the integer part, 7+0.7=(n+1),
4, and the position after the next scan can be set as the cutting boundary.

[Effects of the Invention] As explained above, according to the present invention, by providing an area generation circuit having a memory that holds the on/off position of the boundary area for each main scanning line, It is possible to achieve the same effect as equipped with a bitmap memory, at a much lower cost, and (2)!, IIJ
Processing when generating a cutout area can be sped up, and by having (:3) addresses below the decimal point, the cutout boundaries can be smoothed even when image scaling scans are performed, such as when enlarging image data. be able to.

[Brief explanation of the drawing]

Figure 751 is a block diagram of an embodiment according to the present invention, Figures 2 (A) to (C) are explanatory diagrams of masking processing, Figure 3 is a diagram showing a masking pattern, and Figure 4 is a diagram showing the conventional masking pattern. FIG. 5 is a diagram showing the storage of one masking pattern shown in FIG. 3 in the conventional bitmap memory, and FIG. 6 is a diagram showing the generation of a rectangular masking pattern for another conventional masking pattern shown in FIG. 3. , FIGS. 7A and 7B are diagrams showing an example of masking using a conventional rectangular pattern, FIG. 8 is a diagram showing an example of storing the masking pattern shown in FIG. 3 according to this embodiment, and FIG. 10, 13, and 16 are block diagrams of other embodiments according to the present invention. FIGS. 11, 14, and 15 are block diagrams of other embodiments according to the present invention. FIG. 12 is an operation timing chart of the present embodiment shown in FIG. 10; FIG. 17 is a diagram showing a storage example of the masking pattern shown in FIG. 9 as an example; FIG. FIG. 18 is a diagram showing a storage example of the masking pattern when changing to the masking pattern shown in FIG. 17 in the present embodiment shown in FIG. 16. In the figure, 10...sub-scanning counter, 11... main-scanning counter, 12, 13. ...Mask memory, 19°20
. . Comparator, 24 . . . Mask memory address counter, 25 . . . Flag bit memory, 29 . . . Sub-scanning memory. Figure 1 '41・y 1 da 1/' Flo Socro Figure 2 La (A) (B) @ fence, X <J-ゝW-INl+J”-°
,9. ri"-o('-..., Bega N- to special Ran Figure 14 Mask mesori cold [Figure 15 Mask X mori Sui A° field Figure 18 Mask

Claims (3)

[Claims] (1) A designation means for designating a partial area of image information, and an image processing means for performing image processing on the image information of the area designated by the designation means, and the designation means performs image processing for each main scanning line of the image information. An image processing apparatus characterized by retaining boundary information of the area and specifying an area based on the retained information. (2) Claims characterized in that the specifying means is provided with a hierarchical memory, the former memory holds the address value of the latter memory, and is capable of holding a plurality of pieces of arbitrary boundary information for each main scanning line. The image processing device according to item 1. (3) The boundary information held by the specifying means is an area start main scanning address and an area end main scanning address, and the main scanning address information has a decimal part. The image processing device according to item 2.