JPS6225358A - Varying device for interruption request level - Google Patents

Abstract

PURPOSE:To accept a request below the level of interruption processing which is caused currently and to improve a processing speed by increasing the level an interruption request to a central processor at constant intervals of time. CONSTITUTION:An external interruption request signal 5 is latched by a latch 1 and inputted as a decoding start signal to a decoder 2. The decoder 2 already inputs interruption level data 8 and an interruption request signal 7 having a preset level is outputted to a system bus 4. The interruption request signal 7 is inputted to a CPU 10 and then a latch reset signal 9 is sent out to reset the latch 1. The interruption level data 8 is varied by an interruption level data varying part 3 at constant intervals of time to allow an interruption request to be accepted.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to an apparatus for processing interrupt requests to a central processing unit, and is particularly suitable for microcomputer systems in which there are many causes of interrupt requests.

[Background of the invention]

In the conventional processing for an interrupt request, if an interrupt request lower than the level of the interrupt processing currently being executed by the central processing unit occurs, processing is performed after waiting for the end of the current processing.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an interrupt level variable device that is inexpensive with an extremely simple hardware configuration and that can reduce the reduction in system processing speed due to differences in interrupt request levels.

[Summary of the invention]

The interrupt request level to the central processing unit can be increased at regular intervals, and even if the central processing unit is executing interrupt processing at a higher level than the currently requested interrupt request level, it will be accepted. I made it so that it could be done.

[Embodiments of the invention]

An embodiment of the present invention will be described below with reference to FIG. External interrupt request signal 5 generated by an external factor is latched by latch 1 and then input to decoder 2 as decoding start signal 6. Interrupt level data 8 is input to decoder 2. An interrupt request signal 7 at a preset level is output to the system bus 4. This interrupt request signal 7 is input to the central processing bag @10, and when the interrupt is accepted, the latch is released by the latch release signal 9, and the output of the interrupt request signal 7 is stopped. The above is an explanation of what happens when a normal interrupt occurs.

However, the next interrupt processing is at a higher level than the level requested by the central processing unit 10 with the interrupt request signal 7.

Let's explain what happens when you run . In this case, the interrupt level data 8 is varied at regular intervals in the interrupt level data variable section 3, and accordingly the interrupt request signal 7 is also varied so that the interrupt request can be accepted.

Next, an example of the circuit of the interrupt level data variable section 3 will be explained with reference to FIG. When the external interrupt request signal 5 is active (logic z, #) and the interrupt confirmation signal 34 is inactive (logic h''), the decoder 23 becomes operational and according to the preset interrupt level data 8, Interrupt request signal 2
Any one of 4 to 60 is output. When these interrupt request signals are accepted by the central processing unit, the interrupt confirmation signal 34 becomes active (logic 1L'), the operation of the decoder 23 is prohibited, and the output of the interrupt request signal is stopped. Next, a case will be described in which the central processing unit is executing interrupt processing at a higher level than the level requested by the interrupt request signal. The interrupt confirmation signal 34 is inactive (logic 'H''), and any of the interrupt confirmation signals 24 to 3Q is output. Even if a certain period of time is exceeded in this state, If the interrupt confirmation signal 34 does not become active (logic 1L''), the counter 22 is operated by the periodically generated clock pulse 35, changes the value of the interrupt level data 8, and outputs the interrupt request signals 24 to 30. I will raise it to a higher rank in order. As a result, when the interrupt request signal is accepted by the central processing unit, the interrupt confirmation signal 34 becomes active (logic 'L').
Therefore, the output of the interrupt request signal is stopped.0 The monostable multivibrator 21 determines the timing to preset the initial interrupt level data 31 in the counter 22 when the interrupt confirmation signal 34 becomes active (logic 1L:). It is meant to occur.

According to this embodiment, by using the counter 22, the interrupt request level can be calculated using extremely simple hardware. This has the effect that it is possible to configure a variable device, and that it becomes easier to accept processes with low interrupt request levels.

〔Effect of the invention〕

According to the present invention, even if an interrupt request is received that is lower than the level of the interrupt processing currently being executed, the interrupt request is reliably accepted, thereby improving the processing speed of the entire system.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an interrupt level variable device showing an embodiment of the present invention, and FIG. 2 is a circuit diagram of the interrupt level data variable section of FIG. 1. 1...Latch 2...Decoder 3...Interrupt level data variable unit 4...System bus 5...External interrupt request signal 6...Decode start signal 7...Interrupt request signal 8... Interrupt level data 9... Latch release signal 10... Central processing unit 21... Monostable multivibrator 22... Counter 25... Decoder 24... Interrupt request signal 1 25 ...Interrupt request signal 2 26...Interrupt request signal 6 27...Interrupt request signal 4 28...Interrupt request signal 5 29...Interrupt request signal 6 50...Interrupt Request signal 7 31...Initial interrupt level data 32...Reset signal 33...Interrupt generation signal 34...Interrupt confirmation signal 35...Clock pulse 1゜,

Claims (1)

[Claims] Level changing means for changing the level of an interrupt request over time in an information processing device comprising a central processing unit and a plurality of peripheral devices capable of generating interrupt requests of different levels to the central processing unit. An interrupt request level variable device characterized by being provided.