JPS6225335A - Sequencer - Google Patents

Sequencer

Info

Publication number
JPS6225335A
JPS6225335A JP16436685A JP16436685A JPS6225335A JP S6225335 A JPS6225335 A JP S6225335A JP 16436685 A JP16436685 A JP 16436685A JP 16436685 A JP16436685 A JP 16436685A JP S6225335 A JPS6225335 A JP S6225335A
Authority
JP
Japan
Prior art keywords
cpu
eeprom
output
sequencer
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP16436685A
Other languages
Japanese (ja)
Inventor
Kazuhiko Mitsuo
満尾 一彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Electric Works Co Ltd
Original Assignee
Matsushita Electric Works Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Works Ltd filed Critical Matsushita Electric Works Ltd
Priority to JP16436685A priority Critical patent/JPS6225335A/en
Publication of JPS6225335A publication Critical patent/JPS6225335A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE:To prevent an EEPROM from being rewritten owing to the runaway of a CPU by allowing a runaway detecting means to detect access to an external ROM for sequence program storage not being attained at a constant period by using the EEPROM. CONSTITUTION:A write control circuit 7 triggers periodically a retriggerable monostable multivibrator 9 which detects a runaway with an output signal from a decoder 8 by the addressing of a CPU 1 and also inputs the Q output of the monostable multivibrator 9 and a write signal WT from the CPU 1 to a OR gate 10 to place the EEPROM 6 in a write enable state. When access from the CPU 1 is cased owing to the runaway while the write signal WT is generated and then the Q output of the monostable multivibrator 9 is inverted a specific time later, a write enable WE is at L from the generation of the write signal WT to the inversion. The EEPROM 6 is not rewritten when this L period is within the time required for the writing of the EEPROM 6.

Description

【発明の詳細な説明】 [技術分野] 本発明は、シーケンサに関するものである。[Detailed description of the invention] [Technical field] The present invention relates to a sequencer.

[背景技術] 一般的にシーケンサを動作させるシーケンスプログラム
は、シーケンサ本体に内蔵されているRAMからなるメ
モリに保存するのが通常な方法であるが、RAMではノ
イズによって書き込み内容が変化する恐れがあり、又揮
発性記憶素子であるためバッテリーバックアップが必要
で、更にラインが変わると、プログラムの変更が大変で
あるという問題があるため、RAMの代わりにEPRO
Mで運転する方法がよく用いられる。しかしEPROM
にプログラムを書き込むための高電圧を通常シーケンサ
は備えておらず、直接には書き込めない。そこで一度プ
ログラムをカセットテープに落とすか、EEPROM(
5V電圧で書き込み可能)に書き込むかして、EPRO
Mに書き込みができる電圧を有するROMライタにその
内容(カセットテープ、E 、E P ROMから)を
取り込み、その後EPROMに書く作業をしなければな
らなかった。
[Background technology] Generally speaking, the sequence program that operates a sequencer is usually stored in a memory consisting of RAM built into the sequencer itself, but with RAM, there is a risk that the written contents may change due to noise. Also, since it is a volatile memory element, battery backup is required, and when the line changes, it is difficult to change the program. Therefore, EPRO is used instead of RAM.
The method of driving with M is often used. But EPROM
Normally, sequencers do not have the high voltage needed to write programs to them, so they cannot be written directly. Therefore, you should either transfer the program to a cassette tape or use an EEPROM (
EPRO
The contents (from the cassette tape, E, or EPROM) had to be loaded into a ROM writer with a voltage that would allow writing to the M, and then written to the EPROM.

しかしカセットテープでは手間がかかるため、EEPR
OMが特に利用されている。ここでEEPROMは不揮
発性であり、5■電圧で再き込み可能であるにもかかわ
らず、EPROMの代わりに使用はされてはいなかった
However, since cassette tapes are time-consuming, EEPR
OM is particularly utilized. Here, although EEPROM is non-volatile and can be rewritten with 5 volts, it has not been used in place of EPROM.

つまりシーケンサで使用する5■電圧で書き込み可能で
あるから、シーケンサの暴走時に書き込み信号(W T
 )が制御演算用のCPUから出力され、シーケンスプ
ログラムが破ij!される恐れがあったからである。
In other words, since writing is possible with the 5-volt voltage used in the sequencer, the write signal (W T
) is output from the control calculation CPU, and the sequence program is broken. This is because there was a fear that he would be

[発明の目的] 本発明は上述の問題点に鑑みて為されたもので、その目
的とするところは、CP Uの暴走時にEEF ROM
 !:書き込まれているシーケンスプログラムが破壊さ
れるのを防ぎ、シーケンサ内蔵の電源により書き込み可
能なEEPROMを用いて、プログラム保存時の作業の
煩わしさを無くしたシーケンサを提供するにある。
[Object of the Invention] The present invention has been made in view of the above-mentioned problems, and its purpose is to protect the EEF ROM when the CPU runs out of control.
! : To provide a sequencer which prevents the written sequence program from being destroyed and eliminates the troublesome work of saving the program by using an EEPROM which can be written by the sequencer's built-in power supply.

[発明の開示] 本発明は制御演算用のCPUと、CPUの制御演算用の
プログラム用、処理用のメモリと、周辺装置とからなり
、シーケンスプログラムを外部に接続したROMで動作
可能としたシーケンサにおいて、シーケンスプログラム
保存用の上記ROMをシーケンサ内蔵の電源電圧で書き
込み可能なEEPROMを使用し、上記CPUから一定
周期でアクセスされ、該アクセスが所定時間以上無くな
れば出力を反転する暴走検出手段の出力と、CPUから
出力される書き込み信号との一致出力で上記EEPRO
Mをイネーブルする書き込み制御回路を備え、上記所定
時間をEEPRO,Mの書き込みに必要な時間以下とす
ることを特徴とするものである。
[Disclosure of the Invention] The present invention provides a sequencer that is composed of a CPU for control calculations, a program for control calculations of the CPU, a memory for processing, and a peripheral device, and is capable of operating a sequence program on an externally connected ROM. The ROM for storing the sequence program is an EEPROM that can be written using the power supply voltage built into the sequencer, and is accessed by the CPU at a constant cycle, and the output of the runaway detection means is inverted if the access is not performed for a predetermined period of time or more. and the write signal output from the CPU, the above EEPRO
The present invention is characterized in that it includes a write control circuit that enables M, and the predetermined time is set to be less than or equal to the time required to write EEPRO,M.

以下実施例により本発明を説明する。The present invention will be explained below with reference to Examples.

及(几 第1図は実施例を示しており、演算処理用のCPU1に
はデータバス2と、アドレスバス3と、制御バスとを介
して制御演算用の動作プログラムを書き込んだROM4
と、処理用のRAM5とを接続するとともに、外部に設
けたソケットなどに上りEEPROM6を接続しである
。EEPROM6はシーケンサに使用する5V?+!圧
で書き込み可能なものであり、CPUIからの読出し信
号RDにより書き込んだプログラムが読出され、また書
き込み信号WTが書込イネーブル端子WEに入力される
とアドレスバス3を介してアクセスされたアドレスに、
データバス2から送られてきたデータを書き込むのであ
る。
(几Figure 1 shows an embodiment. A CPU 1 for arithmetic processing is connected to a ROM 4 in which an operating program for control calculations is written via a data bus 2, an address bus 3, and a control bus.
and a processing RAM 5, and an upstream EEPROM 6 is connected to a socket provided externally. Is EEPROM6 5V used for sequencer? +! The written program is read out by the read signal RD from the CPUI, and when the write signal WT is input to the write enable terminal WE, the address accessed via the address bus 3 is written.
The data sent from data bus 2 is written.

書き込み制御回路7はcpu iが暴走したときニ誤っ
てEEPROMG内のシーケンスプログラムが書き替え
られて破壊されるのを防止するためのものであり、正常
時にはCPUIにより周期的にアドレスされ、デフーグ
8からの出力信号により暴走検出手段であるリトリがマ
ブル型のワンショットマルチバイブレータ9を周期的に
トリがするとともに、該ワンショットマルチパイプレー
ク9のQ出力とCPUIからの書き込み信号WTとをオ
アデート10に入力して共に”L”の時にEEPROM
6を曾き込みイネーブルとするようになっている。ここ
でワンショットマルチバイブレータ9は抵抗Rとコンデ
ンサCとからなる酔♀於回路により、最後のトリ〃があ
った後にQ出力を反転させるものである。
The write control circuit 7 is intended to prevent the sequence program in the EEPROMG from being accidentally rewritten and destroyed when the CPU i goes out of control.During normal operation, it is periodically addressed by the CPU and is read from the defogger 8. The runaway detecting means periodically trigs the one-shot multi-vibrator 9 based on the output signal of the one-shot multi-pipe rake 9, and outputs the Q output of the one-shot multi-pipe rake 9 and the write signal WT from the CPU to the OR date 10. EEPROM when input and both are “L”
6 is loaded and enabled. Here, the one-shot multivibrator 9 inverts the Q output after the last tri-vibrator by means of an inverter circuit consisting of a resistor R and a capacitor C.

しかして、通常においてはワンショットマルチバイブレ
ータ9はQ出力が反転するまえにトリがが与えられ、そ
のQ出力を”I、″のままとする。したがってCPU 
1から書き込み信号WTを出力すると、オアデー)10
の出力がL′となり、EEPROM6は書き込み状態に
設定され、内容を書き替える。
Normally, the one-shot multivibrator 9 is given a signal before the Q output is inverted, and the Q output remains as "I,". Therefore the CPU
When the write signal WT is output from 1 to 10
The output becomes L', the EEPROM 6 is set to the write state, and the contents are rewritten.

次にCPU1が暴走し、最悪のケースとして第2図(、
)に示すようにCPUIから書き込み信号WTが発生し
、また暴走によってCPU 1からのアクセスがなくな
り、ワンショットマルチバイブレータ9のQ出力が所定
時間後に第2図(b)に示すように反転する。従って書
き込み信号WTの発生からQ出力が反転するまでの間書
き込みイネーブル端子WEは”L″′となる。ここでこ
の″L″期間twが、EEPROM6の書き込み時に必
要とする時間以内であれば、EEPROM6は内容を書
き替えることが出来ず、従前のシーケンスプログラムを
保存する。つまり本実施例ではワンショットマルチバイ
ブレータ9の最終のトリガを受けてからQ出力を反転さ
せるまでの所定時間がこの書き込みに必要とする時間を
越えないように、上記時定数回路を設定しており、上述
の暴走時のシーケンスプログラムの保存を可能とする。
Next, CPU1 goes out of control, and in the worst case, Figure 2 (,
), the write signal WT is generated from the CPU 1, and there is no access from the CPU 1 due to runaway, and the Q output of the one-shot multivibrator 9 is inverted after a predetermined time as shown in FIG. 2(b). Therefore, the write enable terminal WE becomes "L'' from the generation of the write signal WT until the Q output is inverted. Here, if this "L" period tw is within the time required for writing into the EEPROM 6, the contents of the EEPROM 6 cannot be rewritten and the previous sequence program is saved. In other words, in this embodiment, the time constant circuit is set so that the predetermined time from receiving the final trigger of the one-shot multivibrator 9 to inverting the Q output does not exceed the time required for this writing. , it is possible to save the sequence program at the time of the above-mentioned runaway.

[発明の効果1 本発明は制御演算用のCPUと、CPUの制御演算用の
プログラム用、処理用のメモリと、周辺装置とからなり
、シーケンスプログラムを外部に接続したROMで動作
可能としたシーケンサにおいて、シーケンスプログラム
保存用の上記ROMをシーケンサ内蔵の電源電圧で書き
込み可能なEEPROMを使用し、上記CPUから一定
周期でアクセスされ、該アクセスが所定時間以上無くな
れば出力を反転する暴走検出手段の出力と、CP、11 Uから出力される書き込み信号との一致出力で上記EE
PROMをイネーブルする書き込み制御回路を備え、上
記所定時間をEEPROMの書き込みに必要な時間以下
とするので、CPUの暴走が生じてもE E F RO
Mの内容の書き替えが起きず、そのためシーケンサ内蔵
の電源電圧で書き替え可能なEEPROMの使用を可能
とし、結果、書き込み作業の簡略化が図れるという効果
を奏する。
[Effects of the Invention 1] The present invention provides a sequencer that is composed of a CPU for control calculations, a program for control calculations of the CPU, a memory for processing, and a peripheral device, and is capable of operating a sequence program using an externally connected ROM. The ROM for storing the sequence program is an EEPROM that can be written using the power supply voltage built into the sequencer, and is accessed by the CPU at a constant cycle, and the output of the runaway detection means is inverted if the access is not performed for a predetermined period of time or more. and the write signal output from CP and 11U, and the above EE is output.
It is equipped with a write control circuit that enables the PROM, and the predetermined time is set to less than the time required for writing to the EEPROM, so even if the CPU runs out of control, E
Since the contents of M are not rewritten, it is possible to use an EEPROM that can be rewritten using the power supply voltage built into the sequencer, and as a result, the writing operation can be simplified.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明の実施例の回路図、!n2図は同上の動
作説明用のタイムチャートであり、1はCPU、4はR
OM、5はRAM、6はEEPROM、7は書き込み制
御回路、8はヂフーグ、5〕はワンショットマルチバイ
ブレータである。 代理人 弁理士 石 1)侵 七 手続r山王8(自発) 昭和60年10月26日 持J′l−庁長官殿 昭用60年特許願第164366号 2 発明の名称 ジーゲンサ 3、浦正をする者 を件との関係  特許出願人 住 所 大阪府門真市大字門真1048番地名称<58
3)松下電工株式会社 代表者  藤  井  貞  夫 ・1 代理人 郵便番号 530 住 所 大阪市北区梅田1丁目12番17号5 補正命
令の目付  自 発 6 浦正により増加する発明の数 なし7、補正の対象
  明細書 8 補正の内容
FIG. 1 is a circuit diagram of an embodiment of the present invention. Figure n2 is a time chart for explaining the operation of the same as above, 1 is the CPU, 4 is the R
OM, 5 is a RAM, 6 is an EEPROM, 7 is a write control circuit, 8 is a difugu, and 5] is a one-shot multivibrator. Agent Patent Attorney Ishi 1) Infringement 7 Proceedings r Sanno 8 (spontaneous) October 26, 1985 J'l - Director General of the Agency 1960 Patent Application No. 164366 2 Name of the invention Siegensa 3, Urasa Relationship to the matter Patent applicant address 1048 Kadoma, Kadoma City, Osaka Name <58
3) Matsushita Electric Works Co., Ltd. Representative: Sadao Fujii 1 Agent postal code: 530 Address: 1-12-17-17 Umeda, Kita-ku, Osaka 5 Weight of amendment order Voluntary issue: 6 Number of inventions to be increased by Urasa: None: 7 , Subject of amendment Description 8 Contents of amendment

Claims (1)

【特許請求の範囲】[Claims] (1)制御演算用のCPUと、CPUの制御演算用のプ
ログラム用、処理用のメモリと、周辺装置とからなり、
シーケンスプログラムを外部に接続したROMで動作可
能としたシーケンサにおいて、シーケンスプログラム保
存用の上記ROMをシーケンサ内蔵の電源電圧で書き込
み可能なEEPROMを使用し、上記CPUから一定周
期でアクセスされ、該アクセスが所定時間以上無くなれ
ば出力を反転する暴走検出手段の出力と、CPUから出
力される書き込み信号との一致出力で上記EEPROM
をイネーブルする書き込み制御回路を備え、上記所定時
間をEEPROMの書き込みに必要な時間以下とするこ
とを特徴とするシーケンサ。
(1) Consists of a CPU for control calculations, a program for CPU control calculations, a memory for processing, and peripheral devices,
In a sequencer that can operate a sequence program using an externally connected ROM, the ROM used to store the sequence program uses an EEPROM that can be written to using the power supply voltage built into the sequencer, and is accessed by the CPU at regular intervals. The above-mentioned EEPROM is activated when the output of the runaway detection means, which inverts the output when the output is lost for a predetermined period of time, coincides with the write signal output from the CPU.
1. A sequencer comprising a write control circuit for enabling said sequencer, said predetermined time being less than or equal to the time required for writing into an EEPROM.
JP16436685A 1985-07-25 1985-07-25 Sequencer Pending JPS6225335A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP16436685A JPS6225335A (en) 1985-07-25 1985-07-25 Sequencer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP16436685A JPS6225335A (en) 1985-07-25 1985-07-25 Sequencer

Publications (1)

Publication Number Publication Date
JPS6225335A true JPS6225335A (en) 1987-02-03

Family

ID=15791775

Family Applications (1)

Application Number Title Priority Date Filing Date
JP16436685A Pending JPS6225335A (en) 1985-07-25 1985-07-25 Sequencer

Country Status (1)

Country Link
JP (1) JPS6225335A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1001341A1 (en) * 1998-11-13 2000-05-17 Nec Corporation Method and apparatus for controlling rewrite of a flash EEPROM in a microcomputer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP1001341A1 (en) * 1998-11-13 2000-05-17 Nec Corporation Method and apparatus for controlling rewrite of a flash EEPROM in a microcomputer

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