JPS6225293B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a glitch prevention circuit for a digital-to-analog converter.

In a digital-to-analog conversion device, when a digital signal changes from "0, 1, 1, ... 1" to "1, 0, 0, ... 0", or from "1, 0, 0, ... 0", A phenomenon in which the analog signal level temporarily drops to the level of "0, 0, 0... 0" when changing to "0, 1, 1... 1",
It is known that so-called glitches occur. The cause of this glitch is the time difference between the rise and fall of the digital signal. In general, a digital element connected to the input side of a digital-to-analog converter has a finite rise and fall time, and the rise time is usually faster than the rise time. For this reason, when the signal goes up and down the midpoint of the level, for example, "1, 0, 0,...0"
When changing from to a small value, it is originally “0, 1,
A signal that becomes "1, . . . 1" temporarily causes a state of "0, 0, 0, . . . 0" on the way. For this reason, the analog output signal, which should be lower than the midpoint by 1/2 ⁿ -1 (where n is the number of bits), temporarily drops to the zero point. This kind of phenomenon, or glitch, changes from "0, 1, 1...1" to "1,
0,0...0'' occurs similarly. Also,
The above-mentioned glitch is the largest when the MSB (most significant bit) switches, and is half as large when the "MSB-1" bit switches, and the lower the bit, the less its influence. Furthermore, glitches become an auditory problem when the output level is small, and especially when the output level converges to a central level, large noises occur.

However, in order to eliminate the influence of the glitch, conventionally, as shown in Fig. 1, a D/A (digital
A sample hold circuit 2 is provided on the output side of the D/A converter 1 to output an analog signal when the output of the D/A converter 1 reaches a steady state. The sample and hold circuit 2 has a configuration in which a switching element 5 is connected between two stages of operational amplifiers 3 and 4, and a capacitor 6 is provided between the signal line and the ground, so that the output of the D/A converter 1 is in a steady state. When the analog signal reaches the capacitor 6, the switching element 5 is driven to close by the sampling pulse, and the analog signal is held in the capacitor 6. FIG. 2 shows the glitch removal operation described above, in which a shows the output signal waveform of the D/A converter 1, and b shows the output signal waveform of the D/A converter 1.
1 shows a sampling pulse, and c in the same figure shows an output waveform of the sample and hold circuit 2. By sampling the glitch-containing analog signal output from the D/A converter 1 in the sample-and-hold circuit 2 in this manner, glitches can be removed as shown in FIG. 2c.

However, in the above-mentioned conventional method for removing glitches using the sample and hold circuit 2, operational amplifiers 3, 4, etc. are required, resulting in problems such as a complicated circuit configuration and a very high cost. be. Furthermore, since the switching element 5 must be controlled on and off using sampling pulses, the configuration becomes complicated from this point as well. Furthermore, the sample-and-hold circuit 2 may also cause a field-through phenomenon or a droop phenomenon, resulting in various problems.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a glitch prevention circuit for a digital-to-analog converter that can reliably prevent the occurrence of glitches with a simple configuration.

An embodiment of the present invention will be described below with reference to the drawings. In Figure 3, 11 indicates the number of output bits, for example.
This is a 12-bit digital signal output device, and all the bits of the digital signal are connected to an inverter circuit 12 that performs a delay operation, for example, with respect to the falling edge of the signal.
and an inverter circuit 1 that performs normal signal inversion operation.
3 to a D/A (digital/analog) converter 14.

In the first stage inverter circuit 12, the inverters provided corresponding to each input bit are C-MOS transistors (complementary MOS transistors) as shown in FIG.
A variable resistor 15 is commonly provided at the power supply terminals of the transistors 12a and 12b. The C-MOS inverter shown in FIG. 4 has an input signal IN of "1" as shown in FIG. 5a.
When the voltage falls from zero to "0", the MOS transistor 12a is turned on and the MOS transistor 12b is turned off. As a result, charging of the capacitor C formed by the capacitance of the circuit is started via the transistor 12a, but since the variable resistor 15 is interposed in series in the charging circuit, the charging time constant is It's big and takes a long time to charge.
Therefore, the rise of the output signal OUT is delayed as shown in FIG. 5b. Further, when the input signal rises from "0" to "1", the transistor 12a is turned off and the transistor 12b is turned on, and the charge in the capacitor C is discharged via the transistor 12b. In this case, only the transistor 12b is interposed in the discharge path, the discharge time constant is very small, and the capacitor C is discharged instantaneously. As a result, the output signal
The falling edge of OUT is not delayed and corresponds to the input signal IN. In this way, C-
When an input signal is applied to the MOS inverter, the MOS inverter performs a delayed output operation when the input signal falls, and performs an output operation proportional to the input when the input signal rises.

Next, the operation of the present invention configured as described above will be explained. The digital signal output from the digital signal output device 11 has a falling time faster than a rising time, which causes glitches. By intervening, the rise time and fall time of the digital signal at the input end to the D/A converter 14 become equal, and the occurrence of glitches is prevented. For example, the digital signal output from the digital signal output device 11 is "1, 0, 0, . . . at point a in FIG.
0" to "0, 1, 1,...1", that is, the most significant bit MSB shown in Figure 6a
is "1" to "0", and the other 2 to "0" shown in Figure 6b
Assuming that the LSB (least significant bit) changes from “0” to “1”, the most significant bit MSB completes the fall while the other bits 2 to LSB are still at the “0” level and changes to “0”. “It becomes a level. As a result,
The output of the digital signal output device 11 is temporarily in the state of "0, 0, 0, . . . 0". However, the most significant bit MSB is
As shown in Figure c, it is delayed at the same time as the inversion. In this case, the delay time in the inverter circuit 12 is
The variable resistor 1 is set in advance so as to match the rise time of the signal output from the digital signal output device 11.
Adjust according to 5. On the other hand, when the 2nd to LSB bits output from the digital signal output device 11 rise from "0" to "1", the 6th
As shown in FIG. d, the signal is inverted by the inverter circuit 12 without delay. As a result, in the digital signal output from the inverter circuit 12, the rise time of the most significant bit MSB matches the fall time of the other 2 to LSB bits. and,
The output of the inverter 12 is inverted by an inverter circuit 13, returned to the original signal level as shown in FIG. 6e and f, and sent to the D/A converter 14. In this way, when the digital signal output from the digital signal output device 11 changes from "1, 0, 0, ... 0" to "0, 1, 1, ... 1", only the most significant bit is connected to the inverter circuit. delayed by 12;
Its falling edge coincides with the rising edge of other bits. As a result, an all "0" state will not occur at the input point of the D/A converter 14, and glitches will be prevented from occurring.

Further, the digital signal output from the digital signal output device 11 changes from "0, 1, 1, ... 1" to "1, 0, 0, ... 0" as shown at point b in FIG.
When the bit changes to , the other bits 2 to LSB except the most significant bit MSB are delayed by the inverter circuit 12, and the rise time and fall time of the most significant bit MSB and the other bits 2 to LSB coincide. As a result, as in the case described above, the all "0" state does not occur at the input point of the D/A converter 12, and glitches are prevented from occurring.

Note that in the above embodiment, the case where the fall time of the digital signal output from the digital signal output device 11 is faster than the rise time is shown.
Even if the time difference between falling and rising times is reversed, it can be implemented in the same way.

As described above, according to the present invention, an inverter circuit is used to delay the rise time or fall time of a digital signal so that the rise time and fall time match, so that an expensive operational amplifier or the like is not required. This makes it possible to reliably prevent the occurrence of glitches with a simple configuration and to reduce costs. Since the rise time or fall time of the digital signal is delayed by a C-MOS inverter, the number of components is small, and multiple bits can be commonly controlled by one variable resistor. The resistance becomes constant, and the influence on analog signals can be reduced.

[Brief explanation of the drawing]

Fig. 1 is a block diagram showing a glitch prevention circuit of a conventional digital-to-analog converter, and Fig. 2 a to c
1 is a signal waveform diagram for explaining the operation of FIG. 1, FIG. 3 is a circuit configuration diagram showing an embodiment of the present invention, and FIG.
This figure shows the detailed configuration of the inverter circuit in FIG. 3, FIG. 5 shows the input/output signal waveforms of the inverter circuit shown in FIG. 4, and FIG. 6 shows a diagram for explaining the operation of FIG. It is a signal waveform diagram. 12, 13... Inverter circuit, D/A (digital/analog) converter, 15... Variable resistor.

Claims (1)

[Scope of Claims] 1. A first inverter circuit that delays the rise time or fall time of a digital signal input to a digital-to-analog converter to match the rise time and fall time of the digital signal; The second inverter circuit inverts the digital signal output from the first inverter circuit, returns it to its original signal level, and outputs it to the digital-to-analog converter. A glitch prevention circuit for a digital-to-analog converter, characterized in that it prevents the occurrence of glitches due to time differences. 2. The glitch prevention circuit for a digital-to-analog converter according to claim 1, wherein the first inverter circuit is constituted by a C-MOS transistor.