JPS62252211A - Data latch circuit - Google Patents

Abstract

PURPOSE:To accurately prevent a through current flow, by providing a signal generation circuit that puts an analog switch at an off-state. CONSTITUTION:An analog switch 21 consisting of an NMOS controlled by a control signal phi, and a PMOS controlled by a control signal, the inverse of phi, is provided. By setting an output signal Q at an H-level, the control signal phiis set at an L-level, and the control signal, the inverse of phi, at the H-level, regardless of the H-level, or the L-level of a clock signal CK, and the analog switch 21 is turned off. Therefore, no through current is permitted to flow. Also, by setting the output signal Q of the latch circuit at the L-level, the analog switch 21 is turned off, thereby, the through current is prevented from running.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention provides an asynchronous set, reset or set
This relates to a data latch circuit with reset.

(Prior art) Conventionally, as a technology in this field, Japanese Patent Application Laid-Open No. 0-7
There was one described in Publication No. 0817. The configuration will be explained below using figures.

FIG. 2 is a circuit diagram showing a configuration example of a conventional data latch circuit with non-identical wI type set φ reset.

This data latch circuit consists of complementary MOS transistors (
There is an analog switch (also referred to as a transfer gate) 1 consisting of a CMOS inverter 2 and an OS inverter 3 for switch feedback on the output side of the analog switch 1. N-channel type M for connecting and setting
O3l transistor (hereinafter simply referred to as NM (Is or ll)
) 4 and reset P-channel MOS
A transistor (hereinafter simply referred to as PMOS or MOS) 5 is connected. Furthermore, an inverter consisting of a MOS transistor (hereinafter simply referred to as MOS) 6.7 for inputting the data signal DT is connected to the input side of the analog switch l, and a through-hole is connected between No. 5e and the power supply voltage vDD. MOS8 for current interruption, also the MO97
A MOS 9 for cut-off of through current is connected between the ground potential and the ground potential. Note that 10 in FIG. 2 is
Inverter for inverting clock signal GK, 11.12 is OS inverter for output C, S is set signal, ■ is inverted reset signal, Q is output signal, V is inverted output signal, A is latch circuit input side node (1tc standard)
.

It! 2 is a through current.

Next, the operation will be explained.

An analog switch 1 is turned on in synchronization with the rise of a data latch clock signal GK, data DT is input through the analog switch 1, and the data signal DT is latched by a latch circuit including inverters 2 and 3. When the set signal S is input manually as an asynchronous forced input signal, M
When the OS4 is turned on and the potential of the node A becomes the ground potential, and the output signal Q is set to H level through the inverter 11, even if the analog switch l is in the on state, the reset signal S When MOS8 is off, the current path from power supply voltage V to D+ to OS8, 8 to analog switch 1 to MOS4 is cut off, so the through current 11 is generated despite the H or L level of data signal DT. can prevent the flow of Similarly, when inputting the inverted reset signal ■, MOS5 is turned on and the output signal Q is reset to L level.
Since MOS9 is turned off, power supply voltage VDD→analog switch 1-MOS7.9→ground.

This current path is cut off, and the flow of through current I2 can be prevented.

(Problems to be Solved by the Invention) However, the data latch circuit having the above configuration has the following problems.

(i) At the input end of the latch circuit consisting of the inverter 2.3, MO5t8 and MO5t9 for cutting off the through current are provided.

Therefore, if the data latch circuit shown in Fig. 2 is applied to various display device drivers, etc. consisting of LEDs (light emitting diodes), LCDs (liquid crystal elements), thermal heads, etc., which are composed of multi-stage shift registers and latch circuits,
The chip area of an integrated circuit increases due to wiring area, gate area, element area, etc.

(ii) Since the set signal S line and the inverted reset signal f line have long routes, the capacitance of each of these signal lines increases by the wiring pattern and gate capacitance during set and reset operations. Therefore, the burden on drivers for generating set and reset signals made up of MOS inverters and the like increases. Of course, in drivers for various display devices that have a large number of bits, the load capacity increases as the number of bits increases. Therefore,
In order to perform set and reset operations at high speed, a driver with a lower gain G+s is required.

(iii) MOS8 and 9 are provided, and the set signal line goes to MOS4 and 8, and the reset signal line goes to MOS5.
Since it is necessary to route the MOS
8 and 9, the set signal S is supplied only to MOS4, and the reset signal ■ is supplied only to MOS5.Compared to a data latch circuit, the circuit configuration and layout configuration are more complicated.The present invention has the above-mentioned conventional technology. A data latch circuit that solves the problems of increased gate area and wiring area, increased burden on the control signal generation driver due to increased parasitic capacitance, complexity of circuit configuration, and complexity of pattern layout design. It provides:

(Means for Solving the Problems) In order to solve the above problems, the present invention provides an analog switch for controlling input of data signals, and a data signal connected in series to the analog switch and input through the analog switch. and a circuit that switches the output of the latch circuit to a set state or a reset state using a non-synchronized set signal, a reset signal, or a set signal/reset signal. A signal generation circuit is provided that generates a control signal to turn off the analog switch.

(Function) According to the present invention, since the data latch circuit is configured as described above, the signal generation circuit generates a control signal in synchronization with the generation of the set signal or reset signal, and the analog switch is activated by the control signal. This eliminates the need for a conventional through-current interrupting MOS.
The circuit configuration can be simplified. Therefore, the above-mentioned problem can be eliminated.

(Embodiment) Fig. 1 (1) and (2) show a first embodiment of the present invention, and Fig. 1 (1) is a circuit diagram 4 of a data latch circuit with asynchronous set/reset. (2) is a signal generation circuit for a signal supplied to the data latch circuit.

The data latch circuit in FIG. 1 (1) has an analog switch (also referred to as a transfer gate) 21 composed of an NMOS controlled by a side control signal φ and an O8 at P controlled by an inverted control signal positive. , those NMOS and P
An inverted data signal n- is input to each case side of the MOS, and six inverted data signals n- whose respective sources of the NMOS and PMOS are connected to node A are generated by a shift register, a flip-flop circuit, etc. Ru. A latch circuit composed of CMOS inverters 22 and 23 is connected to node A, and an output signal Q is sent from the latch circuit.

Further, the node A has N which is controlled by the set signal S.
The drain of the MOS 24 is connected to the drain of a PMOS 25 controlled by the 1-inversion reset signal (2), the source of the NMQS 24 is connected to the ground, and the drain of the PMO 925 is connected to the power supply voltage VD port. In FIG. 11 (1), an inverter composed of MOS 8 and 7 as shown in FIG. 2 is connected to the input side of the analog switch 21, and the inverter inverts the data signal and outputs the inverted signal τ. may be input to the analog switch 21.

The signal generation circuit shown in FIG. 1 (2) is a circuit that supplies control signals φ, T, set signal S, and inverted reset signal ■ to the circuit shown in FIG. 30, 31.32, 33.34, 3-person AND
A gate 35 is provided.

Inverters 30 and 31 are connected in series to the set signal SO terminal, and a set signal S is output from the inverter 31 at the subsequent stage. An inverter 32 is connected to the reset signal RO terminal, and an inverted reset signal (2) is output from the inverter 32. The three-man power AND gate 35 has its two inverting inputs connected to a set signal So terminal and a reset signal Ro terminal, and has one input terminal connected to a clock signal CK terminal. Further, an inverter 33 is connected to the output side of the AND gate 35, and an inverter 34 is further connected to the output side of the inverter 33. The inverter 33 outputs an inverted control signal "φ-," and the signal T is inverted by the inverter 34 to output the control signal φ.

Next, the operation will be explained.

(1) Latch operation When the set signal So and reset signal RO in Figure 1 (2) are both at ground potential (hereinafter referred to as L level), the set signal S is at L level through inverters 30 and 31, and inverted reset is performed through inverter 32. The signal ■ is the power supply voltage W
OO (hereinafter referred to as H level).

Therefore, both MOSs 24 and 25 in FIG. 1(1) are in an off state. When the analog switch 21 is turned on, the inverted data signal W input in this state is written into the latch circuit made up of inverters 22 and 23. Also, analog switch 2! When turned off, the latch plane enters the latched state and remains latched regardless of changes in the inverted data signal.

(2) Set and reset operations The operations for setting and resetting latched data asynchronously with the clock signal CK will be explained.

In order to set the output signal Q to the H level, it is necessary to set the node A to the L level.

When the potential of node A is forcibly lowered to L level by turning on MOS 24, output signal Q of inverter 22 becomes H level. Also, when setting, the set signal S
The MOS 24 can be turned on by setting O to the H level, but the inverted signal (=:L level) of the set signal So is input to the AND gate 35, and the AND gate 3
5 becomes L level, and the clock signal CK becomes H and L.
Regardless of the level, the control signal φ becomes L level, the inverted control signal T becomes H level, and the analog switch 21
turns off.

Therefore, even if the inverted data signal 1 is at H level, the power supply voltage v[]] lower analog switch 21 (not shown) does not flow.

Similarly, at reset, MOS25 is turned on and node A
When increasing the potential of the latch circuit and setting the output signal Q of the latch circuit to the L level, the output of the AND gate 35 in FIG. No through current flows through the path D-MOS 25→analog switch 21→ground (not shown).

3 and 4 are circuit diagrams of signal generation circuits with malfunction prevention circuits showing second and third embodiments of the present invention;
The circuit in the figure is a set priority type malfunction prevention signal generation circuit,
The circuit shown in the figure is a reset priority type malfunction prevention signal generation circuit.

The first embodiment described above is designed on the assumption that the set signal So and the reset signal RO are not used at the same time.Normally, it is unthinkable to use both signals So and RO at the same time, but the system Malfunctions and wiring errors due to noise, etc., and software problems, etc.
It is also conceivable that an L level signal is applied to the set signal So terminal and the reset signal RO terminal at the same time. that time,
Since both MOS24 and 25 are turned on, the power supply voltage VDD
- A through current flows through the path of MOS25, 24→ground.

In particular, if the first embodiment is applied to a driver for a display element with a large number of bits, a large amount of short circuit current will flow, which may lead to destruction of the IC chip.

Therefore, in order to prevent these troubles, the circuits shown in FIGS. 3 and 4 are provided with a protection circuit for preventing malfunction within the IC chip.

Among these, in the set priority type signal generation circuit shown in Fig. 3,
The inverter 32 in FIG. 1(2) is connected to the HAND gate 42.
The circuit configuration is made by replacing the .

In the operation shown in FIG. 3, when the set signal So is set to H level, the output of NAND42 is fixed to L level, and the first
The MOS 25 in FIG. 1 is turned off. Even if the reset signal Ro becomes H level for some reason, the inverted reset signal ■ remains at L level, and thereby the MOS 25 also remains in the off state. ? [It is possible to prevent through current in the path of voltage VDD, MOS25, 24 → ground. In the circuit shown in FIG. 3, when the set signal So and the reset signal Ro go to H level at the same time, the set state takes priority over the reset state.

On the other hand, FIG. 4 shows a beam set priority type signal generation circuit, in which the inverter 30 in FIG.
The circuit configuration is made by replacing the D gate 50 with t.

In FIG. 4, when the reset signal Ro is at H level, W
Since the output of the AND gate 50 is fixed at L level,
When the set signal S is at H level, the MOS 24 in FIG. 1(2) is maintained in the off state, and the same advantages as in FIG. 3 can be obtained.
In the circuit shown in FIG. 4, when the reset signal RO and the set signal SO become H level at the same time, the reset state takes priority.

1st and 2nd above. The advantages of the third embodiment can be summarized as follows.

(2) A signal generation circuit is provided, and the set signal S, the inverted reset signal (2), and the clock signal GK themselves have control functions, so that through current can be prevented during asynchronous set and reset. Furthermore, regarding the data latch circuit shown in FIG. 1 (1), the conventional through-current cutoff MOs 98 and 9 are omitted, resulting in a reduction in wiring area, a corresponding reduction in parasitic capacitance, and a burden on the control signal generation driver. It is possible to measure the reduction of

(2) In conventional circuits, when inputs occur simultaneously to the set signal So terminal and the reset signal RO terminal due to noise or the like, a short circuit occurs between the power supply and the ground, and a large amount of malfunctioning current flows. On the other hand, in the second and third embodiments, it is possible to easily realize a data latch circuit that gives priority to set or reset, so that the short-circuit state can be easily and accurately prevented.

■ Considering display devices such as LEDs, LCDs, and thermal heads, the dimensions per bit of display devices such as LEDs and LCDs tend to become smaller year by year due to technological development, and the development of higher quality display devices is becoming more and more important. It is progressing. Therefore, there is a strong demand to reduce the chip size of devices, and the key point is to reduce the size of shift registers and data latch circuits. As in this embodiment, a device that reduces the size of the circuit configuration itself and improves ease of pattern design is a very effective technical means.

Note that the present invention is not limited to the illustrated embodiment; for example, the first embodiment
The overall configuration of the data latch circuit shown in Figure (1).

For example, it is possible to create a circuit that only has a set or reset affi, or to transform each circuit component into something else. Furthermore, the overall configuration of the signal generation circuit in FIG. 1 (2), FIG. 3, and FIG. You can also do it. In addition to the driver IC of the above embodiment, the present invention can also be applied to general logic LSIs and the like.

(Effects of the Invention) As explained in detail above, according to the present invention, since the signal generation circuit that turns off the analog switch is provided,
With low power consumption, high speed, small size, and simple circuit configuration, penetration r! , it is possible to accurately prevent the flow.

[Brief explanation of drawings]

Figures 1 (1) and (2) show a first embodiment of the present invention; Figure 1 (1) is a circuit diagram of a data latch circuit; Figure 1 (1) is a circuit diagram of a data latch circuit;
2) is a circuit diagram of a signal generation circuit, Figure 2 is a circuit diagram of a conventional data rough/child circuit, and Figures 3 and 4 are circuit diagrams of a second circuit of the present invention.
FIG. 2 is a circuit diagram of a signal generation circuit showing a third embodiment. 21... Analog switch, 22.23... Inverter for latch circuit, 24... MO5 for set, 25
...MOS for reset. Applicant's representative: Yasushi Kakinoki Data latch circuit Figure 1: Data latch circuit of the present invention

Claims (1)

[Scope of Claims] An analog switch that controls the input of a data signal, a latch circuit that is connected in series to the analog switch and latches the data signal that is input through the analog switch, and at least an asynchronous set signal and a reset signal. In the data latch circuit, the data latch circuit includes a circuit for switching the output of the latch circuit to a set state or a reset state, and a signal generating circuit is provided for generating a control signal to turn the analog switch off at the time of setting or resetting. Characteristic data latch circuit.