JPS62247735A - Electric source controller - Google Patents
Electric source controllerInfo
- Publication number
- JPS62247735A JPS62247735A JP61090718A JP9071886A JPS62247735A JP S62247735 A JPS62247735 A JP S62247735A JP 61090718 A JP61090718 A JP 61090718A JP 9071886 A JP9071886 A JP 9071886A JP S62247735 A JPS62247735 A JP S62247735A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- circuit
- outputs
- power supply
- input
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 4
- 238000000034 method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
Classifications
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
- Y02B—CLIMATE CHANGE MITIGATION TECHNOLOGIES RELATED TO BUILDINGS, e.g. HOUSING, HOUSE APPLIANCES OR RELATED END-USER APPLICATIONS
- Y02B70/00—Technologies for an efficient end-user side electric power management and consumption
- Y02B70/30—Systems integrating technologies related to power network operation and communication or information technologies for improving the carbon footprint of the management of residential or tertiary loads, i.e. smart grids as climate change mitigation technology in the buildings sector, including also the last stages of power distribution and the control, monitoring or operating management systems at local level
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y04—INFORMATION OR COMMUNICATION TECHNOLOGIES HAVING AN IMPACT ON OTHER TECHNOLOGY AREAS
- Y04S—SYSTEMS INTEGRATING TECHNOLOGIES RELATED TO POWER NETWORK OPERATION, COMMUNICATION OR INFORMATION TECHNOLOGIES FOR IMPROVING THE ELECTRICAL POWER GENERATION, TRANSMISSION, DISTRIBUTION, MANAGEMENT OR USAGE, i.e. SMART GRIDS
- Y04S20/00—Management or operation of end-user stationary applications or the last stages of power distribution; Controlling, monitoring or operating thereof
- Y04S20/20—End-user application control systems
- Y04S20/221—General power management systems
Landscapes
- Power Sources (AREA)
- Remote Monitoring And Control Of Power-Distribution Networks (AREA)
- Control Of Voltage And Current In General (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は外部からの電源投入、切断信号をマイクロプロ
セッサで処理し下位の電源ユニットを制御しコンピュー
タなどに用いられる電源制御回路に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a power supply control circuit used in computers, etc., which processes external power-on and power-off signals using a microprocessor to control a lower power supply unit.
従来の電源制御回路としては、例えば第2図のブロック
図に示すものがある。この回路は、外部からの電源投入
切断、緊急切断信号等の命令信号及び下位の電源ユニ・
・ノドからの状態報告信号を受信する入力受信回路1と
、入力ポート3.制御用マイクロプロセッサ4.出力ポ
ート52発振器11を含む電源制御部2と、入力端子8
からの信号によりリセットを行うリセッ)・回路9と、
アンド回路10と、出力回路6とから構成される。As a conventional power supply control circuit, there is one shown in the block diagram of FIG. 2, for example. This circuit is used for external command signals such as power on/off, emergency cutoff signals, etc.
- An input receiving circuit 1 that receives a status report signal from the node, and an input port 3. Control microprocessor 4. A power supply control section 2 including an output port 52 and an oscillator 11, and an input terminal 8
A reset circuit 9 that performs reset by a signal from
It is composed of an AND circuit 10 and an output circuit 6.
この制御用マイクロプロセッサ4は、リセット回路9か
らのリセッ1へ信号Aにより初期化され発振器11出力
により内部動作を行う。電源制御部2は、入力ポート3
により入力受信回路1がらの信号を受け、出力ポート5
に下位への命令信号及び外部への報告信号を出力し、リ
セット信号入力と発振器入力信号が確定し内部初期化が
終った後クリア信号Bを出力する。リセット回路9は、
電源制御回路の入力電源投入時に電源制御部2、及びア
ンド回路10にリセット信号を送出する。アンド回路1
0は、リセット回路9の出力とクリア信号Bの出力を入
力とし、出力回路6に出力し、出力回路6は、アンド回
路10の出力と出力ポート5の出力とを入力して下位電
源ユニットへの命令信号及び外部への状態報告信号を出
力する。The control microprocessor 4 is initialized by the reset 1 signal A from the reset circuit 9 and performs internal operations by the output of the oscillator 11. The power supply control unit 2 has an input port 3
receives the signal from the input receiving circuit 1, and outputs the signal from the output port 5.
It outputs a command signal to the lower level and a report signal to the outside, and outputs a clear signal B after the reset signal input and oscillator input signal are determined and internal initialization is completed. The reset circuit 9 is
When the input power of the power supply control circuit is turned on, a reset signal is sent to the power supply control section 2 and the AND circuit 10. AND circuit 1
0 inputs the output of the reset circuit 9 and the output of the clear signal B and outputs it to the output circuit 6, and the output circuit 6 inputs the output of the AND circuit 10 and the output of the output port 5 to the lower power supply unit. outputs command signals and status report signals to the outside.
入力受信回路1に外部からの電源投入、切断。Turns on/off power to input receiving circuit 1 from outside.
緊急切断信号等の命令信号又は下位の電源ユニットから
の状態報告信号を受信した時、制御用マイクロプロセッ
サ4は入力ポート3より命令信号又は状態報告信号を受
け取り、所定の論理時間により処理を行って出力ポート
5に下位電源ユニットへの命令18号又は外部への報告
信号を送出し、下位電源ユニッ1〜又は外部へ出力回路
6を通って送出される。When receiving a command signal such as an emergency disconnection signal or a status report signal from a lower power supply unit, the control microprocessor 4 receives the command signal or status report signal from the input port 3, and processes it according to a predetermined logical time. An instruction No. 18 to the lower power supply unit or a report signal to the outside is sent to the output port 5, and is sent to the lower power supply unit 1 to the outside through the output circuit 6.
また、リセッ1へ回路9により電源制御回路の入力電源
投入時、規定の電圧に達するのを待ち、かつ発振器11
の安定動作時間を待ち、制御用マイクロプロセッサ4に
リセット信号として入力し、制御用マイクロプロセッサ
4は内部初期化後クリア信号Bを出力し、リセット信号
Aとの条件の一致により出力回路6に入力され、下位電
源ユニットへの命令信号又は外部への報告信号を初めて
有効にする。また電源制御回路の入力電源切断時には、
リセット回路9により制御用マイクロプロセッサ4をリ
セッ)・シ、出力回路6にも入力され下位電源ユニツ1
〜又は外部への報告信号を無効とし誤った命令、報告を
しないようにしている。In addition, when the input power of the power supply control circuit is turned on by the circuit 9 to the reset 1, the oscillator 11 waits for the input power to reach the specified voltage.
After waiting for stable operation time, input it to the control microprocessor 4 as a reset signal, and the control microprocessor 4 outputs a clear signal B after internal initialization, and when the condition matches the reset signal A, it is input to the output circuit 6. and enables the command signal to the lower power supply unit or the report signal to the outside for the first time. Also, when the input power to the power supply control circuit is turned off,
The reset circuit 9 resets the control microprocessor 4, which is also input to the output circuit 6 and output to the lower power supply unit 1.
~ Or the report signal to the outside is disabled to prevent incorrect commands and reports.
上述した従来の電源制御回路においては、制御用マイク
ロプロセッサ4でのノイズの混入、予期していない入力
条件又はデハッグ不充分等によるプログラムミスによる
スト−ルが起きた場合、外部からの電源投入切断、緊急
切断信号等の命令信号及び下位の電源ユニットからの状
態報告信号を受けつけない場合がある。これら命令信号
のうち電源投入信号においては、この信号が来た時、ス
1〜−ルが起きたか、もしくは起きてた場合には単に電
源の投入が出来なくなって故障となり、電源制御回路の
入力電源の切断再投入で初期状態に復帰させることが出
来るが、電源切断が出来ないという事態は運用−E支障
があり、復帰の為には分電盤のスイッチを一度切断後再
投入する必要があり、特に大型システムにおいては問題
である。また、緊急切断指示は火災、地震、水害等の予
期しない状況時に発せられ、システムの電源を直ちに切
断しなければならないが、直ちには切断出来ないと大問
題となる。In the conventional power supply control circuit described above, if a stall occurs due to a programming error due to noise in the control microprocessor 4, unexpected input conditions, or insufficient debugging, the power supply cannot be turned on or off from the outside. , command signals such as emergency disconnection signals, and status report signals from lower power supply units may not be accepted. Among these command signals, in the power-on signal, when this signal comes, a shutdown has occurred, or if it has occurred, the power simply cannot be turned on, resulting in a failure, and the input to the power supply control circuit. It is possible to return to the initial state by turning the power off and then on again, but a situation where the power cannot be turned off poses an operational problem, and in order to recover, it is necessary to turn off the switch on the distribution board and then turn it on again. This is a problem, especially in large systems. Further, an emergency disconnection instruction is issued in the event of an unexpected situation such as a fire, an earthquake, or a flood, and it is necessary to immediately disconnect the power to the system, but if the power cannot be disconnected immediately, a major problem will occur.
本発明の目的は、これらの問題を解決し、制御用マイク
ロプロセッサがスl−−ルしても電源制御を支障なく行
える電源制御回路を提供することにある。SUMMARY OF THE INVENTION An object of the present invention is to solve these problems and provide a power supply control circuit that can perform power supply control without any trouble even if the control microprocessor is idle.
本発明の電源制御回路の構成は、外部装置からの電源投
入、電源切断の命令信号を受け下位電源装置からの状態
報告信号を受ける入力受信回路と;この入力受信回路か
らの命令信号を入力ポートを介して入力し、リセット信
号により初期化されこの初期化の終了時にクリア信号を
出力し、出力ポートを介して前記下位装置への命令信号
および前記外部装置への状態報告信号を出力するマイク
ロプロセッサを含む電源制御部と;前記出力ポートから
前記下位装置への信号を出力する出力回路と:電源投入
の時およびリセット要求信号が入力した時前記リセット
信号を出力するリセット回路と;前記リセット信号と前
記クリア信号がある時前記出力回路への信号を出力する
論理回路と:前記電源切断の命令信号があった時前記電
源制御部の命令出力の最大遅延時間より長い時間後に前
記リセッ1へ要求信号を出力し前記下位装置への切断命
令信号によりその動作を停止する遅延回路とを備えるこ
とを特徴とする。The configuration of the power supply control circuit of the present invention includes an input receiving circuit that receives power-on and power-off command signals from an external device and a status report signal from a lower power supply; and an input port that receives command signals from this input receiving circuit. a microprocessor that is initialized by a reset signal, outputs a clear signal at the end of this initialization, and outputs a command signal to the lower-level device and a status report signal to the external device via an output port. an output circuit that outputs a signal from the output port to the lower device; a reset circuit that outputs the reset signal when the power is turned on and when a reset request signal is input; a logic circuit that outputs a signal to the output circuit when the clear signal is present; and: a request signal to the reset 1 after a time longer than the maximum delay time of the command output of the power supply control section when the power supply disconnection command signal is present. and a delay circuit that outputs a signal and stops its operation in response to a disconnection command signal to the lower device.
し実施例〕 次に、本発明について図面を参照して説明する。Example] Next, the present invention will be explained with reference to the drawings.
第1図は本発明の一実施例を示すブロック図である。本
実施例は、外部からの電源投入、電源切断、緊急切断信
号等の命令信号及び下位電源ユニットからの状態報告信
号を受信する入力受信回路1と:入カポート3.制御用
マイクロプロセッサ4.出力ポート51発振器11を備
え、制御用マイクロプロッサ4がリセット信号Aにより
初期化され発振器11の出力により内部動作を行い入力
ポート3により人力受信回路1からの信−号を受け、出
カポ−1−5により下位への命令信号及び外部への状態
報告信号を出力し、リセット信号Aと発振器11からの
入力が確定し、制御用マイクロプロセッサ4の内部初期
化が終った後クリア信号Bを出力する電源制御部2と;
この電源制御部2ヘリセット信M、 Aを出力するリセ
ット回路9と;このリセッ)〜回路9からのりセラ1〜
信号Aと電源制御部2からのクリア信号Bとを入力しこ
れらの論理積を出力するアンド回路10と;外部からの
電源切断及び緊急切断信号が入力受信回路1に入力され
た時電源制御部2と遅延回路7とに入力され、前記電源
切断及び緊急切断信号が入力された後下位電源ユニツ1
〜への切断命令信号を出力するまでの遅延時間の最大時
間より長い時間後にリセット回路9ヘリセット要求信号
を出力し、前記下位電源ユニットへの切断命令信号の入
力により動作を停止する遅延回路7と、外部への状態報
告信号及び大泣への命令をアンド回路10からの信号が
来たとき確定し出力する出力回路6とを有する。FIG. 1 is a block diagram showing one embodiment of the present invention. This embodiment includes an input receiving circuit 1 which receives command signals such as power-on, power-off, and emergency disconnection signals from the outside, and a status report signal from a lower power supply unit; and an input port 3. Control microprocessor 4. The control microprocessor 4 is initialized by the reset signal A, performs internal operation by the output of the oscillator 11, receives a signal from the human power receiving circuit 1 through the input port 3, and outputs the output port 1. -5 outputs a command signal to the lower level and a status report signal to the outside, and outputs a clear signal B after the reset signal A and input from the oscillator 11 are confirmed and the internal initialization of the control microprocessor 4 is completed. a power supply control unit 2;
This power supply control unit 2 has a reset circuit 9 that outputs reset signals M and A;
an AND circuit 10 which inputs the signal A and the clear signal B from the power supply control section 2 and outputs the logical product thereof; and a power supply control section when a power cutoff and emergency cutoff signal from the outside is inputted to the input receiving circuit 1; 2 and the delay circuit 7, and after the power cutoff and emergency cutoff signals are inputted, the lower power supply unit 1
a delay circuit 7 that outputs a heliset request signal to the reset circuit 9 after a time longer than the maximum delay time until it outputs a disconnection command signal to ~, and stops its operation upon input of the disconnection command signal to the lower power supply unit; and an output circuit 6 which determines and outputs a status report signal to the outside and a command to run out when a signal from the AND circuit 10 arrives.
以」二の構成による本実施例は、外部からの電源切断信
号及び緊急切断信号が入力され、かつ制御用マイクロプ
ロセッサがストールしていた場合、下位電源モジュール
に対して切断命令信号を出せなくなるが、遅延回路を通
して制御用プロセッサに対してリセット信号を与えるこ
とにより、制御用プロセッサを初期化して強制的に下位
電源モジュールに対して切断命令信号を出すことができ
る。In this embodiment with the second configuration, if a power cutoff signal and an emergency cutoff signal are input from the outside and the control microprocessor is stalled, it becomes impossible to issue a cutoff command signal to the lower power supply module. By applying a reset signal to the control processor through the delay circuit, the control processor can be initialized and forcibly issue a disconnection command signal to the lower power supply module.
また、外部からの電源切断信号及び緊急切断信号が入力
され、かつ制御用プロセッサがストールしていない場合
は、下位電源モジュールに対して正常な切断命令信号を
出すと共に遅延回路に入力され、遅延回路はその動作を
停止することとなる。In addition, if a power cutoff signal and an emergency cutoff signal are input from the outside and the control processor is not stalled, a normal cutoff command signal is output to the lower power supply module and is input to the delay circuit. will stop its operation.
以上説明したように本発明によれば、制御用マイクロプ
ロセッサがストールしていても、ス1ヘールしていなく
ても、下位電源モジュールに対して切断命令信号を出せ
るので、万一制御用マイクロプロセッサがス1ヘールし
ても、通常の電源切断及び緊急時の電源切断が支障なく
行えるという効果がある。As explained above, according to the present invention, even if the control microprocessor is stalled or not stalled, it is possible to issue a disconnection command signal to the lower power supply module. Even if the system fails, normal power shutoff and emergency power shutoff can be performed without any problem.
第1図は本発明の一実施例のブロック図、第2図は従来
の装置の一例のブロック図である。
1・・・入力受信回路、2・・電源制御部、3・・・入
力ポート、4・・・制御用マイクロプロセッサ、5・・
・出力ポート、6・・・出力回路、7・・・遅延回路、
8・・・リセット回路入力電源端子、9・・リセット回
路、10・・・アンド回路、11・・・発振器。FIG. 1 is a block diagram of an embodiment of the present invention, and FIG. 2 is a block diagram of an example of a conventional device. DESCRIPTION OF SYMBOLS 1... Input receiving circuit, 2... Power supply control section, 3... Input port, 4... Control microprocessor, 5...
・Output port, 6...output circuit, 7...delay circuit,
8... Reset circuit input power supply terminal, 9... Reset circuit, 10... AND circuit, 11... Oscillator.
Claims (1)
位電源装置からの状態報告信号を受ける入力受信回路と
;この入力受信回路からの命令信号を入力ポートを介し
て入力し、リセット信号により初期化されこの初期化の
終了時にクリア信号を出力し、出力ポートを介して前記
下位装置への命令信号および前記外部装置への状態報告
信号を出力するマイクロプロセッサを含む電源制御部と
;前記出力ポートから前記下位装置への信号を出力する
出力回路と;電源投入の時およびリセット要求信号が入
力した時前記リセット信号を出力するリセット回路と;
前記リセット信号と前記クリア信号がある時前記出力回
路への信号を出力する論理回路と;前記電源切断の命令
信号があった時前記電源制御部の命令出力の最大遅延時
間より長い時間後に前記リセット要求信号を出力し前記
下位装置への切断命令信号によりその動作を停止する遅
延回路とを備えることを特徴とする電源制御回路。An input receiving circuit that receives command signals for powering on and powering off from external devices and receiving status report signals from lower power supplies; command signals from this input receiving circuit are input through the input port, and initialization is performed by a reset signal. a power supply control unit including a microprocessor that outputs a clear signal when the initialization is completed, and outputs a command signal to the lower-order device and a status report signal to the external device via the output port; an output circuit that outputs a signal from to the lower device; a reset circuit that outputs the reset signal when the power is turned on and when a reset request signal is input;
a logic circuit that outputs a signal to the output circuit when there is the reset signal and the clear signal; and a logic circuit that outputs a signal to the output circuit when there is the command signal to turn off the power; A power supply control circuit comprising: a delay circuit that outputs a request signal and stops its operation in response to a disconnection command signal to the lower device.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61090718A JPS62247735A (en) | 1986-04-18 | 1986-04-18 | Electric source controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61090718A JPS62247735A (en) | 1986-04-18 | 1986-04-18 | Electric source controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62247735A true JPS62247735A (en) | 1987-10-28 |
Family
ID=14006322
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61090718A Pending JPS62247735A (en) | 1986-04-18 | 1986-04-18 | Electric source controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62247735A (en) |
-
1986
- 1986-04-18 JP JP61090718A patent/JPS62247735A/en active Pending
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