JPS62247529A - Method for alignment - Google Patents

Abstract

PURPOSE:To ensure a high-precision alignment for each of the patterns on a wafer by a method wherein stored data are used for the control of step movement for the step-and-repeat treatment of other substrates when patterns of substrates in the same lot are processed by the step-and-repeat technique. CONSTITUTION:In the processing of a plurality of chips 2 on a wafer 1, a global alignment is accomplished, for example, between measuring points P and Q. In the event there is any array distortion involving patterns on the wafer 1, a difference deltax is detected between the actual distance from the measuring point P to Q and the distance expected by design to exist between the two points P and Q (the distance to be covered by a correct chip line-up). Acquisition of data concerning the pattern array on the wafer 1 will enable a correct compensation for the elimination of the array distortion present in the global alignment. The method for such a correct compensation consists of a means for reading the chip pattern array on the wafer 1, a means for the arithmetic handling and/or storage of the collected data, and a means to enable the application of the collected data to the global alignment process by establishing correspondence between the collected data and the conditions in the wafer 1.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an alignment method for a step-and-repeat type processing apparatus, and more particularly to an alignment method for a step-and-repeat type projection exposure apparatus (hereinafter referred to as a stepper) used in the manufacturing process of integrated circuit devices.

For example, a stepper is a reduction projection optical system (hereinafter referred to as a reticle) that reduces a pattern for forming a circuit on an enlarged original plate (hereinafter referred to as a reticle).
This is a device that repeatedly exposes and prints a semiconductor substrate (hereinafter referred to as a wafer) through a lens (hereinafter referred to as a lens).

In this apparatus, the area that is projected and exposed at one time is usually a small area corresponding to one integrated circuit element portion (hereinafter abbreviated as a chip) to several chips. Therefore, in order to print the pattern on the reticle over the entire surface of the wafer, exposure is repeated while the wafer is moved stepwise relative to the reticle in the X and Y directions within a plane orthogonal to the optical axis of the lens. Here, the number of exposures ranges from tens to hundreds.

+Small w -J-L〒tunl〉≦1li^sky-71? -^I1, S- is usually performed several to ten times, so from the second step onwards, relative positioning (hereinafter abbreviated as alignment) between the reticle pattern and each chip pattern on the wafer is required. Become. Here, alignment methods can be roughly classified into the following two types.

One method is to align the reticle between two or more predetermined points between two or more chips on the wafer, and use the coordinates obtained through this alignment as the origin to measure the wafer using a length measurement scale such as a laser interferometer. This is a method called global alignment, in which exposure is repeated while stepping the image.

The other method is called die-by-die alignment, in which the reticle pattern and the chip pattern on the wafer are directly aligned and exposed through a projection exposure lens at each chip printing position.

By the way, in die-by-die alignment, since the wafer chip pattern and reticle pattern are directly aligned for each chip, there is no positional deviation between the reticle pattern image and the wafer chip pattern during exposure, but it takes longer to process the wafer and reduces throughput. It has the disadvantage of

On the other hand, although global alignment is good in terms of throughput, it poses a problem of positional deviation between the reticle pattern image and the wafer chip pattern.

The present invention was made in view of the above circumstances, and its purpose is to provide an apparatus for step-and-repeat processing of a plurality of pattern portions on each of a plurality of substrates whose processes are managed on a lot-by-lot basis. An object of the present invention is to provide an alignment method that can align each pattern with high precision and without reducing the throughput of the apparatus.

In order to achieve this object, the present invention sequentially aligns each pattern portion with respect to a reference by die-by-die alignment for at least one substrate in a lot unit, and □When processing the pattern portions of other substrates in the lot unit by step-and-repeat, data regarding the arrangement of the other substrates is stored based on the stored data. It is characterized by controlling step movement for step-and-repeat processing.

The alignment method of the present invention will be explained below using a stepper as an example.

Generally, chip patterns arranged on a wafer should originally be arranged at equal intervals along the x and Y axes, but the arrangement is slightly disordered mainly due to the following two reasons. One of the reasons for this is due to the nature of the exposure equipment (aligner) used during pattern printing at the process opening, or the condition of the wafer and reticle (mask).The other reason is that the wafer is damaged due to heating processes such as diffusion and oxidation. This is caused by your own distortion.

When global alignment is performed for a plurality of chips 2 on a wafer l as shown in FIG. , 0 and the original distance (assuming that if the chips are correctly aligned, there will be a linear pattern alignment distortion radially from the center of the wafer l° as shown in Figure 2). It is conceivable to perform step exposure with the following correction values taken into consideration.

That is, L is the actual measurement value, Lo is the original dimension, and, X=(1+K)Xo ・・・・・・・・・・・・・・・
・・・・・・・・・・・・・・・(2) Y=(1+K)
Yo ・・・・・・・・・・・・・・・・・・・・・
・・・・・・・・・Step exposure is performed so that (3) is obtained. Xo here.

Yo is the original step feed amount. However, the wafer
The pattern arrangement within is not always linear. For example, if you have a nonlinear array characteristic curve (curve 4) as shown in Figure 2, the reticle pattern will have an alignment error represented by the difference between straight line 3 and curve 4 at each X point. As a result, each chip pattern of the evaporator 1 is overlaid and printed. Furthermore, alignment errors also occur when the arrangement of the chip patterns on the wafer 1 is not arranged radially. In other words, when step-feeding the wafer I, alignment accuracy is not sufficient if the step-feed correction amount K is always constant.

On the other hand, if you want information about the pattern arrangement of the wafer,
It becomes possible to apply accurate correction to global alignment using the above information. The means for this are (A)
means for reading the array of chip patterns on the wafer l, (
B) Means for calculating and/or storing the read information; (C) Means for associating the information with the wafer 1 and making it possible to use the information for global alignment; Some valid processes (
procedure) can be considered.

First, we will discuss individual methods.

As for the means (A) for reading the arrangement of chip patterns on the wafer 1, there is a method (1) of using the measuring means of the stepper itself. If the alignment position of each individual chip is read by a built-in laser interferometer or other length measurement function after one die-by-die alignment,
The data can be used as correction values for subsequent global alignment of that wafer l. Or (2
) It may be an independent device with only an alignment function. It is a stepper with the projection exposure function removed, and can be considered an improved version of the current coordinate measuring machine.

Next, regarding the means for calculating and/or storing information in (B), first, there is a method (1) for storing all measurement data in a storage device with respect to coordinates based on a specific chip pattern within the wafer l. Conceivable. However, this method has the disadvantage of requiring a huge amount of storage capacity when applied to all wafers l in the middle of the process. In that case, (2) means for storing the obtained data as a constant of a mathematical formula for pattern arrangement distortion predicted in advance becomes effective. The majority of currently available aligners other than steppers are contact or proximity type aligners and mirror projection type aligners. It is known with which type of aligner the first photo process was performed on the target wafer 1, and the characteristics of these aligners during patterning can be expressed in the form of a mathematical formula. For example, for some mirror projection types,
) sθy−N'2 l Y la + G(x, y)
I! φx + k x ・・・・・・=・(4) Y=y
+△y=y−k(y)(θχ+θy) + y(θχ+
θy)+2G(x,y)sθx+(f2K(y)±f2
S) α+2G(x,y)fφy+ky
......(5). Here, s, I!
is a machine-specific constant, G (x.

y), K (y) are values determined by the coordinates of the wafer l, θX, θy, φX, φy, α are the angular errors of the optical system, and kx, ky are the linear elongation in the radial direction due to the temperature of the mask and wafer. It shows. By substituting the obtained data into the equation, simultaneous equations are established, and the unknowns θ2. θX
It is sufficient to store the cans and the like in the storage device using φxcbvafP. The number of factors for this distortion (
It is possible to store a much smaller amount of general data than (1), and a larger amount of general data.
i) Data acquisition can be limited to the minimum amount of data necessary to solve the equation, or (ii) Variable accuracy can be further improved by using data from all measurement points.
(iii) Alternatively, in preparation for unpredictable distortion, or the habits of individual aligners can be added as a variable term.

Next, regarding the means for associating information with wafers in (C), wafer 1 is generally managed in units of lots, for example, units of 25 carriers, and wafers within a lot are preferably processed under the same conditions. Therefore, one possible method is to consider one wafer among the wafers as a representative and associate them with each other. Further, a code mark, number, symbol, etc. may be marked on a part of the wafer to manage each wafer.

Next, consider combinations of the above means.

l) If wafers are subject to process control on a lot-by-lot basis, it is effective to use a stepper to perform die-by-die alignment on the first wafer in the lot, and at the same time import that information to perform global alignment on the second and subsequent wafers. become. In this case, even if all the data is stored, the stored data becomes unnecessary once all wafers in the lot are completed and can be deleted.

2) Also, in the case of lot-by-lot management, it is also possible to place a dedicated alignment device in front of the stepper and memorize the positions of all chips before sending them to the stepper. This procedure is nothing but saving the time lost due to the serial operation of alignment and exposure in die-by-die alignment using a stepper by removing only the alignment operation and performing parallel operations. In this case as well, it is advantageous to use all the data as is. According to this method,
Since the measurement is taken just before exposure, all error components can be read.

3) When management is performed on a wafer basis, it is effective to store the variables in the form of the formula variables described above. In this case, the information is captured by die-by-die alignment using the first stepper in the repeated photo process, or an alignment machine is placed in front of the first stepper to capture the data, and these data are then used in the subsequent global alignment. The data will be used.

Various other combinations can be considered based on the above three combinations, but these will ultimately be considered by the process manager based on the balance between alignment accuracy and throughput required in the actual process.

As described above, according to the present invention, a highly accurate alignment method using global alignment can be provided.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a wafer having a plurality of chip patterns, and FIG. 2 is a diagram showing an arrangement error curve of the chip patterns of the wafer shown in FIG.

Claims (1)

[Claims] To sequentially align each of the pattern portions with respect to a predetermined standard in order to perform step-and-repeat processing of a plurality of pattern portions on the substrate for each of a plurality of substrates whose processes are managed on a lot-by-lot basis. In the method, for at least one substrate in the lot unit, each of the pattern portions is sequentially aligned with the reference by die-by-die alignment, and the alignment of the pattern portions on the at least one substrate is performed. When processing the pattern portions of other substrates in the lot unit by step-and-repeat processing after the at least one substrate, step-and-repeat processing of the other substrates is performed based on the stored data. An alignment method characterized by controlling step movement for.