JPS62247461A - Counting system for executing time of vector instruction - Google Patents

Abstract

PURPOSE:To produce a program having high efficiency by inhibiting the count-up action of a vector timer for a period during which a vector unit is not executing the vector whose processing is requested from a scalar unit. CONSTITUTION:A vector unit VU-1 receives a vector instruction requested from a scalar unit SU 120 and executes and controls it by a vector executing unit VEU (not shown here) at an instruction control part 131. At the same time, a vector timer VT 132 counts the time during which the execution of the vector instruction is started and completed. For this purpose, a timer control signal TC is applied to the timer VT 132. The timer VT 132 counts up the clock signals CLOCK for counting of time. Then the timer VT 132 is inhibited to count up the signals CLOCK for the periods excepting the time needed for execution of the vector instruction by the signal TC received from the part 131.

Description

[Detailed Description of the Invention] [Summary] In an information processing device in which a scalar unit and a vector unit operate in parallel, only the time during which the vector unit executes a vector instruction sent from the scalar unit is measured to calculate 3 charges and programs. facilitates performance evaluation.

[Industrial application field]

The present invention relates to a method for measuring execution time of vector instructions in an information processing apparatus including a scalar unit and a vector unit.

[Technical Background] In general, in scientific and technical computers, the following methods have been conventionally used to achieve higher speeds.

■ Increase the data processing capacity of the vector unit that processes vector instructions.

■ Make it a multi-system.

In method (2), the speed-up effect differs depending on the ratio of vector instructions to other instructions in the program, and the larger the proportion occupied by the former instructions, the greater the effect.

A specific example is shown in FIG.

(A) in FIG. 5 shows the case where the vector instruction has a higher time ratio than other instructions, and (B) in FIG.
Regarding the opposite case, the effect is shown by comparing the current situation and the case where the processing capacity of vector instructions is doubled.

That is, in (A), the total processing time is approximately halved, but in (B), there is almost no difference.

Therefore, even if you simply increase the processing capacity of vector instructions,
In a program such as (B) in which the ratio of other instructions is large, the balance of the computer becomes poor and a large speed-up effect cannot be obtained.

Therefore, in general, a single system with an optimal balance of processing power is created.

In order to achieve higher speeds, the multi-system method (2) above is used.

By the way, in scientific calculation processing etc., programs are written in FORTR.
It is written in AN, etc., and in order to perform vector processing, it is usually possible to process what is written in FORTRAN as is. However, in that case, there is no problem as long as the maximum capacity of the vector processing function can be brought out.2 Normally, the program is tuned at the compiler processing stage to take advantage of the characteristics of each machine (in order to increase vector processing efficiency, the vector length is increased). You need to change the program to in this case.

In a multi-system, at the time of tuning, the processing time for each job must be exactly the same no matter how many times the same job is run. this is.

This is to determine whether the tuning was effective.

However, in a multi-system, if a vector unit that processes instructions for scientific and technical calculations, such as vector instructions, is shared by multiple units that process other instructions, such as scalar units, one scalar The execution time of a vector instruction requested from a unit to a vector unit is affected by the execution of vector instructions requested from other scalar units to the same vector unit at the same time, and therefore varies depending on the situation.

In this way, in order to improve the program, it is necessary to include the instructions included in the program. Knowing the execution time of each vector instruction is a powerful aid.

Furthermore, in the two computers, information on the execution time of the program is necessary for billing the job. However, in scientific and technological computers, scalar instructions and vector instructions, which have different processing times, operate in parallel, so the conventional simple billing method is no longer sufficient.

[Conventional technology]

Next, the conventional technology will be specifically explained using a vector processor (hereinafter referred to as ``P'') as an example.

VP is a vector unit 7) (V
LI) and a scalar unit (SU) that processes other instructions (scalar instructions).

First, an example of the configuration of a basic single system VP (represented by VP-1) is shown in FIG. 6(a).

In the figure, 600 is a main storage unit (represented by MSU);
05 is a storage control unit (represented by MCU).

610 is VP-1, 620 is SU, and 630 is VU-1.

Next, we will introduce a multi-system with two SUs and one VU (V
(referred to as PM), an example of its configuration is shown in FIG. 6(b).

In FIG. 6(b), 600 is MSU, 605 is MC
U, 610 is VP-M, 620 is S Uo, 62
1 is SU, 630 is VU-M. Note that ■UM has twice the processing capacity of VU-1.

Next, the state of program execution in each of the configuration examples shown in FIGS. 6(a) and 6(b) will be explained with reference to FIGS. 7(a) and 7(b).

Figure 7(al) and (b) are respectively Figure 6(a) and
(This is a time chart that corresponds to BL and shows how su, vu, etc. are executing instructions.

Next, FIG. 8 shows the configuration of the vector unit U in the single system of FIG. 6(a).

In the figure, 800 is an MSU, and 805 is an MCU.

820 is SU, 830 is VU, 840 is vector control unit) (represented by VCU), 841 is control signal, 850
is a vector execution unit) (represented by VEU), 860 is a load pipeline, 861 is a store pipeline, 8
70 is a vector register (represented by VR), 880 is an addition pipeline, 881 is a multiplication pipeline, and 882 is a division pipeline.

The VCU 840 is a unit that controls vector instructions.
Control signal 841 controls command execution of VEU 850 .

The VEU 850 is a unit that executes vector instructions, and includes load pipelines 860 . It has a store pipeline 861 and a VR 870 that holds vector data.

Furthermore, in order to execute an instruction to read vector data from the VR870, perform an operation, and write the result to the VR870, an addition pipeline 880° and a multiplication pipeline 88
1. It has a division pipeline 882.

In one VP, instructions are fetched from the MSU using the SU. When the SU fetches a scalar instruction, it executes it within the SU, and when it fetches a vector instruction, it passes it to the VU.

Next, the circuit that receives the vector instruction in the VU of FIG. 8 is shown in FIG. 9, where 900 in FIG.
Compatible with CU840. Vector instructions are input through bus 901 to instruction fetch stage register (denoted V FSR ) 911 .

Here the Vector Processor Stage Register (VFSR)
If there is no instruction in the VFSR 915 (represented by ), the instruction is transferred from the VFSR 911 to the VFSR 915.

However, when the VFSR 915 contains a preceding instruction or the instruction buffer (represented by VFR) 912 contains a preceding instruction, the instruction is transferred from the VFSR 911 to the VFB 912 and buffered.

When the preceding instruction leaves VFSR915, VFB912
If a command is included in the command, the command is input from the VFB 912 through the selector 914 to the VFSR 915 at the next timing.

The above operations are performed under the control of the instruction fetch control unit 913.

Instructions from the VFSR 915 are sent to an instruction decoder 918 and an exception check unit 919, and further sent to a vector queue stage register (represented by VQSR) 916 to control instruction transmission.

The instruction processing control unit 913 checks whether the VFB 912 is clogged and whether there is an instruction in the VPSR 915, and
12. Manually issues commands to the VPSR915 and performs selection control. Also, when VFB912 is full, VUFull
A signal is sent to SU900 via control line 902, and 5U9
Stops sending subsequent instructions starting from 00.

The exception check unit 919 performs exception checks for instructions in the VPSR 915 and checks the decoding results.

The command management control unit 917 controls command transmission based on decode information sent from the command decoder 918 and information from the VQSR 916.

Manages instructions being executed in the VEU. These controls are performed by control signals 920 to the VEU.

Next, V of the multisystem shown in Fig. 6(b)
The circuit configuration of the VCU in UM is shown in FIG. 1O. In Figure 10, 1030 VFUO and 1040 VF
The circuit and operating function of U.

The circuit portions 911 to 916 and 918 to 919 in FIG. 9 are basically the same. V F Uo, V F U
+ operate independently, S Uo , S
Instruction transfer, instruction buffering, and decoding to/from U+.

Perform exception checks, etc.

Reference numeral 1050 is an instruction switching control unit that handles vector instructions sent from SU (hereinafter referred to as 0-series vector instructions) and S
Control is performed to select which of the vector instructions sent from U (hereinafter referred to as 1-system vector instructions) is to be executed by the VEU.

1051 is a signal line for sending the selection signal.

The selection signal is a selector SEL indicated by 1052.1053.
sent to.

Selectors 1052 and 1053 switch the information input to the VQSRIO 61 and the command management control unit 1060 to the θ system or 1 system. Command management control unit 1060 and VQSR 106
1 corresponds to 917 and 916 in FIG. 9, respectively.

Next, the execution of the program will be explained using FIG. 7(b).

In FIG. 7(b), from To to T, Sue.

Both SU and SU execute scalar instructions, and there are no vector instructions. At T1, vector instructions are sent from both SUO and SU to VU, and VFUa, respectively.

Input to VFUI.

Here, the instruction switching control section 1050 in FIG.
The 0 system and 1 system are selected, but in this example, the 0 system is given high priority.

From T1, θ-based vector instructions are executed.

The vector instruction packets of the 1 system wait for execution (indicated by the period tw) until all the clusters of vector instructions (referred to as instruction packets) from the 0 system are completed.

At Tt, the first packet of the O system ends, and the instruction switching control unit 1050 switches the instruction execution to the 1 system.

[Problem that the invention seeks to solve]

In general-purpose computers, various timers have been conventionally provided to measure the execution time of programs.

These timers are also used in scientific computers.

It is installed in the SCARA unit and is used to measure the elapsed time of the program. However, the elapsed time of this program indicates the operating time including scalar instructions and vector instructions.

In this way, conventional timers merely measure elapsed time, and do not necessarily correspond to instruction execution time. Furthermore, it has not been possible to separate scalar instructions and vector instructions and measure their respective execution times.

[Means for solving problems]

According to the present invention, a vector timer is provided in a vector unit, and a count-up operation is performed during the execution of a vector instruction, thereby making it possible to independently measure the execution time of only the vector instruction.

FIGS. 1 and 2 show the basic configuration of the present invention in the case of one scalar unit and the case of a plurality of scalar units, respectively.

In FIG.

100 is MSU.

105 is MCU.

110 is a single system vector processor VP-
1°120 is a scalar unit SU.

130 is a vector unit VU.

131 is an instruction management control unit.

132 is a vector timer VT.

133 is a timer control signal TC.

134 is a clock signal CLOCK.

The scalar unit SU executes a program including a vector instruction, and when a vector instruction is detected.

The vector unit VU-1 is requested to perform the processing.

Vector unit VU-1 receives a vector command requested from scalar unit SU.

The instruction management control unit 131 manages execution using a vector execution unit (VEU) (not shown), and causes a vector timer VT to measure the time from the start of execution to the end of execution of the vector instruction.

Therefore, a timer control signal TC indicating that the vector instruction is being executed is applied to the vector timer VT.

The vector timer VT measures time by counting up the clock signal CLOCK.

The vector timer VT is prohibited from counting up the clock signal CLOCK during a period other than when the vector instruction is being executed by the timer control<TfJ signal TC given from the instruction management control section 131.

In this way, the execution time of a vector instruction is accumulated in the vector timer VT each time the vector instruction is executed.

In fig.

200 is MSU.

205 is MCU.

210 is a multi-system vector processor VP-M
.

220 is a SCARA unit 5U (1° 221 is a scalar unit SUt.

230 is a vector unit VU-M.

231 is an instruction management control unit.

232 is a vector timer VT corresponding to the scalar unit SUO.

233 is a vector timer VT corresponding to the scalar unit SU1.

234 is a timer control signal 'rco indicating that a vector instruction from the scalar unit Sue is being executed.

235 is a timer control signal TC indicating that a vector instruction from the scalar unit SU is being executed.

236 is a clock signal CLOCK.

The scalar units su, , sut execute programs in parallel, and when each detects a vector instruction, requests processing to the vector unit VU-M.

The command management control section 231 of the vector unit VU-M
When a request to process vector instructions is received from a scalar unit SU, , SU, those vector instructions are sent to the issuer (
Each vector timer VT0. Timer control signals TC, TC, are applied to VT, respectively.

When each vector timer v'r, , VT, is not inhibited by the timer control signal 'rco, TCI.

Count up the clock signal CLOCK.

In this way, vector timers VT,, VT, have
The execution time of the vector I/L instructions requested from the scalar units SU, , SU, to the vector unit VU-M is accumulated separately for each scalar unit.

[Effect]

According to the present invention, it is possible to measure only the net execution time excluding the waiting time until the vector instruction requested from the scalar unit to the vector unit is executed. When processing vector instructions in one shared vector unit,
Accurate vector instruction execution time can be measured for each SCARA unit, excluding the mutual influence of requests from each SCARA unit.

〔Example〕

FIG. 3 shows one embodiment of the present invention applied to the single system shown in FIG. 1, and the configuration shown in FIG.
This figure corresponds to an improved version of the vector control unit CU in the conventional example shown in the figure.

The correspondence between the reference numbers and components shown in FIG. 3 is as follows.

300: 5U 301: Bus for sending vector instructions 302: Control line for sending VUFull signal 310: Vector control unit VCU of vector unit VU-1 311: Instruction fetch stage register VFS312:
Instruction buffer VFR 313: Instruction fetch control section 314: Selector 5EL 315: Vector processor stage register PSR 316: Vector queue stage register VQR 317: Instruction management control section 318: Instruction decoder DEC 319: Timer control signal line 320: AND circuit 321: Vector timer VT 322: In clock signal line operation, vector instructions are sent to VF through bus 301.
Input to SR. If there is no instruction in the VPSR and the VPSR is empty, the instruction is moved from the VFSR to the VFSR. VPSR contains a preceding instruction or V
When the FB contains a preceding instruction, the instruction in the VFSR is sent to the VFR and temporarily held (puffered).

If there is an instruction in the VFB when the preceding instruction is sent from the VPSR and it becomes vacant, that instruction will be transferred from the VFB through the selector SEL to the VPSR at the 9th timing.
is input.

The above control is performed by the instruction fetch control unit 313.

VPSR is an instruction register for identifying instructions in the instruction decoder DEC. Also, VQSR.

This is an instruction register for controlling instruction transmission by the instruction management control unit.

The instruction instruction fetch control unit 313 controls instruction fetch, checks the degree of clogging of the VFB and the presence or absence of an instruction in the VPSR, and inputs the instruction to the VFB and VPSR and inputs the instruction to the selector SE.
When the VFB is full, a VU Full signal is sent to the SU via the control signal line 302 to stop the SU from sending out any more commands.

The instruction decoder DEC decodes instructions in the VPSR.

The command management control unit 317 controls the command transmission of commands in the VQSR based on decode information sent from the command decoder DEC and information from the VQSR.

The vector timer VT is a counter that counts up the clock signal CLOCK from the clock signal line 322 by +1. CLOCK is output from the AND circuit 3 by the timer control signal TC output from the instruction management control section 317.
At 20, the input of the vector timer VT is controlled.

The instruction management control unit 317 turns on the timer control signal TC only when a vector instruction is being executed.

FIG. 4 shows one embodiment of the present invention to which the multi-system shown in FIG. 2 is applied, and the configuration shown in FIG.
This is a corresponding example of an improved VU in the conventional example shown in the figure.

The correspondence between the reference numbers shown in FIG. 4 and the constituent elements is as follows.

400 Niskara Unit SU.

401 Niskara Unit SU.

405: Vector unit VU-M 406: Vector control unit VCU 411.421: Bus 412.42 for sending vector commands
2: Control signal line 413 that sends the VU Full signal that prohibits vector instruction sending. 423: Instruction fetch stage register V F
S Ro, V F S RI414.424: Instruction Hara 7 A” F B +l l V FB+ 415.425: Selector 5EL 416.426: Instruction instruction fetch control unit 417.42
7: Execution time vector timer VTEo, VTEI 430: Instruction switching control section 431: Selector 5EL 432: Instruction transmission buffer 433: Flag 434: Instruction management control section 435: Clock signal line 441.451: Waiting time vector timer VTW o
, V T W + 442.452: AND circuit 443.453: Control signal line that sends vector command interlock signal 444.454: Signal line in use by other SUs In operation, first VF is connected from SUo through bus 411.
Assume that a vector command is sent to SRo. At this time, if the instruction fetch stage register VFSRO is empty and the instruction switching control unit 430 is facing the SUa side,
It is transferred to the command transmission buffer 432 through the selector 5EL415 and the selector 5EL431.

When the flag 433 is O, it indicates a vector instruction from 5U (1), and when it is 1, it indicates a vector instruction from SU. This information is sent to the instruction management control unit 434.

The instruction management control unit 434 manages the state in which vector instructions from which scalar unit are being executed. At this time, depending on the contents of the flag 433, the execution time vector timer TE (1, VTEI) is selected and SUa, SO, and SO are measured separately.

When the buffer VFB0 is full, the instruction fetch control unit 416 sends a signal to the control signal line 412 to SU.
sends a signal through which the instruction is prohibited from being sent. The operation is the same for SU.

The command switching control unit 430 controls which SU to accept and accept commands from, and sends a signal via the control signal line 412 or 422 to the SU whose acceptance is prohibited. Further, it controls the selector 5EL431 and sets the flag 433.

In each SU, if a vector instruction appears after receiving the instruction sending prohibition signal, the sending of this instruction is prohibited, and the SO
Apply an interlock inside.

At this time, the control signal line 443 or 4
53 to send the vector instruction in clock signal.

On the VU side, a waiting time vector timer VT is set for each SU.
Wo has a VTWI, and the clock signal CLOCK is output from the AND circuit 442 or 452.
control the count up.

The AND circuit 442 receives the other SU that is sent from the instruction switching control unit 430 and indicates that SUA<VU of the current location is being used.
AN of busy signal and vector instruction in clock signal
Takes D logic and sends an output signal to VTWI.

This allows v'rwo to measure the period during which vector instructions from its own SU are stopped because other SUs are using the VU. A similar operation is performed for VTW.

These latency vector timers VTW, , V'r w
, when charging a program using CPU time, you can calculate the impact of CPU time due to other SUs using VU by subtracting the VTWI value from the CPU time. can be removed.

Furthermore, in a multi-system with multiple SUs,
In order to increase the overall efficiency of the system, the value of ■TW can be used to optimize the program scheduling control for each SU.

〔Effect of the invention〕

By knowing the execution time of a vector instruction, for example, the amount of time the vector unit operates in a job can be treated as separate billing.

Furthermore, when improving programs, by knowing the actual execution time of vector instructions, it is possible to create more efficient programs.

[Brief explanation of drawings]

FIG. 1 and FIG. 2 are diagrams showing the basic configuration of the present invention using a single system and a multi-system, respectively. FIG. 3 is a configuration diagram of an embodiment using a single system. FIG. 4 is a configuration diagram of an embodiment using a multi-system. FIG. 5 is an explanatory diagram of the speed-up effect of vector instruction processing. Fig. 6 is a block diagram of a conventional vector processor, Fig. 7 is a time chart showing a comparison of program execution of each ff (vector processor), Fig. 8 is a block diagram of a single system vU, and Fig. 9 is a block diagram of a conventional single system. Figure 10 is a diagram showing the configuration of a conventional multi-system VCU. In Figures 1 and 2. 110 Nisingle system vector unit P-1 120 Niscara unit 5U t3O: Vector unit ■υ 131: Instruction management control unit 132: Vector timer 133: Timer control signal TC 134: Clock signal CLOCK 21O: Multi-system vector processor PM 220.221 Niscara unit SU,, SU. 230: Vector unit VU- M 231: Command management control unit 232. 233: Pect 7L/Tie? V T 6
, V T 1234.235: Timer control signal TC
,,TC. 236: Clock signal CLOCK Fig. 1 Fig. 2 (A) (B) Nct I-Effect of combination of meeting seal No. 5f! 1 (Q) VP-1 11 ◆ Time mouth =: Ko Sukaku now Kintsu I 4 pH 1 W Oto Otsu Be 7 Toru 4 N 4' Haiku banquet ill 8 j to Lee! Hector 7'CN! zue 7'Q 7"riA banquet ↑πspicy Y
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figure

Claims (3)

[Claims] (1) In an information processing device consisting of a scalar unit that processes scalar instructions and a vector unit that processes vector instructions requested from the scalar unit, the vector unit has a vector timer ( 132), and prohibits the vector timer (132) from counting up during a period when the vector unit is not executing the vector instruction requested to be processed by the scalar unit. A vector instruction execution time measurement method characterized in that a vector timer (132) can measure only the time during which vector instructions are being executed. (2) a plurality of scalar units that process scalar instructions;
In an information processing device consisting of a vector unit that processes vector instructions requested by these scalar units, the vector unit has one vector timer (232, 233) for each scalar unit that counts up the clock during operation. A vector timer (232,
233) controls so that the count-up operation is prohibited except during the period when the vector instruction requested by the corresponding scalar unit to the vector unit is executed, and the vector unit is requested for each scalar unit. A vector instruction execution time measurement method characterized in that only the time during which vector instructions are executed can be measured by each vector timer (232, 233). (3) The vector unit further includes one latency vector timer (441, 4) for each scalar unit.
51) and each waiting time vector timer (441,
451) prohibits the count-up operation except during the period when the execution of the vector instruction requested by the corresponding scalar unit to the vector unit is awaited by the execution of the vector instruction requested to the vector unit by another scalar unit. Execution time measurement of a vector instruction according to claim 2, characterized in that the execution time measurement of a vector instruction according to claim 2 is characterized in that the execution time of a vector instruction is controlled such that the time required for each scalar unit to wait for other scalar units can be measured. method.