JPS62245663A - Semiconductor device - Google Patents
Semiconductor deviceInfo
- Publication number
- JPS62245663A JPS62245663A JP61089301A JP8930186A JPS62245663A JP S62245663 A JPS62245663 A JP S62245663A JP 61089301 A JP61089301 A JP 61089301A JP 8930186 A JP8930186 A JP 8930186A JP S62245663 A JPS62245663 A JP S62245663A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- conductor
- capacitor
- grounding
- semiconductor chip
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 44
- 239000003990 capacitor Substances 0.000 claims abstract description 49
- 239000004020 conductor Substances 0.000 claims abstract description 37
- 239000000758 substrate Substances 0.000 claims abstract description 32
- 239000000463 material Substances 0.000 claims abstract description 15
- 239000002184 metal Substances 0.000 claims description 15
- 238000005219 brazing Methods 0.000 claims description 14
- 238000006243 chemical reaction Methods 0.000 description 3
- 230000002265 prevention Effects 0.000 description 3
- 230000000694 effects Effects 0.000 description 1
- 239000000945 filler Substances 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/13—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body combined with thin-film or thick-film passive components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48135—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/48137—Connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being arranged next to each other, e.g. on a common substrate
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/4847—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond
- H01L2224/48472—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a wedge bond the other connecting portion not on the bonding area also being a wedge bond, i.e. wedge-to-wedge
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Structures For Mounting Electric Components On Printed Circuit Boards (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は半導体装置に関し、特に高周波高出力用トラン
ジスタとチップコンデンサを含むインピーダンス変換回
路とを有する半導体装置に関する。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device, and particularly to a semiconductor device having an impedance conversion circuit including a high-frequency, high-output transistor and a chip capacitor.
高周波高出力トランジスタを含む半導体装置は、通常、
トランジスタの入力インピーダンスが小さい為に、パッ
ケージ内部にチップコンデンサの容量とボンティング線
のインダクタンスとでインピーダンス変換回路を構威し
２、こわをトランジスタの入力に接続して外部回路との
インピーダンス整合を取り易くしている。Semiconductor devices that include high-frequency, high-power transistors usually
Since the input impedance of the transistor is small, an impedance conversion circuit is constructed inside the package using the capacitance of the chip capacitor and the inductance of the bonding wire2, and the impedance is connected to the input of the transistor to achieve impedance matching with the external circuit. I'm making it easy.
第３図は従来の半導体装置の一例の斜視図である。FIG. 3 is a perspective view of an example of a conventional semiconductor device.
第３図に示すように、従来例は金属の接地用導体１′上
に熱伝導のよい絶縁基板２が設けられ、そ−スミ極のポ
ンディングパッド５及びエミッタ電極のボンディングパ
ット６をボンディング線７′及び８′によってそれぞれ
接地用導体１′の接続領域１３及びチップコンデンサの
容量電極１１′に接続し、更に容量電極１１′はボンデ
ィングｍ１２′によって外部の入力端子へ接続した構造
をしている。As shown in FIG. 3, in the conventional example, an insulating substrate 2 with good thermal conductivity is provided on a metal grounding conductor 1', and a bonding pad 5 of a summation electrode and a bonding pad 6 of an emitter electrode are connected with bonding wires. 7' and 8' are connected to the connection area 13 of the grounding conductor 1' and the capacitor electrode 11' of the chip capacitor, respectively, and the capacitor electrode 11' is further connected to an external input terminal by bonding m12'. .
ここで、ベース電極を接地するためのボンディング線７
′のインダクタンスが大きいと、この半導体装置の電力
利得が低下するので、ボンディング線７′の長さは出来
るだけ短かぐすることが好ましい。即ち、第３図に示す
ように、ボンディング線７′は金属の接地用導体１′の
最も半導体チップ３に近い所に接続している。Here, bonding wire 7 for grounding the base electrode
If the inductance of bonding line 7' is large, the power gain of this semiconductor device will decrease, so it is preferable to make the length of bonding line 7' as short as possible. That is, as shown in FIG. 3, the bonding wire 7' is connected to the metal grounding conductor 1' at the point closest to the semiconductor chip 3.
又、このような半導体装置では、チップコンデンサの容
量１１椿９’を金属の接地用導体１′に固着する際にＡ
ｕＳ ｉ系のろう材を用いるが、通常、ろう材はチップ
コンデンサの底面の大きさより広がる。In addition, in such a semiconductor device, A
A uS i-based brazing material is used, and the brazing material is usually wider than the size of the bottom surface of the chip capacitor.
しかも、ろう材が付着した箇所にボンディング線をボン
ディングしてもはがれるので、従来例の半導体装置では
ろう材が接続領域１３に広がらないようにチップコンデ
ンサとボンディング線の接続領Ｍ１３との間にけろう材
の流れ止め溝１４を設けている。Moreover, even if the bonding wire is bonded to a place where the brazing material has adhered, it will peel off, so in conventional semiconductor devices, the soldering material should be placed between the chip capacitor and the connection region M13 of the bonding wire so that the brazing material does not spread to the connection region 13. A flow prevention groove 14 for the brazing material is provided.
上述し九従来の半導体装置は、接続領域１３とチップコ
ンデンサとの間にろう材の流れ止め溝１４を設けるため
に、チップコンデンサと半導体チップとの距離が遠くな
シ、従って、トランジスタのエミッタ電極のポンディン
グパッド５とチップコンデンサの電極１１′とを結ぶボ
ンディングａ８’の長さが増しこの部分のインダクタン
スが増大して高周波特性が損なわれるという欠点がある
。In the nine conventional semiconductor devices described above, in order to provide the brazing material flow prevention groove 14 between the connection region 13 and the chip capacitor, the distance between the chip capacitor and the semiconductor chip is long, and therefore the emitter electrode of the transistor is The disadvantage is that the length of the bonding a8' connecting the bonding pad 5 and the electrode 11' of the chip capacitor increases, and the inductance of this portion increases, impairing high frequency characteristics.
更に又、この例の半導体装置では、ボンディングをする
部分の接続領域１３とトランジスタのポンディングパッ
ド５．６及びチップコンデンサの電極１１′との高さが
異なるので、ボンディング線８′を短かくしようとして
接続領域１３とチップコンデンサ及び半導体チップとを
近接しすぎると、今度は、ボンディングの作業性が非常
に悪くなるという欠点もある。Furthermore, in the semiconductor device of this example, the heights of the bonding area 13, the transistor bonding pad 5.6, and the chip capacitor electrode 11' are different, so the bonding line 8' should be shortened. However, if the connection region 13 and the chip capacitor or semiconductor chip are placed too close to each other, there is also the drawback that the bonding workability becomes extremely poor.
本発明の目的は、トランジスタとチップコンデンサとを
接続するボンディング線の長さが短かく高周波特性に優
れかつボンディングの作業性も良い半導体装置を提供す
ることにある。SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device that has short bonding lines connecting a transistor and a chip capacitor, has excellent high frequency characteristics, and has good bonding workability.
本絹１の発明の半導体装置は、接地用導体上に設けられ
た絶縁基板と、該絶縁基板上に設けられた導電膜と、該
導電膜上に設けられかつトランジスタを内蔵する半導体
チップと、誘電体基板の裏面に設けられた第１の容量電
極が前記接地用導体に接続固着され前記誘電体基板の表
面でかつ前記半導体チップに近い側に設けられた接地用
電極と前記半導体チップから遠くなる側に設けられた第
２の容量電極と前記第１の容量電極と接地用電極とを前
記誘電体基板側面で接続する接続導体とから成るチップ
コンデンサと、前記トランジスタのエミッタ（又はベー
ス）と前記第２の容量電極とを接続する金属線と、前記
トランジスタのベース（又はエミッタ）と前記接地電極
とを接続する金属線とを含んで構成される。The semiconductor device of the invention of Honkin 1 includes: an insulating substrate provided on a grounding conductor, a conductive film provided on the insulating substrate, a semiconductor chip provided on the conductive film and containing a transistor; A first capacitor electrode provided on the back surface of the dielectric substrate is connected and fixed to the grounding conductor, and a first capacitor electrode provided on the surface of the dielectric substrate close to the semiconductor chip and a first capacitor electrode provided on the surface of the dielectric substrate close to the semiconductor chip and a first capacitor electrode provided on the side far from the semiconductor chip. a chip capacitor comprising a second capacitor electrode provided on a side facing the dielectric substrate, a connecting conductor connecting the first capacitor electrode and a grounding electrode on a side surface of the dielectric substrate; and an emitter (or base) of the transistor. It is configured to include a metal line connecting the second capacitor electrode and a metal line connecting the base (or emitter) of the transistor and the ground electrode.
本絹２の発明の半導体装置は、接地用導体上に設けられ
た絶縁基板と、該絶縁基板上に設けられた導電膜と、該
導電膜上に設けられかつトランジスタを内蔵する半導体
チップと、誘電体基板の裏面に設けられた第１の容量電
極が前記接地用導体に接続固着され前記誘電体基板の表
面でかつ前記半導体チップに近い側に設けられた接地用
型、極と前記半導体チップから遠くなる側に設けられた
第２の容量電極と前記第１の容ｆ冒極と接地用電極とを
前配防雷体基板側面で接続する接続導体と前記接地用電
極と前記接続導体との境界の表面に設けられたろう材の
クリープ防止用のストッパとから成るチップコンデンサ
と、前記トランジスタのエミッタ（又はベース）と前記
第２の容量電極とを接続する金属線と、前記トランジス
タのベース（又はエミッタ）と前言己接地電極とを接続
、する金属線とを含んで楢成される。The semiconductor device of the invention of Honkin 2 includes: an insulating substrate provided on a grounding conductor, a conductive film provided on the insulating substrate, a semiconductor chip provided on the conductive film and containing a transistor; A first capacitor electrode provided on the back surface of the dielectric substrate is connected and fixed to the grounding conductor, and a grounding mold and pole provided on the surface of the dielectric substrate and on the side closer to the semiconductor chip, and the semiconductor chip. A connecting conductor that connects a second capacitive electrode provided on a side far from the first capacitive electrode and the grounding electrode on a side surface of the front lightning protection board, and the grounding electrode and the connecting conductor. a chip capacitor consisting of a stopper for preventing creep of the brazing material provided on the boundary surface of the transistor, a metal wire connecting the emitter (or base) of the transistor and the second capacitor electrode, and a base (or base) of the transistor; (or emitter) and a metal wire connecting the ground electrode.
〔実施例）
次に、本第１及び第２の発明の一実施例について図面を
参照して説明する。[Example] Next, an example of the first and second inventions will be described with reference to the drawings.
第１図は本第１の発明の半導体装置の一実施例の斜視図
である。FIG. 1 is a perspective view of an embodiment of the semiconductor device of the first invention.
第１図に示すように、この半導体装置は、金属の接地用
導体１上に熱伝導のよい絶縁基板２が固着され、その土
に半導体チップ３が、導電膜４を介して設けられ、半導
体チップ３上に形成されたトランジスタのベース電極の
ポンディングパッド５及びエミッタ１極のボンディング
パット６がらそれぞれボンディング線７及び８を介して
金属の接地用導体１上に容量１１ｉ＠ｌｊ９が接続固着
されたチップコンデンサ上に設けた接地用電極１５及び
容量電極１１に接続されている。更に、容量電極１１は
ボンディング線１２を通じて外部の大刀端子と接続され
ている。ここで、チップコンデンサ上の接地用電極１５
（サチップコンデンサ側面の接続導体１６を介して裏面
の容量電極９と接続しているので、金属の接地用導体１
を通じて電気的に接地される。As shown in FIG. 1, in this semiconductor device, an insulating substrate 2 with good thermal conductivity is fixed on a metal grounding conductor 1, a semiconductor chip 3 is provided on the ground with a conductive film 4 interposed therebetween, and the semiconductor A capacitor 11i@lj9 is connected and fixed on the metal grounding conductor 1 through bonding lines 7 and 8, respectively, from the bonding pad 5 of the base electrode of the transistor formed on the chip 3 and the bonding pad 6 of one emitter pole. It is connected to a grounding electrode 15 and a capacitor electrode 11 provided on the chip capacitor. Furthermore, the capacitor electrode 11 is connected to an external long sword terminal through a bonding wire 12. Here, the grounding electrode 15 on the chip capacitor
(Since it is connected to the capacitive electrode 9 on the back side via the connecting conductor 16 on the side surface of the subchip capacitor, the metal grounding conductor 1
electrically grounded through.
第２図は本第２の発明の半導体装置の一実施例に使用す
るチップコンデンサの斜視図である。FIG. 2 is a perspective view of a chip capacitor used in an embodiment of the semiconductor device of the second invention.
このチップコンデンサは、誘電体基板１ｏの裏面に容量
電極９を設け、誘電体基板１ｏの表面に容量電極１１と
接地用電ｔｊ＃１５とを設しナ、接地用電極１５と容量
電極９とを誘電体基板１０の側面を通じて接続する接続
導体］６を設け、更に接地用電極１５と接続導体１６と
の境界の表面にろう材のクリープ防止用のストッパ１７
を設けた構造をしている。In this chip capacitor, a capacitive electrode 9 is provided on the back surface of a dielectric substrate 1o, a capacitive electrode 11 and a grounding electrode tj#15 are provided on the surface of the dielectric substrate 1o, and a capacitive electrode 9 is provided on the surface of the dielectric substrate 1o. A connecting conductor] 6 is provided to connect the grounding electrode 15 and the connecting conductor 16 through the side surface of the dielectric substrate 10, and a stopper 17 for preventing creep of the brazing material is provided on the surface of the boundary between the grounding electrode 15 and the connecting conductor 16.
It has a structure with
このろう材のクリープ防止用のストッパ】７ｕ。This stopper for preventing creep of the brazing filler metal]7u.
チップコンデンサを金属の接地用導体１に同着する際に
用いるろう材が、ろう材の種類や作業条件によっては、
裏面から側面の接続導体１６を通じて接地用電極１５に
向って這い上るいわゆるクリープ現象が起こり、ろう材
が接地用電極１５に付着してボンディングの接続が出来
なくなることを防ぐために設けたものである。The brazing material used to attach the chip capacitor to the metal grounding conductor 1 may vary depending on the type of brazing material and working conditions.
This is provided to prevent a so-called creep phenomenon in which the brazing material creeps up from the back surface toward the grounding electrode 15 through the side surface connection conductor 16 from adhering to the grounding electrode 15 and making it impossible to make a bonding connection.
〔発明の効果〕
以上説明したように本発明は、入力インピーダンス変換
用のチップコンデンサとして側面に設けた接続導体によ
シ接地用導体と電気的に接続された接地用電極と容量！
極とを表面に備えたものを使用することによって、従来
例の接地導体に設けられていたろう材流れ止め溝が不要
になると共にボンディング線を接続するチップコンデン
サの容量電極、接地用電極及び半導体チップ表面のトラ
ンジスタのポンディングパッドをほぼ同一の平面上に近
接して配置することができて、ボンディングの作業性が
良くしかもボンディング線が短く高周波特性の優ねた半
導体装置を提供することができるという効果がある。[Effects of the Invention] As explained above, the present invention is a chip capacitor for input impedance conversion that uses a grounding electrode and a capacitor that are electrically connected to a grounding conductor through a connecting conductor provided on the side surface!
By using a capacitor with electrodes on the surface, there is no need for the brazing material flow prevention groove provided in the conventional ground conductor, and the capacitance electrode of the chip capacitor to which the bonding wire is connected, the ground electrode, and the semiconductor chip can be used. The bonding pads of the transistors on the front surface can be placed close together on almost the same plane, making it possible to provide a semiconductor device with good bonding workability and short bonding lines and excellent high-frequency characteristics. effective.
第１図は本第１の発明の半導体装置の一実施例の斜視図
、第２図は本第２の発明の半導体装置の一実施例に使用
するチップコンデンサの斜視図、第３図は従来の半導体
装置の一例の斜視図である。
１、ｌ′・・・・・・接地用導体、２・・・・・・絶縁
基板、３・・・・・・半導体チップ、４・・・・・・導
電膜％ ５．６・・・・・・ポンチインクパッド、
７． ７’、 ８． ８’・・・・・・ボンディング
線、９． ９’・・・・・・容量側Ｌ １０．１０′・
・・・・・ｖｊｗ体基板基板１．１１’・・・・・・容
量電極、１２．１２’・・・・・・ボンディング線、１
３・旧・・接続領域、１４・旧・・流れ止め溝、１５・
・・・・・接地用電極、１６・・川・接続導体、１７・
・・・・・ストッパ。
代罪人 弁理士 内 原 晋、・−亀一替゛、”
ビ、“１
緊１ 図FIG. 1 is a perspective view of an embodiment of the semiconductor device of the first invention, FIG. 2 is a perspective view of a chip capacitor used in an embodiment of the semiconductor device of the second invention, and FIG. 3 is a conventional one. 1 is a perspective view of an example of a semiconductor device; FIG. 1, l'...Grounding conductor, 2...Insulating substrate, 3...Semiconductor chip, 4...Conductive film% 5.6... ... Punch ink pad,
7. 7', 8. 8'...Bonding wire, 9. 9'...Capacity side L 10.10'・
...vjw body substrate substrate 1.11'...capacitance electrode, 12.12'...bonding wire, 1
3. Old... connection area, 14. old... flow stop groove, 15.
...Grounding electrode, 16. River/connection conductor, 17.
...Stopper. Representative guilty patent attorney Susumu Uchihara, Kame Kazue.”
B, “1 Urgent 1 Figure
Claims (2)
板上に設けられた導電膜と、該導電膜上に設けられかつ
トランジスタを内蔵する半導体チップと、誘電体基板の
裏面に設けられた第１の容量電極が前記接地用導体に接
続固着され前記誘電体基板の表面でかつ前記半導体チッ
プに近い側に設けられた接地用電極と前記半導体チップ
から遠くなる側に設けられた第２の容量電極と前記第１
の容量電極と接地用電極とを前記誘電体基板側面で接続
する接続導体とから成るチップコンデンサと、前記トラ
ンジスタのエミッタ（又はベース）と前記第２の容量電
極とを接続する金属線と、前記トランジスタのベース（
又はエミッタ）と前記接地電極とを接続する金属線とを
含むことを特徴とする半導体装置。(1) An insulating substrate provided on a grounding conductor, a conductive film provided on the insulating substrate, a semiconductor chip provided on the conductive film and containing a transistor, and a semiconductor chip provided on the back surface of a dielectric substrate. A first capacitive electrode is connected and fixed to the grounding conductor, and a grounding electrode is provided on the surface of the dielectric substrate on the side closer to the semiconductor chip, and a first capacitor electrode is provided on the side farther from the semiconductor chip. 2 capacitor electrode and the first
a chip capacitor consisting of a connecting conductor connecting the capacitive electrode and the grounding electrode on the side surface of the dielectric substrate; a metal wire connecting the emitter (or base) of the transistor to the second capacitive electrode; The base of the transistor (
or an emitter) and a metal wire connecting the ground electrode.
板上に設けられた導電膜と、該導電膜上に設けられかつ
トランジスタを内蔵する半導体チップと、誘電体基板の
裏面に設けられた第１の容量電極が前記接地用導体に接
続固着され前記誘電体基板の表面でかつ前記半導体チッ
プに近い側に設けられた接地用電極と前記半導体チップ
から遠くなる側に設けられた第２の容量電極と前記第１
の容量電極と接地用電極とを前記誘電体基板側面で接続
する接続導体と前記接地用電極と前記接続導体との境界
の表面に設けられたろう材のクリープ防止用のストッパ
とから成るチップコンデンサと、前記トランジスタのエ
ミッタ（又はベース）と前記第２の容量電極とを接続す
る金属線と、前記トランジスタのベース（又はエミッタ
）と前記接地電極とを接続する金属線とを含むことを特
徴とする半導体装置。(2) An insulating substrate provided on a grounding conductor, a conductive film provided on the insulating substrate, a semiconductor chip provided on the conductive film and containing a transistor, and a semiconductor chip provided on the back surface of the dielectric substrate. A first capacitive electrode is connected and fixed to the grounding conductor, and a grounding electrode is provided on the surface of the dielectric substrate on the side closer to the semiconductor chip, and a first capacitor electrode is provided on the side farther from the semiconductor chip. 2 capacitor electrode and the first
A chip capacitor comprising a connecting conductor connecting a capacitance electrode and a grounding electrode on a side surface of the dielectric substrate, and a stopper for preventing creep of a brazing material provided on a boundary surface between the grounding electrode and the connecting conductor. , comprising a metal line connecting the emitter (or base) of the transistor and the second capacitor electrode, and a metal line connecting the base (or emitter) of the transistor and the ground electrode. Semiconductor equipment.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61089301A JPS62245663A (en) | 1986-04-17 | 1986-04-17 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP61089301A JPS62245663A (en) | 1986-04-17 | 1986-04-17 | Semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62245663A true JPS62245663A (en) | 1987-10-26 |
Family
ID=13966846
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP61089301A Pending JPS62245663A (en) | 1986-04-17 | 1986-04-17 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62245663A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5701033A (en) * | 1995-03-20 | 1997-12-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
-
1986
- 1986-04-17 JP JP61089301A patent/JPS62245663A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5701033A (en) * | 1995-03-20 | 1997-12-23 | Mitsubishi Denki Kabushiki Kaisha | Semiconductor device |
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