JPS62245594A - Data writing method for dynamic memory - Google Patents

Abstract

PURPOSE:To attain a lump writing to a dynamic (D) memory with a simple constitution by controlling the writing to a static (S) and the lump impressing of data to a bit line by a corresponding timing signal or the like corresponding to the sequence of change of a control signal. CONSTITUTION:When a row address, a column address, a writing control signals; the inverse of RAS, the inverse of CAS and the inverse of WE respectively are applied, a timing signal generating circuit 9 outputs the timing signals phiS, phiWE, phiSA or the like corresponding to the sequence in the change of the signals. When an FET6 is turned on by the column address CL, an FET4 is turned off by the signal phiS, the S memory is separated from the bit line pair BL, the inverse of BL and the data is written through a data output buffer 7, a writing circuit 8 or the like. Similarly, when an FET6 is turned off, the FET4 is turned on, the memory 5 is connected to the bit line pair BL, the inverse of BL, and the contents of the memory 5 are entirely written through a sense amplifier 1 in the D memory 3 at high speed with the simple constitution requiring no increase in the number of terminals.

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a data writing method for a dynamic memory (D-RAM), and in particular, it relates to a method for writing data into a dynamic memory (D-RAM), and in particular, to a dynamic memory (D-RAM) that has a built-in static memory that statically stores data read from memory cells. The present invention relates to a D-RAM data writing method.

(b) Conventional technology In general, in a D-RAM, a large number of memory cells selected by a word line are connected to a pair of bit lines each connected to a large number of sense amplifiers, and each pair of bit lines is selected by a column address. The structure is such that it can be connected to the input/output bus connected to the data output buffer and write circuit, and read and write operations are performed using externally applied row address control signal RAS, column address control signal σX1, and write The timing is controlled by various timing signals outputted from the timing generation circuit based on the control signal W1.

By the way, it is well known that the D-RAM mentioned above has read modes called page mode and nibble mode. Furthermore, in recent years, a static column read mode has been developed that allows data at an arbitrary column address within the same row address to be retrieved at high speed. In each of the data reading methods of the page mode, nibble mode, and static column method, reading the first bit of data after setting the row address is almost the same, and reading data from the second bit onward is different. There is. FIG. 3(a) is a timing diagram showing the basic reading method.

In FIG. 3(a), when the row address control signal R-AS falls while the row attos is applied, the row address is fetched, and the memory cells connected to the word line selected by the row address are Data is read to each bit line by the sensing operation of the sense amplifier. Then, when the address control signal dAs falls with the column address applied, the column address is taken in, and the bit line specified by the address is connected to the input/output bus, and the data on the bit line is is output from the data output buffer to the input/output terminal.

On the other hand, data writing is the same in each of the page mode, nibble mode, and static column method, and is written as shown in FIG. 3(b). Figure 3 (b>
In this case, when the row address control signal RAS falls with the row address applied, the memory cell selected by the word line is read out to the bit line in the same way as described above. Next, at the falling edge of either the column address control signal CAS or the write control signal WE, whichever is later, the column address and data input are taken in, and the bit line selected by the column address is connected to the input/output bus. The write circuit applies a signal based on the data input to the selected bit line via the input/output bus to forcibly change the state of the sense amplifier and the bit line. This results in
Data can be written.

Regarding reading and writing of such data,
This is detailed in the article published on pages 153 to 174 of "Nikkei Electronics" published on September 12, 1988.

(c) Problems to be Solved by the Invention The above-mentioned D-RAM requires an operation to periodically refresh the memory cells, but there is a restriction that column address access is prohibited during the refresh operation. Therefore, by providing a static memory cell on each of a pair of bit lines, storing the data read to the bit line in each static memory cell, and then separating the bit line and static memory cell, the data can be stored even during refresh operation. D- which enables column address access
RAM has been developed. Even in this D-RAM,
Data writing is performed in the same manner as shown in FIG. 3(b). That is, when the column address control signal CAS or the write control signal WE falls, whichever is later, the bit line and static memory cell selected by the column address are connected to the input/output bus, and the write circuit forces them simultaneously. It has been rewritten as . However, this writing method does not take full advantage of the characteristics of static memory cells. That is, static memory cells can be separated from bit lines, so D-RAM
It is possible to write data independently of each section, and to write data in a batch from static memory cells to memory cells in the D-RAM section. To achieve this functionality,
Control signals are required to control each write mode, the number of external terminals increases, and there are problems in terms of compatibility and versatility with conventional D-RAMs.

(D) Means for Solving the Problems The present invention has been made in view of the above-mentioned points, and the present invention has been made in view of the above-mentioned points. When the third control signal change (WE falls) after the first control signal change (R\S falls), the static memory cell and the bit line are separated and selected by the column address. When data is written to a static memory cell that has been previously set, and the first control signal changes after the third control signal changes,
A static memory cell is connected to a bit line, a sense amplifier performs a sensing operation, and data stored in the static memory cell is written to the memory cell all at once.

(*) Effect According to the above method, the first control signal (RAg), the second
control signal (σX1 or S), and a third control signal (
Normal read mode that can be controlled by Wl), CA
S (CS) before R In order to distinguish between refresh mode, RAS only refresh mode, etc., the static memory cell is The third control signal (WE
) After the change in the first control signal (RAS), the batch write mode is set from the static memory cells to the memory cells in the D-RAM section, thereby making it possible to control the write mode without adding external terminals. Become.

(f) Example FIG. 1 is a circuit diagram showing an embodiment of the present invention.

The n sense amplifiers (1) arranged in a column are flip-flop type sense amplifiers, and timing signals φ and A are applied to the gates of MOSFETs (2) connected to each sense amplifier (1). The sensing operation is controlled by Each sense amplifier (1) has a pair of bit lines BLi and BLi (i=1.2,
......n) is connected.

This bit line BLi and the word line Wj (j=1.2,...
. . . The memory cell (3) selected by m) is arranged. Further, at the ends of the bit lines BLi and 111, there is a MOSFE to which a timing signal φ is applied to the gate.
A static memory cell (5) is connected via T(4), and a column selection signal line CLi which has a high voltage level according to the column address is connected between the static memory cell (5) and input/output buses I10 and Ilo. (iwl,
2. MOS F where n) is incorrectly applied to the gate
ET(6) is connected.

The input/output buses I10 and Ilo have data output buffers (
7) and a write circuit (8) are connected. Here, the memory cell (3) is a well-known dynamic memory cell consisting of a capacitor and a MOS FET, while the static memory cell (5) is a cell consisting of two inverters whose inputs and outputs are connected to each other. .

A timing generation circuit (9) that controls read and write operations, etc. includes a RAS system timing circuit (10) that inputs a row address control signal RAg, and a CAS system timing circuit (10) that inputs a ram address control signal CAS (or convex). It consists of a timing circuit (11) and a WE system timing circuit (12) that inputs the write control signal WE, and each circuit (10), (11), and (12) receives each control signal RAS, CAS, and WE. A control signal C to control the generation of multiple timing signals according to the order of change.
RAS, CcAs, and Cwl are fully applied. Also,
The CAS timing circuit (11) and the WE timing circuit (12) include an AT that detects column address transitions.
The signal ATD from the D circuit (13) is no longer applied. R
The AS system timing circuit (10) receives a row address, and based on the row address, outputs a timing signal -WLs sense amplifier (10) that sets the word line Wj to a high voltage level.
The timing signal -9 that controls the sensing operation in 1) and the timing signal φ9 that controls the MOSFET (4) are created, and the CAS timing circuit (11) is
A timing signal -6L that sets the column selection signal CLi to a high voltage level based on the column address, and a timing signal φ that controls the operation of the output buffer (7). Further, the WE system timing circuit (12) is a write circuit that takes in the data applied to the data input/output terminal (14) and outputs a complementary signal based on the data to the input/output bus I10 and port. Timing signal 4□ to control (8)
etc.

FIGS. 2(8) to 2(c) are timing diagrams showing the operation of the circuit shown in FIG. 1, and the operation will be explained below.

FIG. 2(a) shows the case of normal read operation,
First, when the row address control signal RAS falls while a row address is applied, the row address is taken in, and the word line Wj based on the row address goes high according to the timing signal -WL from the RAS system timing circuit (10). voltage level. A weak potential difference is generated between each bit line BLi and BLi by the memory cell (3) connected to this word line Wj, and this potential difference causes the sense amplifier (1) to operate according to the timing signals φ and A. The amplification is false due to the amplification. Then, when the column address control signal CAS falls, the control signal CCAS output from the CAS timing circuit (11) causes the R
Timing signal -5 from AS system timing circuit (10)
is output, MOSFET (4) turns on,
The data read to the bit lines BLi and BLi is applied to the static memory cell (5) and stored. Then MOS FET (4) is turned off and bit 1iB
I, i and BLi and the static memory cell (5) are separated. Furthermore, when the column selection signal CLi based on the column address becomes a high voltage level due to the timing signal φ0 output from the CAS timing circuit (11), the selected MOSFET (6) is turned on and the static memory cell (5 ) data is input/output bus I10.
and Ilo, and a timing signal φ. , the signal is output from the output buffer (7) to the input/output terminal (14). After that, if the column address control signal σx1 is in the low state, the ATD
The timing signal φ is generated by the signal ATD from the circuit (13).
CL and φ. , is output from the CAS timing circuit (11), and data of the selected static memory cell (5) is output from the output buffer (7) in the same manner as described above.

FIG. 2(b) is a timing diagram when writing data to the static memory cell (5). After the row address control signal RAS falls, the write control signal WE
bring down. At this time, row address control signal RAS
With the fall of , the same read operation to the memory cell (3) and write operation to the static memory cell (5) as described above are performed. Furthermore, if the column address control signal CAS falls as shown by the broken line before the write control signal WE falls, the timing signal from the CAS system timing circuit (11) ≠ CL, as in FIG. 2(a), After the data of the static memory cell (5) selected by the column address is output via the input/output buses I10 and 110, the write mode is entered. That is, it is a read-modify-write mode. - Column address control signal CA after write control signal WE falls
When S is brought down, it immediately enters write mode and data based on the fetched column address is not output, but is written to the static memory cell (5) selected by the column address. . That is, when the write control signal WE falls, the write circuit (8) generates a complementary signal based on the data applied to the input/output terminal (14) by the timing signal -□ output from the WE system timing circuit (12). is output to the input/output bus I10 and the vortex.Furthermore, due to the fall of the column address control signal CAS and the control signal CW! indicating that the write mode is in effect, the timing signal -CL is output from the CAS system timing circuit (11). Therefore, the column selection signal CLi based on the column address becomes a high voltage level, the selected MOSFET <6) is turned on, and the input/output bus I10 and Ilo
The data output to is applied and stored. For writing after the 2nd bit, AT is applied every time a column address is applied.
CA by the signal ATD output from the D circuit (13).
Timing signal φCL from S-system timing circuit (11)
is output, so data is written into the static memory cell (5) selected by the column address in the same way as described above.

FIG. 2(c) shows that the data written in the static memory cell (5) as shown in FIG. 2(b) is transferred to the memory cell (5).
3) is a timing diagram when writing to column address F. After the write control signal WE falls, the column address F address control signal C
Row address control signal R with AS at high voltage level
Shut down AS. The WE system timing circuit (12) is
After the write signal W1 falls, the row address control signal RAS falls, thereby outputting the control signal C□.

In response to this control signal Cwll, a timing signal≠5 is first output from the CAS timing circuit (11), so the MOSFET (4) is turned on and the static memory cell (5) is connected to the bit lines BLi and BLi.

As a result, a potential difference occurs between the voltages precharged to the bit lines BLi and BLi based on the state of the static memory cell (5). Next, the word line Wj specified by the row address fetched by the fall of the row address control signal RAS is connected to the RAS system timing circuit (
10) is set to a high voltage level according to the timing signal φWL from the word line Wj, and the memory cell (3
) are connected to bit lines BLi and BLi. At this time, bit lines BLi and [i are static memory cells (
5) Since the potential difference has been expanded due to this, the memory cell (3) is forced into that state. Furthermore, R
When the timing signal output from the AS system timing circuit (10) and finally the sense amplifier (1) performs a sensing operation, the potential difference between the bit lines BLi and BLi is amplified and expanded, and the state can be secured.
A voltage is applied to each memory cell (3), and data is written to the memory cell (3). As a result, the data stored in the static memory cell (5) can be collectively specified by the row address in the memory cell (
3).

As shown in FIG. 2 (8), (b), and (c), the mode in which data is written to the static memory cell (5) is determined depending on the timing of the fall of the externally applied control signals RAS, CAS, and Wl. Static memory cell (5)
It is possible to control the mode in which data is written all at once to the memory cells (3) of the D-RAM section.

(G) Effects of the Invention As described above, according to the present invention, the data writing function of a D-RAM incorporating static memory cells is increased.
This has the advantage that a D-RAM that is easy to use can be obtained, and that data writing speed can be shortened because batch writing can be performed.

[Brief explanation of drawings]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 (a> to FIG. 2(e) are timing diagrams showing the operation of the circuit diagram shown in FIG. 1, and FIG. 3(a) and (b) are timing diagrams showing conventional examples. (1)... sense amplifier, (2) (4) (6)...
・MOS FET, (3>... memory cell,
(5) Static memory cell, (7) Data output buffer, (8) Write circuit, (9
)...Timing generation circuit, (10)...RAS system timing circuit, (11)...CAS system timing circuit, (12)...WE system timing circuit, (1
3)...ATD circuit, (14)...Input/output terminal. Applicant Sanyo Electric Co., Ltd. and one other agent Patent attorney Takuji Nishino and one other person Figure 1 Figure 2 [3 (a) Figure 2 (b)
Figure 3 (G) Figure 3 (b)

Claims (1)

[Claims] 1. A pair of bit lines each connected to a large number of sense amplifiers, and a second MOSFET to which the pair of bit lines are connected via a first MOSFET and controlled by a column address selection signal line. A static memory cell to which an input/output signal line is connected, a write circuit that sends a write signal to the input/output signal line, and a read operation based on at least first, second, and third control signals applied from the outside. and a timing signal generation circuit that generates a plurality of timing signals for controlling write operations, etc. In the data write method for a dynamic memory, the second (or third) control signal is changed after the first control signal changes.
When the control signal of the first M is changed, the write circuit sends write data to the input/output signal line by the timing signal from the timing generation circuit.
With the OSFET turned off, the second MOSFET selected by the column address is turned on to write data to the static memory cell, and further, the first control signal changes after the third control signal changes. When I did,
A data writing method for a dynamic memory, characterized in that the first MOSFET is turned on by a timing signal from the timing generation circuit, and data stored in the static memory cell is applied to the bit line all at once.