JPS62245575A - Memory device - Google Patents

Abstract

PURPOSE:To efficiently use the memory capacity of a memory device by receiving writing data supplied from a floppy disk controller, detecting an added prescribed data mark, extracting only a writing signal and storing. CONSTITUTION:The memory device MD is provided to a host system HS. The reading circuit RD of the device MD receives a sector address corresponding to the access of a magnetic bubble memory device MBM, adds a prescribed pattern signal R constituting an ID field written in a ROM2 so as to have a prescribed format and transmits to the floppy disk controller (FDC). A writing circuit WR receives the writing signal WD supplied from the FDC, a clock signal and the prescribed mark, the classification of the writing data and the prescribed mark disposed at the first of the writing data are detected, only the writing data is extracted and writted in the device MBM through an input and output IF. In this manner, the memory capacity of the device can be efficiently used.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a memory device, and relates to a technique that is effective for use in, for example, a magnetic bubble memory device compatible with a floppy desk memory device.

[Conventional technology]

Floppy disk memory devices are widely used in information processing devices having various microcomputer functions because the floppy disk as a storage medium is inexpensive and easy to handle. However, the above-mentioned floppy disk memory has a durability problem and is not suitable as a memory device in which frequently used programs for controlling various processes are stored. Therefore, the inventors of the present application,
Previously, we developed a magnetic bubble memory device that is compatible with floppy desk memory devices. This magnetic bubble memory device is one in which an interface circuit is provided between a floppy disk control device and a magnetic bubble memory device, and the magnetic bubble memory device is used as the storage section in place of the floppy disk memory. Note that data line transfer methods for disk memory and bubble memory are described, for example, in Japanese Patent Application Laid-Open No. 57-125453 and Japanese Patent Application Laid-Open No. 60-25090.
It is known from the publication No.

[Problem that the invention seeks to solve]

In the format of floppy desk memory (IMB format), each sector consists of an ID (index) field and a data field, as shown in FIG. Note that the first sector number 01 corresponding to the index hole (INDX), gap GapO1 synchronization part 5
ync, index mark IM and gap Gapl
A preamble consisting of: Although not shown, a gap called a postamble is provided between the index hole (INDX) and the final sector.

The storage information amount constituting each of the above formats is assigned a storage capacity in bytes as shown in the numerical values (decimal notation) corresponding to FM (single density) and MFM (double density). Therefore, as a magnetic bubble memory device to be compatible with the above-mentioned floppy disk memory, the average value of the true storage information Data is about 1.
This would require twice as much storage capacity.

An object of the present invention is to provide a memory device compatible with floppy desk memory devices that allows efficient data storage.

The above and other objects and novel features of the present invention will become apparent from the description of this specification and the accompanying drawings.

[Means for solving problems]

A brief overview of typical inventions disclosed in this application is as follows.

That is, a pattern generation circuit generates a storage pattern signal for the index section corresponding to the format of the floppy disk memory, and receives write data supplied from the floppy disk controller, separates the clock signal and data, and separates the beginning of the data. A detection circuit is provided to detect a predetermined data mark added to the section, and only a write signal is extracted and transmitted to the storage device.

[For production]

According to the above means, since only true data is written to a storage device such as a magnetic bubble memory device, the storage capacity thereof can be used efficiently.

(Embodiment) FIG. 1 shows a block diagram of an embodiment of a microcomputer system to which the present invention is applied.

Although not particularly limited, the host system H3 includes a central processing unit CPU, a read-only memory ROMI, and a random access memory RA, as shown by the broken line in the figure.
Peripheral devices such as MI, input/output device I10, timer circuit TM, and floppy disk controller FDC are connected by a bus. The buses include an address bus and a data bus. In addition, the central processing unit cp
In addition to the bus, a control signal line (not shown) is provided between U and each of the peripheral devices. Such a host system H3 is similar to a known microcomputer system or consists of 84 or more systems.

The host system H3 is provided with the following memory device MD as indicated by a broken line in the figure.

The memory device MD is composed of an interface circuit FBIF as shown by a dotted line in the same figure, and a magnetic bubble memory device MBM. The interface circuit FBIF performs various information conversion operations to replace the magnetic bubble memory device MBM with a floppy disk memory.

The interface circuit FBIF is composed of the following circuit blocks.

Although not particularly limited, the interface circuit FBIF is composed of the following devices connected to a microprocessor MPU by an address bus AB and a data bus DB.

The read circuit RD receives the sector address corresponding to the access of the magnetic bubble memory device MBM, and converts a predetermined pattern signal R forming an ID field written in the read-only memory ROM2, which will be described later, into a predetermined format. and sends it to the floppy disk device FDC. Although not particularly limited, for the first sector 01, the bit pattern corresponding to the preamble as shown in FIG. It is added to.

The buffer memory BUM is a data storage circuit designed to have a storage capacity of one track or more of the floppy disk memory to which it is associated.

The random access memory RAM constitutes the work area of the microprocessor MPU and stores data necessary for the information conversion processing operation.

The read-only memory ROM 2 stores therein, although not particularly limited to, a control program for the information conversion operation, and storage information constituting signals such as the ID field, preamble, and postamble.

The write circuit WR receives a write signal WD supplied from the floppy disk controller FDC, and inputs a clock signal, a predetermined mark, and a write data so that only true write data is stored in the magnetic bubble memory device MBM. Data separation and the predetermined mark (address mark A) placed at the beginning of the write data.
M2) It has a function of detecting t- and extracting only the write data.

The input/output IF performs a signal conversion operation for transmitting and receiving signals to and from the magnetic bubble memory BM.

Note that the pulse TP output from the floppy disk controller FDC to designate a track is, although not particularly limited, supplied to the microprocessor MPU and counted there to identify the track number. be.

An outline of the operation of this embodiment circuit will be explained below.

When the floppy disk controller FDC is activated, the interface circuit FBIF and the magnetic bubble memory device fMBM are also put into operation.

In a write operation, the floppy disk controller F
Since the pulse TP designating the track address is supplied from DC, the interface circuit FBIF performs an address selection operation of the magnetic bubble memory MBM corresponding to the pulse TP. Further, in response to access to the magnetic bubble memory MBM, a pattern signal according to the format constituting the ID field is sent to the floppy disk controller FDC via the reading circuit RD. At this time,
In the ID field, the magnetic bubble memory device M
A sector address corresponding to the BM access is added.

The floppy disk controller FDC receives the synchronization signal Sync included in the ID field, synchronizes the internal clock signal with the clock signal of the interface circuit FBIF, and decodes the sent sector address. Then, when a sector to be written is detected, a write signal WD is sent out. The write circuit WR separates the clock signal, address mark AM2, and write data in the write signal WD, and also extracts only the data to be written by identifying the mark placed at the beginning of the write data and writes it as is. Or input/output circuit I after storing in buffer memory BUM
Send it to the magnetic bubble memo U M B M via F,
This is what writes the information. As a result, only true data is stored in the buffer memory BUM and magnetic bubble memory device MBM.

In the case of a read operation, the ID field is added to the data stored in the magnetic bubble memory device fiMBM corresponding to the trunk address, and the data is sent to the floppy disk controller FDC. The floppy disk controller FDC sends data corresponding to the designated sester out of the read signal R to the central processing unit C.
It is sent to the PU.

As a result, the floppy disk control value W F DC allows data to be written/read in the same way as when accessing a floppy disk memory.

FIG. 2 shows a circuit diagram of an embodiment of the mark detection circuit included in the write circuit WR.

A write signal WD supplied from the floppy disk controller FDC is supplied to shift registers SRI and SR2 connected in series. This shift register SRI and SR
2 is, although not particularly limited, a TT'L() transistor.
It is composed of integrated circuits (transistor logic).

By supplying a clock signal CLK synchronized with the write signal WD to the clock terminal CLK, a write signal WD in which the clock signal and the mark and data are alternately arranged one bit at a time is taken in.

Among the output signals of the shift registers SRI and SR2,
By outputting output signals A, C, F, and G of 1 pin +-W, parallel conversion of the serial write signal WD and separation of the clock signal and mark or data are performed. However, in this state, it is impossible to determine whether a signal output at a certain timing is a clock signal or a mark or data. Therefore, each output signal of the shift registers SRI and SR2 is supplied to the read-only memory ROM3, although this is not particularly limited. This ROM detects the address mark AM2 by operating as a decoder circuit. For example, in the case of a single density (FM) recording system, when FB or an FB bit pattern expressed in hexadecimal notation is supplied,
The detection output is outputted via flip-flop circuits FFO and FFI. At this time, if there is write data corresponding to F8 or FB in the write data, a malfunction occurs in which this is detected as the mark. Therefore, in this embodiment, the pattern of the clock signal supplied together with the address mark AM2 is a special pattern (missing clock).
Using this fact, the true address mark AM2 (
FB, FB). Therefore, in addition to the mark, storage information for decoding the input signal of the bit pattern corresponding to the missing clock is written in the ROM 3. In the structure of the write signal WD, the clock signal is supplied before the mark and data, so the detection signal of the missing clock signal is supplied to the flip-flop circuit FF3, and the output signal of the flip-flop circuit FF3 is is fed back to the input terminal of the ROM 3 so that it becomes one of the conditions for detecting the mark.

In addition, the latch circuit FF converts the clock signal CLK to 1/8
The parallel-converted signal is captured in synchronization with the frequency-divided timing signal.

This will be explained in detail with reference to the timing diagram shown in FIG.

Of the write data WD, the bit pattern corresponding to the address mark FB (or FB) is made up of a clock signal C and data D (address mark FE) arranged alternately every other bit, as shown in the figure.

Such a serial write signal WD is converted into a parallel signal by supplying it to the shift registers SRI and SR2. At this time, the clock signal C supplied corresponding to the address mark is 2 as shown in the figure.
When expressed in base notation, it becomes a specific pattern (missing clock) such as 11000111. When such a pattern of signals is supplied, the output signal of the flip-flop circuit FF2 becomes 1 and is fed back to the input side. After the output signal of this flip-flop circuit FF2 is set to 1, when a pattern of 11111011 indicating the address mark FB is supplied, its detection output is formed via the flip-flop circuit FFI. By this detection output, the 1/8 frequency dividing circuit of the clock signal CLK is temporarily reset via, for example, the microprocessor MPU or a predetermined logic circuit, and the 8 pins of the serially supplied write signal WD excluding the clock signal are reset. The write data No. 8 consisting of the following data is temporarily stored in the batza memory BUM or the like via the launch circuit FF, and then written into the magnetic bubble memory device fMBM.

In addition, in the case of the MFM (double density) method, the address mark AM2 is divided into 3 bytes and 1 byte, as shown in FIG. 6, and A1 in hexadecimal is written in the 3 bytes.
The remaining 1 byte is allocated to the above FB or FB. Then, the missing clock is A consisting of the above 3 bytes.
Inserted at the last byte in the 1 repeat signal.

Therefore, in the MFM system, as shown in the timing diagram of FIG.
Missing clocks having bit patterns of 00001 and 00001010 are detected. therefore,
After this, since the address mark FB or FB is inserted, it is necessary to remove it and then import the true data.

FIG. 3 shows a circuit diagram of another embodiment of the mark detection circuit included in the write circuit WR.

A write signal WD supplied from the floppy disk controller FDC is supplied to shift registers SRI and SR2 connected in series. This shift register SRI and SR
2 is not particularly limited, but TTL () transistor
For example, an integrated circuit such as product name r74Ls164 is used.

By supplying a clock signal CLK synchronized with the write signal WD to the clock terminal CLK, a write signal WD in which the clock signal and the mark and data are alternately arranged one bit at a time is taken in. This is similar to the embodiment shown in FIG. 2 above. In this embodiment, the output signals H to H of the shift registers SRI and SR2 are used as output signals to form a 16-bit parallel-converted output signal.

In order to separate the clock signal and data (including marks) among the output signals, every other bit of the signal is divided into sets of 8-bit signals. A total of 8-bit signals obtained from outputs A, C, E, and F of shift registers SRI and SR2 are supplied to input terminals AI to A8 of digital comparator DCI. A total of 8-bit signals obtained from the outputs BSD, F and H of the shift registers SRI and SR2 are supplied to input terminals AI to A8 of the digital comparator DC2.

A bit pattern AMP corresponding to the address mark is supplied to the other inputs B1 to B8 of the digital comparator DCI. A bit pattern MCP corresponding to the missing clock is supplied to the other inputs B1 to B8 of the digital comparator DC2. Thereby, the operation of comparing and detecting coincidence between the address mark and the missing clock as shown in FIG. 4 or FIG. 5 is performed simultaneously and in parallel. Then, the comparison-spread output signal is supplied to an AND gate circuit G, where an output matching both conditions is obtained.

The digital comparators DCI and DC2 receive a coincidence output signal of A=B from an exclusive OR circuit that receives signals from the corresponding input terminals A1 and 81 or A8 and 88, respectively, and an AND circuit that receives their -spread output signals. It forms the

Incidentally, the output signals corresponding to the digital comparators DCI of the shift registers SRI and SR2 are supplied to the input of a launch circuit (not shown), and after the above-mentioned comparison-spread output is obtained, in synchronization with the timing of the data signal, True write data is captured.

Although not particularly limited, the digital comparator DC
Pattern signals AMP and MC supplied to I and DC2
For P, information stored in a register is used. As a result, settings can be made arbitrarily by software or the like in accordance with the connected floppy disk control device FDC, in other words, in accordance with the recording method such as FM or MFM. This makes it possible to improve its versatility.

The effects obtained from the above examples are as follows. That is, (1) the storage capacity of the memory device can be used efficiently by detecting the address mark included in the write signal and extracting only the true data and writing it into the memory device. You can get the effect that you can.

(2) As a result of (1) above, the required storage capacity can be reduced, and the number of magnetic bubble memory elements can be reduced, which has the effect of reducing the cost of memory devices that are compatible with floppy disk memory devices. can get.

Although the invention made by the present inventor has been specifically explained above based on Examples, it goes without saying that the present invention is not limited to the above Examples and can be modified in various ways without departing from the gist thereof. For example, the memory device is
Static RAM instead of magnetic bubble memory device
It may be replaced with a semiconductor storage device such as a dynamic RAM, a COD (charge transfer device) memory device, etc. In addition to the format shown in FIG. Any information may be used as long as it has an identification mark in front of the data to indicate that the following information is data.

The interface circuit that performs a signal conversion operation between the floppy disk control device and the memory device can have various configurations depending on the memory device used, and may use the microprocessor shown in FIG. 1 above. Alternatively, it may be constructed from one semiconductor integrated circuit device having a microcontroller function or the like.

The present invention can be widely used as a memory device compatible with floppy disk memory devices.

〔Effect of the invention〕

A brief explanation of the effects obtained by typical inventions disclosed in this application is as follows. That is, by detecting the address mark included in the write signal and extracting only true data and writing it into the memory device, the storage capacity of the memory device can be used efficiently.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a circuit diagram of an embodiment of the mark detection circuit included in the writing circuit shown in FIG. A circuit diagram of another embodiment of the mark detection circuit. FIG. 4 is a timing diagram for explaining an example of its operation. FIG. 5 is a timing diagram for explaining another example of its operation. FIG. 6 is a format diagram for explaining the recording method of the floppy disk memory.

Claims (1)

[Claims] 1. A pattern generation circuit that generates a storage pattern signal for the index section corresponding to the format of the floppy disk memory, and a pattern generation circuit that generates a clock signal and data by receiving write data supplied from the floppy disk controller. a detection circuit that separates the clock signal and detects a predetermined mark added to the beginning of the data; an input/output circuit that writes the clock signal and the separated write data to the storage device according to the detection output of the detection circuit; and the input/output circuit. A memory device characterized by comprising a storage device that sends and receives data through a storage device. 2. The memory device according to claim 1, wherein the memory device is a magnetic bubble memory device. 3. The memory device according to claim 1, wherein the memory device is a static RAM device. 4. The format of the floppy desk memory is such that each sector consists of an index field and a data field, and the beginning of the data field contains a predetermined mark and a missing clock. The memory device according to claim 1, 2 or 3, wherein the memory device detects coincidence between the mark and the missing clock having a pattern different from that of a normal clock signal. . 5. The detection circuit includes a shift register that converts a serially supplied write signal into parallel, and a read-only memory that receives the output signal of the shift register and forms the mark and missing clock detection outputs. 5. A memory device according to claim 1, wherein the memory device is characterized in that: 6. The detection circuit is composed of a shift register that converts a serially supplied write signal into parallel data, and a matching circuit that receives the output signal of the shift register and forms detection outputs of the mark and missing clock. 5. A memory device according to claim 1, characterized in that: