JPS6224388U - - Google Patents
Info
- Publication number
- JPS6224388U JPS6224388U JP11576185U JP11576185U JPS6224388U JP S6224388 U JPS6224388 U JP S6224388U JP 11576185 U JP11576185 U JP 11576185U JP 11576185 U JP11576185 U JP 11576185U JP S6224388 U JPS6224388 U JP S6224388U
- Authority
- JP
- Japan
- Prior art keywords
- snooze
- circuit
- switch
- alarm
- monitor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012544 monitoring process Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Electric Clocks (AREA)
- Electromechanical Clocks (AREA)
Description
第１図は本考案にかかるスヌーズモニタ回路が
組込まれた電子アラーム時計の好適な実施例を示
すブロツク回路図、第２図は第１図における一般
的なスヌーズ作用を説明するタイミングチヤート
図、第３図は本考案にかかるスヌーズモニタ回路
の作用を説明するタイミングチヤート図である。
２２……アラーム回路、２４……目安接点、４
０……発音回路、５０……スヌーズコントローラ
、５２……スヌーズカウンタ、５４……スヌーズ
スイツチ、８２……スヌーズモニタスイツチ、８
４……モニタ回路、９０……パルス切替器、φ２
……高速パルス。
1 is a block circuit diagram showing a preferred embodiment of an electronic alarm clock incorporating a snooze monitor circuit according to the present invention; FIG. 2 is a timing chart illustrating the general snooze operation shown in FIG. 1; FIG. 3 is a timing chart explaining the operation of the snooze monitor circuit according to the present invention. 22... Alarm circuit, 24... Reference contact, 4
0... Sound generation circuit, 50... Snooze controller, 52... Snooze counter, 54... Snooze switch, 82... Snooze monitor switch, 8
4...Monitor circuit, 90...Pulse switch, φ2
...High speed pulse.
Claims (1)
、アラーム動作を一時的に中断するスヌーズスイ
ツチと、スヌーズスイツチ操作後の経過時間を計
数して所定時間経過後に所望のアラーム動作を繰
返すスヌーズ回路とを含む電子アラーム時計にお
いて、外部操作されるスヌーズモニタスイツチと
、前記スヌーズモニタスイツチの出力に基づいて
前記スヌーズ回路に供給される計数パルスを切替
制御するモニタ回路と、を含み、スヌーズモニタ
時にはモニタ回路から高速パルスがスヌーズ回路
のカウンタに供給され、スヌーズ時間を短縮する
ことを特徴とする電子アラーム時計のスヌーズモ
ニタ回路。 An electronic device that includes an alarm circuit that activates an alarm at a set time, a snooze switch that temporarily interrupts the alarm operation, and a snooze circuit that counts the elapsed time after the snooze switch is operated and repeats the desired alarm operation after a predetermined time elapses. The alarm clock includes an externally operated snooze monitor switch, and a monitor circuit that switches and controls counting pulses supplied to the snooze circuit based on the output of the snooze monitor switch, and receives high-speed pulses from the monitor circuit when monitoring the snooze. is supplied to a counter of the snooze circuit to shorten the snooze time.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11576185U JPS6224388U (en) | 1985-07-26 | 1985-07-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11576185U JPS6224388U (en) | 1985-07-26 | 1985-07-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6224388U true JPS6224388U (en) | 1987-02-14 |
Family
ID=30999718
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11576185U Pending JPS6224388U (en) | 1985-07-26 | 1985-07-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6224388U (en) |
-
1985
- 1985-07-26 JP JP11576185U patent/JPS6224388U/ja active Pending