JPS62243194A - Semiconductor sense circuit - Google Patents

Abstract

PURPOSE:To attain the high speed operation regardless of the variation in the element characteristic by providing a circuit controlling a sense differential amplifier to bring an optimum bias condition at high speed. CONSTITUTION:The circuits controlling automatically the bias condition of the sense differential amplifier 11 such as a dummy differential amplifier 14, a precharge potential generating circuit 15, a comparator 16 and a reference potential generator 17 are provided. A current source EFET Q25 of a dummy differential amplifier 14 is controlled so that a voltage V01 entering the comparator 16 from the dummy differential amplifier 14 is equal to an output V02 of the reference potential generator 17. Then the control voltage Vc obtained from the comparator 16 is used as the control voltage of the current source EFET Q15 of the sense differential amplifier 11 as it is. Thus, the sense differential amplifier 11 is set automatically to the optimum bias condition at high speed operation at all times.

Description

DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a semiconductor sense circuit that detects minute potential differences, and particularly to a sense circuit that is useful when applied to a GaAs memory.

(Prior Art) GaAs memory is expected to have low power consumption and high-speed performance. A typical basic circuit configuring a GaAs memory is DCFL (Ω-1rect
Coupled F E T L or+ic
) is a circuit. In order to achieve high-speed performance of semiconductor memory, it is extremely important to ensure high-speed performance of the sense circuit. To this end, it is necessary to satisfy both the sensitivity of sensitively detecting the potential difference between a pair of bit lines and the function of rapidly amplifying the detected potential difference. From this point of view, conventional sense circuits for GaAS memories have been constructed from a sense differential amplifier that detects the difference in bit line potential, and a high-gain amplifier that transmits the output to the subsequent stage. Ta.

FIG. 3 is an example of a sense circuit used in a conventional GaAS memory. The transistors used are a normally-on MESFET (hereinafter referred to as 0FET) and a normally-off type MESFET (hereinafter referred to as EFET). 1 is a differential amplifier for sense, and the load 0FET-Q
l, Q2, driver EFET-Q! , Q4, and a current source DFET-Qs connected to the common source of Q3 and Q4. Negative MDFET-Q1. The drains of Q2 are commonly positive electric f! Connected to AVoo, 0FET-Qs for current source
The source of is connected to fi71aiVss. A pair of pit lines BLs and B10 are connected to the gates of driver EFET-Q3 and Q4, respectively. 2.3 is an inverter amplifier that amplifies the output of the sense differential amplifier 1, and a load DFET-Qs.

Q8, driver EFET-07, and Q9.

The operation of the sense circuit configured in this way is as follows. When reading memory information, bit lines BL1. BL2 (7) Potentials Vt and V2 (1) IftL start to fall, and by detecting the potential difference, the two output potentials Vl' and V2' of the sense differential amplifier 1 also start to move. When these potentials reach the threshold of the inverter amplifier 2.degree.3 at the next stage, one of the output terminals 0UT1.0UT2 becomes the "H" level and the other becomes the "L" level.

FIG. 4 shows an example of potential changes in this sense circuit. When Vl-V2 = Vt, the output potential V2'
is the “H+! level input minimum value VH of inverter amplifier 2
(liln > or more, and the output Vl" is the maximum input level of °L" of the inverter amplifier 3! IVL (I
iaX ) or less, the output terminals 0UTr, 0UT
The potential of 2 becomes significant information.

When Vl-V2, Vt'-V2'-Vll
Teal.

The sensing speed in such a sensing circuit is as follows: ■2' is Va
It is determined by the time required to transition from VH (sin) to VH (sin). In order to shorten this time, make Vo as close as possible to the transition i1[ shown with diagonal lines in Fig. 4, and set the threshold ta v
It is preferable to make t small. However, GaAs
- The characteristics of MESFET vary greatly from wafer to wafer and chip to chip, and therefore VH (win) and VL (wax), which determine the transition region of VO and the inverter amplifier, vary from chip to chip. In fact, the gate length is 1.2 μm and the threshold (1! DFET with voltage -0.5V, +0.IV (7) EF
When a DCF+- circuit consisting of an ET is prototyped, the threshold voltage varies by about ±50 mV between chips.

Therefore, in order to realize high-speed operation of the sense circuit shown in Fig. 3, it is necessary to perform work such as adjusting the power supply Vss for each chip.Otherwise, the operating speed will vary greatly from chip to chip, and the chips will not be able to operate at high speed. The problem was that a lot of

(Problems to be Solved by the Invention) As described above, in the sense circuit of conventional GaAs memory, in order to achieve high-speed operation, adjustment work is required for each chip, or if adjustment work is not performed, the sense circuit does not work properly. There was a problem in that the speed variations were extremely large.

SUMMARY OF THE INVENTION An object of the present invention is to solve such problems and provide a semiconductor sense circuit that can operate at high speed regardless of variations in device characteristics.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a circuit that divides a sense differential amplifier into optimal bias conditions for high-speed operation even if there are variations in element characteristics. will be established.

As such a control circuit, first, a reference potential generator is provided which has the same structure as the inverter amplifier subsequent to the sense differential amplifier, and which shorts its input and output terminals to generate an input threshold sin pressure as a reference potential. .

On the other hand, a dummy differential amplifier is provided which has the same structure as the sense differential amplifier and has two input terminals applied with precharge potentials of a pair of signal lines.

A comparator is provided to compare the output of the dummy differential amplifier and the output of the reference potential generator and control the current source transistor of the dummy differential amplifier so that the difference becomes zero. The output is used as it is as a control voltage for controlling the current source transistor of the sense amplifier.

(Function) With the configuration of the present invention, the amount of current by the current source transistor of the sense differential amplifier is automatically controlled, and when the signal line is at the precharge potential, the output potential of the sense differential amplifier is is set equal to the input threshold voltage of the inverter amplifier.

In this case, the reference potential generator has the same structure as the inverter amplifier that follows the sense differential amplifier, and the dummy differential amplifier also has the same structure as the sense differential amplifier, so there are variations in element characteristics and the inverter amplifier Even if the input threshold voltage of the inverter varies from chip to chip, the output potential at the time of inputting the precharge potential of the sense differential amplifier is controlled so that it is always equal to the threshold voltage of the succeeding inverter amplifier. Wholesale. That is, regardless of variations in device characteristics, the sense external amplifier is always set to optimal bias conditions for high-speed operation.

(Example) The present invention will be explained in detail below.

FIG. 1 shows a sense circuit of a GaAS memory according to an embodiment. A DCFL circuit is used as the basic circuit. The sense amplifier 11, which forms the main part of the sense circuit, is a load DFET.
-Qs 1. Qs 2 , driver EFET-Qs 3
, two inverters consisting of Qt 4 and an EF for the current source.
It is composed of ET-Q1s. Load DFET-
The drains of Qll and Qs2 are commonly connected to the positive power supply Voo, and the source of the current source EFET-Q1s is connected to the negative It
Connected to m V s s. Driver EFET-
O! 3. Bit line BLt paired with the gate of Qr4
, B10 are connected. This sense differential amplifier 11
The two outputs of the inverter amplifiers 12 and 13 respectively
is connected to the input terminal of Inverter amplifier 12.
13 are load DFET-Qla.

It is composed of Qla, driver EFET-Ql7, and Qss.

A dummy differential amplifier 14, a precharge potential generation circuit 15. A comparator 16 and a reference potential generator 17 are provided.

The dummy differential amplifier 14 is formed with the same structure according to the same design rules as the sense differential amplifier 11, and includes the load 0FET-021, Q22, and driver EFET.
It consists of two inverters consisting of -Q23 and Q24 and a current source EFET-Q2S. The precharge potential generation circuit 15 outputs the pull-up potential VPLIL to the pit line precharge potential Vp through the DFET-Q26, and this precharge potential Vp is applied to the two input terminals of the dummy differential amplifier 14. Commonly input. The reference potential generator 17 is connected to the inverter amplifier 12.
Load 0FET-036 and driver EFET-0 constitute an inverter amplifier with the same design rules and the same structure as 13.
37, and its input/output terminals are short-circuited to set the input threshold Ill! It outputs voltage VO2. The comparator 16 is a differential amplifier, and the load DFET-Q3 s
, Q32, an inverter consisting of driver EFETs Q33 and Q34, and a current source DFET-Q3s. The two input terminals of this comparator 16 are the output VO2 of the reference potential generator 17 and the dummy differential amplifier 1.
The output Vos of 4 is input. One output of the comparator 16 is the current source EF of the dummy difference first amplifier fi14.
The control IIN pressure Vc is applied to the gate of ET-025. This control wJN pressure loop constitutes a negative feedback circuit, and as will be explained in detail later, the voltage Vas entering the comparator 16 from the dummy differential amplifier 14 becomes equal to the output V112 of the reference potential generator 17. As shown, 1tFll'a EFET-Q2S of dummy difference first amplification 2114
is controlled.

And the control r1 obtained from this comparator 16! 1 of the sensing differential amplifier 11! EFET for flow source
It is used as the control Il voltage of Qls.

To explain the specific design rules, the load DFET-Qll, Qt□ of the sense differential amplifier 11, and the load DFET-Q2t of the dummy differential amplifier 14.

Q22, and the load DFET-Q31 of comparator 16. Q
32 is a gate width of 20um, inverter amplifier 12.13
Load of 0FET-Qls.

Q+e and reference potential generator 17 load DFET-Q3
6 is a precharge potential generation circuit 15 with a gate width of 10 μm.
The gate width of DFET-Q26 was 5 μm. Driver EFET-Ql of sense differential amplifier 11 3.0+
4. Driver EFET-Q of dummy differential amplifier 14
23, Q24 and comparator 16 driver EFET-
The gate widths of Q33 and Q34 are 20 μm, the gate widths of the current source EFET-Q1s and Q2s of the sense differential amplifier 11 and the dummy differential amplifier 14 are 40 μm, and the gate width of the current source DFET-Q3S of the comparator 16 is 40 μm. The gate width was also 40 μm. Inverter amplifier 12°13 and reference potential generator 17 driver EFET-Q17. Qt
The gate width of 9 and Q37 was set to 40LtrrL. The gate length was set to 1.2 μm for all EFETs and DFETs. Matashikii 1 Direct Electricity II HaD F E T 71
) (-0, 5V, E F E T +0, 1■
It was designed to be. When manufactured according to this strict design standard, with current technology, the variation in threshold voltage between chips is about ±50 mV.

Next, the operation of the sense circuit shown in FIG. 1 will be explained. The reference potential generator 17 is an inverter amplifier whose input and output terminals are short-circuited, and the input-output transfer characteristics of this inverter amplifier are as shown in FIG. Since the input terminal and the output terminal are short-circuited, the output potential Vo2 becomes the input threshold voltage, which is the center of the transition region of the double spectrum characteristic. This output Vo2 corresponds to the threshold voltage V[ shown in FIG. 4, but this differs from chip to chip due to variations in element characteristics. On the other hand, in the dummy differential amplifier 14, the bit line precharge potential Vρ obtained using, for example, the pull-up potential Vpu+- from the promotion circuit is commonly input to two input terminals, and the bit line is in a standby state. Output Vo+ corresponding to the output.

This output VOt corresponds to Va in FIG. 4, but this value also differs from chip to chip due to variations in element characteristics. Comparator 16 compares these two outputs VO1 and VO2 and controls the result l11! ! It is output as pressure Vc. As mentioned above, in order to speed up the sense circuit, VO1 must be Va.
Although it is preferable that Vc be equal to 2, this control circuit outputs the control voltage Vc so as to satisfy this condition. That is, if the output Vo 2 of the reference potential generator 17 shifts in the positive direction, the control IN obtained from the comparator 16
Pressure Vc decreases. As a result, the current amount of the dummy differential amplifier 14 [EFET-Q2S] decreases, and the gate-source voltage V of the driver EFET-Q23 and Q24 decreases.
gs decreases. On the other hand, driver EFET-Q23,
Since the gate potential of Q24 is constant at the precharge potential Vρ, the common source potential of the driver EFETs Q23 and Q24 eventually rises. As the common source potential rises, the output Vo 1 of the dummy differential amplifier 14 rises.

In this way, the control voltage ■. As a result of having a negative feedback effect, when the gain of the comparator 16 is large, regardless of the variation in the output Va 2 of the reference potential generator 17, Vol - VO is always
Stable in state 2. The control pressure Vc obtained from this comparator 16 is directly applied to the sensing differential amplifier 11.
Since the current source E is also supplied to the gate of FET-01s, the sense differential amplifier 11 is always automatically set to the optimal bias condition for high-speed operation.

As described above, according to this embodiment, GaAs-ME
Even if SFETs are used and therefore there are large variations in their threshold mg pressures, the sense circuit will always function at the optimum operating point for high speed operation. In order to obtain such a function, the characteristics of the elements constituting the dummy differential amplifier 14 must be the same as those of the elements constituting the sense differential amplifier 11, and the characteristics of the elements constituting the sense differential amplifier 11 must be the same, and the inverter amplifiers 12 and 13 must have the same characteristics. It is assumed that the characteristics of the elements and the characteristics of the elements constituting the reference position generator 17 are the same, but in reality, doing this means that the dummy circuit and the actual circuit are placed close to each other in the layout of the memory circuit. This is easily possible by arranging the

The present invention is not limited to the above embodiments.

For example, in the embodiment, a sense circuit of a GaAs memory has been described, but the present invention can be similarly applied to other memory circuits such as an S1 memory. In particular, there are many variations in characteristics.
This is effective when using vlESFET.

Further, in the embodiment, a sense circuit for reading information from a memory has been described, but the sense circuit of the present invention is a memory I! It is useful as a sense circuit for detecting minute potential differences based on the same principle in other parts of integrated circuits or in various logic integrated circuits.

[Effects of the Invention] As described above, according to the present invention, it is possible to provide a sense circuit that is always automatically set to the optimum bias condition and capable of high-speed operation even if there are variations in element characteristics.

[Brief explanation of drawings]

FIG. 1 is a diagram showing a sense circuit in a GaAS memory according to an embodiment of the present invention, FIG. 2 is a diagram showing transfer characteristics of an inverter constituting the reference potential generator, and FIG. 3 is a diagram showing a conventional sense circuit. 4 are diagrams showing its operating characteristics. 11...Sense differential amplifier, 12.13...Inverter amplifier, 14...Dummy differential amplifier, 15.
...Precharge potential generation circuit, 16...Comparator, 1
7...Reference potential generator. Applicant's agent Patent attorney Takehiko Suzue0 0.2 0.4 0.6゜Input Cv
) Figure 2

Claims (2)

[Claims] (1) A sense differential amplifier that detects the potential difference between a pair of signal lines precharged to the same potential, and an inverter amplifier provided at the output stage of this differential amplifier, which has the same structure as this inverter amplifier. , has the same structure as the reference potential generator whose input/output terminals are short-circuited to output a reference potential, and the sense differential amplifier, and the precharge potential of the pair of signal lines is common to the two input terminals. A dummy differential amplifier applied to the dummy differential amplifier is compared with the output of the dummy differential amplifier and the reference potential generator, and the current source transistor of the dummy differential amplifier is controlled so that the difference becomes zero. A semiconductor sense circuit characterized in that it also includes a comparator that controls a current source transistor of the sense differential amplifier. (2) the signal line is a bit line of a GaAs memory;
2. The semiconductor sense circuit according to claim 1, wherein the sense differential amplifier, dummy differential amplifier, inverter amplifier, reference potential generator, and comparator are constructed using a DCFL circuit.