JPS62243078A - Hidden-surface erasing method for graphic display - Google Patents

Abstract

PURPOSE:To additionally draw a picture in a display area without exerting an influence on other area by setting a value of a Z address memory of an optional area among image display areas which have been divided into the plural, to a specific value. CONSTITUTION:A controlling circuit 7 is set to a usual mode for executing a hidden-surface erasion processing by a processor circuit 9, and a forced write mode for writing forcibly a Z address value which has been inputted from a picture element generating circuit 1 to a Z address memory 5. First of all, in order to display an image, all values of the memory 5 are set to Zmax and a graphic is drawn in an image display area. Subsequently, a Z address of an area in which forced picture drawing is executed is set to Zmaz, and graphic data are inputted from the circuit 1. Also, to other area, the data are inputted newly from the circuit 1 and a usual hidden-surface erasion processing is executed. In this way, even if additional picture drawing is executed in the display area, no influence is exerted on other area.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a method for erasing hidden surfaces of a three-dimensional image rendered by a three-dimensional graphic display device.

(Summary of the invention) By setting the value of the 7 address memory in any area of the divided image display area to 7, it is possible to write images in different modes such as normal write mode and forced write mode. This allows the values in the Z address memory to be compared correctly even if additions are made.

(Prior art) When displaying a three-dimensional figure in real time as a video,
As in Japanese Patent Application No. 1999-1999, which was already proposed by the same applicant, the three-dimensional image data generated by the pixel generation circuit is sequentially input to the hidden surface elimination circuit, and seven addresses for each pixel are already stored in the Z address memory. The Z addresses stored in the memory are compared in size, and based on the results, it is determined whether to update or leave the contents of the Z address memory as is, and the image is displayed.

(Problems to be solved by the invention) As shown in FIG. 3(a), the display area divided into multiple parts (
When a figure is displayed on the view board ■1 to Va), an image is forcibly added to a certain display area (■4) regardless of the value of the 7 address memory, and then another display area (Vl) is displayed.
When the normal additional 115 strokes are performed to compare the size of two addresses, the two addresses of the two addresses performed during the forced additional drawing
■Since the ax setting is performed over the entire display area, the next normal additional drawing will be compared in size using ax using a Z value (Z) that is different from the two address values that the image originally had. The drawing shown in FIG. 3(d) was performed.

(Means for solving the problem) The Z address memory can be initialized for each divided display area, so that the value of the 2 address memory for performing hidden surface processing is Even if additional drawing is done in , other display areas are not affected.

(Function) The control circuit of the hidden surface erasing section sets the binary value of the Z address memory corresponding to the view port area to be forcibly written to Z 1 lax by the erase counter.

(Example) Embodiments of the present invention will be described below based on the drawings.

FIG. 1 is a block diagram of the hidden surface erasing section of the present invention, and the pixel generating circuit to which image data is input from the processor circuit is Ii! Pixels corresponding to the i image are generated and input to the image memory via the output latch. At this time, hidden surface erasing processing is performed by the 2-address memory and the write control circuit.

Furthermore, the control circuit and erase counter that control the hidden surface erasing method of the present invention set the binary values of the 2-address memory corresponding to the view boat area to be forcibly written to Z and ax to perform normal hidden surface erasing processing. Execute.

Figure 2 shows a display area divided into multiple parts (view board v
1 to V4), the view port (■4) in which an image is written in the forced write mode is a diagram illustrating partial erase in the view port (■4), and the control circuit 7 is a diagram showing partial erase in the view port (■4) in which an image is written in the forced write mode.
input the coordinate values P1 and P2 of
Set to aX. It goes without saying that the regions of P1 and P2 can be freely set by the control circuit.

The hidden surface processing that is actually performed will be explained using the display example shown in FIG.

The control circuit 7 is set to a normal mode in which the processor circuit 9 performs normal hidden surface erasing processing and a forced write mode in which the two address values input from the pixel generation circuit 1 are forcibly written into the two address memory 5. In the case of forced write mode, the control circuit 7 outputs a prohibition flag to the output latch so that the output latch does not output data to the image memory.

(1) Normal mode - To display an image for the first time, set all values in the Z address memory to ZlaX. (Full erase) ■Draw shapes on each view boat. As a result of the above, FIG. 3(a) is displayed.

(2) Strong l111I included mode - Set the 2nd address of PyuBoat v4 for drawing to Z. (Partial erase) -ax ■The control circuit outputs a prohibition flag to the output latch to prevent data from being input to the image memory.

(3) Normal mode ■ Input the graphic data of "ABC" into the pewboard area v4 from the pixel generation circuit. (Va's Z address is Z
Since it is initialized by setting aX, any figure with any Z value will be displayed. ) Through the above steps, FIG. 3(b) is displayed.

(2) Further, new cylinder data is input from the pixel generation circuit to another view board area v1.

■Perform normal hidden surface removal processing. As a result of the above, Figure 3 (C)
is displayed.

(Effects of the Invention) As explained above, the present invention partially sets the 2-address memory of the hidden surface erasing circuit used when displaying a three-dimensional figure to Z, thereby Even after a figure is forcibly drawn, the three-dimensional figure can be updated without affecting other screen areas at all.

[Brief explanation of drawings]

Fig. 1 is a block diagram of the hidden surface erasing unit, Fig. 2 is an explanatory diagram showing partial erase, Fig. 3 is an explanatory diagram without display examples, and Fig. 4 is a mode of the ailIw1 circuit and hidden surface erasing. 3 is a flowchart showing the processing of FIG. 1... Pixel generation circuit 5... Z address memory 6... Output latch 7... Control circuit 8... Erase counter Applicant Seiko Electronics Co., Ltd. Yen (x2.Y2) IP + Ratio 1 Figure 2 (a) , u, 1 to Bσ' watch (b) 廿 circle n'rt side 〃p (C) (d)

Claims (1)

[Scope of Claims] An image is displayed in each of a plurality of display areas divided by a Z-address memory that stores data in the depth direction of a three-dimensional image and a processor circuit, and corresponds to the display area divided by the processor circuit. Initialize the address memory value that stores the Z address to be used (
It consists of an erase counter that is set to Z_m_a_x), and a control circuit that controls the erase counter using data from a processor circuit, and forcibly sets the Z address value in the depth direction to the Z address memory area initialized by the erase counter. A method for erasing hidden surfaces of a graphic display characterized by writing.