JPS6242281A - Graphic display device - Google Patents

Abstract

PURPOSE:To omit comparison/decision processing and to process a hidden surface at a high speed by providing a flag in 1-bit correspondence to each coordinates of a depth buffer and a means which controls the depth buffer and a frame memory. CONSTITUTION:A processing part 1 produces successively the 3-dimensional coordinates of the picture element strings of the sides forming a polygon and delivers them to a digital and differential analyzer DDA2. At the same time, the part 1 delivers control or luminance data to a frame memory 5. Here a flag 8 is provided in 1-bit correspondence to each coordinate of a depth buffer 4. While a control circuit 9 controls the flag 8, the buffer 4 and the memory 5. Thus it is possible to decide with reference to the flag 8 whether the Z coordinates of a display pattern are stored or not in the buffer 4. Then writing is possible to both the buffer 4 and the memory 5. As a result, a hidden surface can be processed at a high speed.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a graphic display device, particularly a hidden surface processing device.

Prior Art FIG. 3 shows the preparation of a conventional single-sided processing apparatus. Third
In the figure, 1 is a processing unit that generates the three-dimensional coordinates of the pixel rows that are the sides of the polygon,
+L1analyzer) 2, and also outputs color or brightness data to the frame memory 6. DDA2
teeth.

The Z coordinate (depth value) of each pixel inside the succulent shape is sequentially interpolated.

A comparator 3 compares the values of the DDA2 and the depth buffer 4. The depth buffer 4 is a memory that stores Z values for all pixels of the CR1 screen. For example, if the CR1 screen is made up of 1280×1024 pixels and the two coordinates of each pixel are represented by 1o bits, then 10 memory planes having a 1280×1024 memory cell array structure are required. A frame memory 5 has the same structure as the depth buffer 4, but the number of branes does not necessarily have to be the same. This frame memory 5 stores color or brightness data output from the processing section 1. 6 is a video controller, CR
The T monitor 7 is supplied with a horizontal/vertical synchronizing signal and a signal obtained by D/MU conversion of the output of the frame memory 5. CR
The T monitor 7 displays an image on a screen using an output signal from a video controller.

Generally, a figure in a three-dimensional space is represented by a set of polygons (a curved surface is approximated by a polygon). Hidden surface processing is the process of distinguishing between visible and invisible parts of a polygon.

FIG. 4 explains the operation of FIG. 3 using triangle v1v2v3 as an example. The coordinates in FIG. 4 represent coordinates on the screen (screen coordinates). In Figure 44, two points Pm (xm, Ym, Zm) p', (x', ,
y', , z'l! l) is on the same scanning line, and PI! to this 2! The coordinate values of l and P'Tn are output from the processing section 1 of FIG. 31 to the DD module 2. At this time, line segment PmP
'Each %m on the construction is based on the point PI, 1, and the X coordinate is I.
, are found incrementally in the X-axis direction by adding ε to the Z coordinate. However, ε−(z', −z,)
/ (Xil-X, ). The coordinates of the nth point Qn from point Pm are Qn (Xm + n, Ym, Z
m + nε). It is sent to the Z seat ld comparator 3 of Qn. In parallel, data is read out from the address corresponding to the screen coordinates (X, +n, YIn) in the depth buffer 4 and compared with the Z coordinate of Qn.

If the Z coordinate of Qn is small, that is, if Qn is closer to the viewpoint, (1) (Xm-1-n, Ym) of depth buffer 4
and (2) write the data output from the processing section 1 to the address corresponding to (X, !l+n, Ym) in the frame memory 5.

Qn OZ seat, if the vote is larger, depth buffer 4. No writing is performed to the frame memory 6.

In this way, it is determined whether the point Qn within the triangle v1v2v5 is visible or hidden. This operation is performed for all points on PmFlm that are found incrementally.

Furthermore, by processing all the scanning lines in the triangle v1v2v3, the triangle v1v2v5
The determination of whether all pixels within the area are visible or hidden is completed. If you perform the above processing on all sides of the figure to be displayed,
The four-sided processed figure will be displayed on the 3RT monitor.

Problems to be Solved by the Invention However, in the conventional hidden surface processing device described above, even if the data in the depth buffer for the pixel to be processed has been cleared, it is necessary to read out that data and make a comparison judgment. processing time was required. The present invention is intended to solve these conventional problems, and it is an object of the present invention to provide a graphic display device that performs high-speed hidden surface processing.

Means for Solving the Problems In order to achieve the above object, the present invention is provided with a flag corresponding to one bit for each coordinate of the depth buffer, and a control circuit for the flag, the depth buffer, and the frame memory.

Therefore, according to the present invention, it is possible to determine whether or not the Z coordinate of the displayed figure is stored in the depth buffer by lighting the flag, and if the Z coordinate of the displayed figure is not stored, it is possible to determine whether the Z coordinate of the displayed figure is stored in the depth buffer. It is possible to write to the depth buffer and frame memory without making a determination, which has the effect of speeding up hidden surface processing.

Embodiment FIG. 1 shows the configuration of an embodiment of the present invention. In FIG. 11, 1 to 7 correspond to those in FIG. 3 and are indicated by the same numbers. 8 is a flag, and one bit corresponds to each pixel on the display screen.

Reference numeral 9 denotes a control circuit which receives data from the flag 8 and the comparator 3 and sends data to the depth buffer 4. Frame memory 5. Controls the DDM2.

FIG. 2 7i is an explanatory diagram of the 7 lugs 8 in FIG. 1. Figure 2a
represents the figure displayed on screen 2, and b represents the data of flag 8. The flag corresponding to the pixel where the figure is displayed is "1", and the flag is "0".

Next, the operation of the above embodiment will be explained. The control circuit 9 reads the flag for the pixel to be processed from the flag 8.

(1) When the flag is "0", the figure or part of the figure is not displayed in the pixel PI. This means that a new figure is always displayed at the pixel PI.

Therefore, at the same time as writing the output of the DDM 2 to the depth buffer 4, color or luminance data is written to the frame memory 5.
write to. Then, the flag for the pixel PI is set to "1".

(2) When the flag is "1", the output of the depth buffer 4 and the output of the DD person 2 are compared, and the depth buffer 4 and the frame memory 6 are
Controls writing to.

As described above, according to the above embodiment, when the flag 8 is read and is "○", the control circuit 9 outputs a write signal to the depth buffer 4 and the frame memory 5, so that the output of the depth buffer 4 and the DD memory 2 are There is no need to compare the outputs of

Effects of the Invention As is clear from the above-mentioned embodiments, the present invention refers to the content of the flag and omits the process of comparing and determining when the flag is "rOFF", and has the effect that the hidden surface processing device can be improved. has.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an m-plane processing device of a graphic display device according to an embodiment of the present invention, and FIG.
,b is a schematic diagram for explaining the 7 lugs of the same device and ma)
FIG. 3 is a block diagram of a conventional hidden surface processing device, and FIG. 4 is a coordinate diagram for explaining the operation of the same device. 1...Processing department, 2...DD person, 3...
...Comparator, 4...Depth buffer, 5...
...Frame memory, 6...Video controller, 7...CRT monitor, 8...
Flag, 9... Control circuit. Name of agent: Patent attorney Toshio Nakao and 1 other person
1 Figure 2 (αn (Vagina Figure 3 J Figure 4)

Claims (1)

[Claims] a depth buffer that stores depth data of each pixel; and a depth buffer that stores depth data of a figure corresponding to each pixel;
and a flag that is turned OFF when no data has been written, and when new depth data enters a pixel and the flag corresponding to the pixel is OFF, the depth data is transferred to the coordinates corresponding to the pixel in the depth buffer. If the flag corresponding to the pixel is ON, data is read from the coordinates corresponding to the pixel in the buffer and compared with the depth data of the pixel, and the depth data of the pixel is determined to be better. A graphic display device characterized in that if the depth data is smaller, the depth data is written into the depth buffer.