JPS62241199A - Semiconductor memory device - Google Patents

Abstract

PURPOSE:To reduce the data volatile rate by writing a data in a floating gate P-ROM while inverting the data when the bit of electron injection type bit shares the majority. CONSTITUTION:An input data is written in a memory section 3 via an input buffer 2 by a data input stage 1. When the input data is an inverted data, data zero is written in all A, B and C or the check bit 11, and when a non- inverted data, 1 is written. In case of the read, the majority decision of the bit 11 is taken by a majority decision circuit 12 and the result is inputted to a exclusive OR gate 14. The desired address is accessed and a read signal is inputted to the gate 14 via a sense amplifier 4. In this case, when the output of the circuit 12 is zero, the read data is inverted, and when 1, the data is outputted as it is. Thus, the bit number of electron injection type is always made a half or below to lower the rate of volatile data.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to semiconductor memory devices such as EPROM and EEPROM.

[Conventional technology]

The memory cell of EPROM is F'AM as shown in Figure 6.
It has an O8 structure. In the figure, ■ is a single crystal semiconductor substrate, and ■ is a single crystal semiconductor substrate.

are respectively conductivity types opposite to that of the substrate, a drain diffusion layer, a floating gate into which electrons are injected, and a control gate that controls writing and reading.
QB is the gate oxide film between the substrate and the 70-ring gate,
Qs is the oxide film between the floating gate and the control gate, 弼, a is the field oxide film, (2), ω, 3D
is Alba. In this structure, the electron injection state shown in FIG. 6[bl] and the erased state shown in FIG. 6(a) take different energy states. The erased state is considered to be energetically balanced, and the pre-injection state means that electrons are injected into the floating gate by avalanche breakdown in the erased equilibrium state, so in the electron injection state,
Excess electrons on the floating cat try to return to the substrate or control gate. In addition, our experimental results show that, after proper control of manufacturing conditions and appropriate screening, the memory retention characteristics of floating gate type programmable memory are determined by the retention of electrons injected into the floating gate. I know it depends on the degree.

As shown in Fig. 4, a conventional EPROM (10 is an input cover sofa (2) for converting input data inputted by a data input means (1) into an internal signal, and a memory section (3)
and the data written in the memory section (3) is “1”
Sense amplifier (4) that determines whether the value is “0” or not.
, an output buffer (5) for giving external load driving capability to the data and outputting output data (6), and an address buffer (7) for receiving an address signal and determining the address of the memory section (3). ), decoder (8), (-(
.

It is composed of a control circuit (9) that controls input and output.

Next, the operation will be explained. In Fig. 4, the memory section (3
), and the data entered by the data manual means (1) is input to that address.
) is written through. When reading the following, the sense amplifier (4) determines whether the data at the specified address in the memory section (3) is "θ°" or "[°", and outputs that data. It is output as output data (6) through a buffer (5). Note that writing and reading are controlled by a control circuit (9). Moreover, as shown in FIG. 5, conventionally, program data written by a writer etc., data actually written to EPROM, and EFR
The data read from OM is exactly the same,
EPROM with original program data intact
f was written, and the written data was read out as is.

[Problem that the invention seeks to solve]

Conventional semiconductor memory devices are configured as described above, so when more than half of all written data is electron injection type data, compared to less than half, there is a higher possibility of data volatilization. There was a point.

This invention was made to solve the above-mentioned problems, and it reduces the number of electron injection type memory bits and creates a non-volatile semiconductor that can write data without worrying about the possibility of data volatilization. The purpose is to obtain a memory device.

[Means for solving problems]

The semiconductor memory device according to the present invention has a check function for storing an inversion signal in order to write the data by inverting it when the number of bits of the electron injection type is more than half of the total human data. bits and also when outputting the written data.

The function determines whether the data should be inverted by the contents of the check bit, and if the data needs to be inverted, it is inverted and not inverted (if the data needs to be inverted, it is output as it is not inverted). It is something I have.

[Effect]

Considering this invention, among the data written to the memory as a result, 'l! Child injection type data can always be less than half, reducing the possibility of data volatilization.

〔Example〕

The configuration of one embodiment of the present invention will be described above with reference to the drawings. In FIG. 1, (b) is a check bit configured with an EPROM to store an inverted signal, (6) is a majority decision circuit that takes a majority vote of 11 and "0" of the check bit data, ( 2) is an inverter, α field is an exclusive OR gate, and (g) is an EP ROM of an embodiment according to the present invention.
It is.

Next, the operation of one embodiment of the present invention will be explained. First, the human data input by the data input means C1) is passed through the input cover sofa (2) in the usual manner.
Write to memory section (3). Next, if this input data is inverted, check bit (6) 3 bits A
, B, and C. Write data "0°" to all of them.

If this manual data is non-inverted, data "1" is written in all check bits A, B, and C of the check bit (b). For reading, first check bit (6) A,
The majority decision of B and C is taken by the majority decision circuit (6), the signal is inverted by an inverter (to), and is input to the exclusive OR gate α. The desired address of the next memo (January 3) is accessed and the read data is input to the exclusive OR gate α through the sense amplifier (4).

At this time, the signal obtained by the majority vote of A, B, and C of the check bit (6) is "0", so that the read data input to the output buffer (5) is inverted, and therefore the output data (6
) becomes the inverted version. If the signal obtained by the majority vote of A, B, and C of check bit αυ is "1°," the read data inputted to the output buffer (5) remains non-inverted, so the output data (6) is It is non-inverted.A flowchart explaining the above configuration in an easy-to-understand manner is shown in Figure 2.Here, as check bits, A, B,
This is because the check bit is an extremely important hint that determines whether all data written in the memory section should be inverted and output. This was done to improve reliability. FIG. 3 shows a circuit diagram of a majority circuit according to an embodiment of the present invention. Figure 11) shows a general majority circuit using logic symbols, and Figure 11) shows the majority circuit using actual n-channel MOS transistors. In Fig. ial, if at least two input signals among the inputs of A and BC are "1", the signals A, , A2 . At least one signal of AI is output as "lo". Therefore, the OR gate α in the subsequent stage
The signal X output through η becomes "1". Next, A
, B, C are "0", the signals A, , A2 ., passed through the AND gate α. A, are all "0". Therefore, the signal X outputted through the OR gate in the subsequent stage becomes "O". Also, the same is true in the figure (bl), and A, B.

If at least two of the input signals of C are “1°.

The output of the NOR circuit composed of n MOS is “0”.
is output, and the gik stage inverter outputs
" is output. Next, if at least two of the input signals A, B, and C are "0", "l" is output to the NOR circuit composed of nMO8, and the subsequent stage "θ" is outputted by the controller. In addition, the diagram in Figure 3 (b
The transistor (G) in l is a teplection type nMO
The S transistor, or transistor a9, is an enhancement nMO8 transistor.

Incidentally, in the above embodiment, the EPROM was explained using Example G.

A similar effect can be obtained using a microcomputer with a built-in gEPROM or an EPROM, or a computer with a built-in EEFROME PROM. Further, although the case where there are 3 check bits is shown, there is no problem with a larger number of hints as long as the check bits are an odd number. Furthermore, in the majority circuit l, nMO8
Although the explanation was given using cMO8 as an example, there is no problem with cMO8.

〔Effect of the invention〕

As described above, according to the present invention, among all input data,
If the number of bits of the electronic injection type is more than half, the data is inverted by the writer and written, so the electronic injection type data can always be less than half of the written data. This has the effect of reducing the possibility of data volatilization. Furthermore, using a plurality of check bits has the effect of improving the reliability of the check bit itself.

[Brief explanation of drawings]

Figure gJ1 is an overall block diagram of a semiconductor memory device according to an embodiment of the present invention. FIG. 2 is a flowchart showing writing and reading in one embodiment of the present invention. @3 Figure is a circuit diagram showing a majority circuit in an embodiment of the present invention. FIG. 4 is a functional block diagram of a semiconductor memory device according to a conventional method. FIG. 5 is a flowchart showing writing and reading according to the conventional method. FIG. 6 is a diagram showing the structure, electron injection state, and erase state of a FAMO8 type memory cell. In addition, in Figure 2, (1) is an input data means, C2) is an input buffer, (3) is a memory section, (4) is a sense amplifier, (5) is an output buffer, (6) is an output data, ( 7)
is an address buffer, (8) is a decoder, (9) is a control circuit, αq is a conventional EPROM, (b) is a check bit, (6) is a majority circuit, QJ is an inverter, C4 is an exclusive OR gate, ( G) is an example of E according to the present invention.
PROM, αyu is AND gate, ση is OR gate, 1
181 is a degradation type n-MOS transistor, ■
1 is an evangelization Flln-MOS transistor, 2 is a single crystal semiconductor substrate, and 2 is a single crystal semiconductor substrate. ■ is the source and drain diffusion layer of the opposite conductivity type to the substrate. (to) is the floating gate into which electrons are injected, (to) is the control gate, (to) is the oxide film between the substrate and the floating gate, (to) is the oxide film between the 70-ing gate and the control gate, and (to) is the oxide film between the substrate and the floating gate. The field oxide film, (to), ■, c31) is aluminum. 3. In the figures, the same reference numerals indicate the same or equivalent parts.

Claims (2)

[Claims] (1) In a floating gate programmable read-only memory formed on a single crystal semiconductor substrate,
It has a check bit to store information that identifies whether the written data is inverted from the original data, and when reading, the contents of the read data are inverted depending on the contents of the check bit. 1. A semiconductor memory device characterized in that it determines whether or not data should be processed and outputs the original data content. (2) There are multiple check bits in a semiconductor memory device, and the data of the check bit is determined by taking a majority vote of the data of “0” and “1” in the check bit, and then the data of the check bit is determined. 2. The semiconductor memory device according to claim 1, which uses an EPROM.