JP2613660B2 - Nonvolatile semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a nonvolatile semiconductor memory device having a memory cell of a FAMOS (Floating Gate Avalanche Injection Metal Oxide Semiconductor) type.

<Prior Art> Conventionally, this type of nonvolatile semiconductor memory device is
EPROM (Electrically Programmable Read Only Memory) memory cells have a structure as shown in FIG. The memory cell includes a gate oxide film 42 covering a surface 41a of a semiconductor substrate 41, a floating gate (floating gate) 43 provided on the gate oxide film 42, and a substrate surface 41a on both sides of the floating gate 43. And a floating gate transistor having a source 44 and a drain 45. The respective ends 44a and 45a of the source 44 and the drain 45 overlap below the floating gate 43. Note that 46 indicates an interlayer insulating film, and 47 indicates a control gate. At the time of writing, 12 to 13 V is applied to the control gate 47 and 8 to 9 V to the drain 45,
44 is grounded, and electrons (hot electrons) generated by impact ionization near the end 45 a of the drain 45 are injected into the floating gate 43. Then, charges are accumulated in the floating gate 43, and the threshold voltage is changed to high or low according to data to be written. In order to complete writing in a short time,
The thickness of the gate oxide film 42 is reduced,
The electric field intensity applied to is increased. On the other hand, at the time of reading, 5 V is applied to the control gate 47 and 1-2 V is applied to the drain 45.
Is applied, and the source 44 is grounded so that the data represented by the threshold voltage is read.

<Problems to be Solved by the Invention> By the way, generally, in a SRAM (static random access memory) or the like, a voltage between a drain and a source at the time of reading (hereinafter, referred to as “bit line voltage”)
Is set to a large voltage close to the power supply voltage (5V). And, by reducing the junction capacitance of the drain, thereby reducing the capacitance of the bit line connected to the drain,
The data sense time is shortened, and the access time of the entire memory is shortened.

However, in the above-mentioned conventional EPROM, when the bit line voltage is raised to 1 to 2 V or more, for example, 5 V, and reading is continued for a long time, the gate oxide film is formed despite reading.
Electrons are gradually injected into the floating gate 43 through 42, and as a result, the threshold voltage may change and the stored content may change (read disturb). For this reason, the bit line voltage must be suppressed to 2 V or less, and the access time cannot be shortened.

Therefore, an object of the present invention is to provide an EPROM that can raise the bit line voltage to about the power supply voltage without causing inconvenience such that the stored contents change, thereby shortening the access time. is there.

<Means for Solving the Problems> In order to achieve the above object, an EPROM of the present invention includes a floating gate provided on an oxide film covering a surface of a semiconductor substrate, and a floating gate provided on one side of the floating gate. A first diffusion region provided so that an end thereof overlaps below the floating gate; and a substrate surface opposite to the first diffusion region with respect to the floating gate, an end portion being laterally separated from the floating gate. Having a second diffusion region provided to
A memory cell comprising a transistor; and a bit line selection circuit for selecting a bit line connected to the first diffusion region and a bit line connected to the second diffusion region by switching between writing and reading. Is the above
The first and second diffusion regions are operated as a drain and a source, respectively, while the first and second diffusion regions are operated as a source and a drain at the time of reading.

<Operation> At the time of writing, a bit line selection circuit selects a bit line connected to the first diffusion region and a bit line connected to the second diffusion region, and sets the first and second diffusion regions to drain and drain, respectively.
Operate as a source. That is, for example, 8 to 9 V is applied to the bit line connected to the first diffusion region, while
The bit line connected to the second diffusion region is grounded. First
The end of the diffusion region is provided so as to overlap below the floating gate, so that electrons generated by impact ionization near the end of the first diffusion region pass through the gate oxide film as in the conventional case. Injected into the floating gate. Therefore, writing is performed as in the conventional case.

On the other hand, at the time of reading, the bit line selection circuit selects the bit line connected to the first diffusion region and the bit line connected to the second diffusion region by replacing the bit line at the time of writing with the first and second bit lines.
Are operated as a source and a drain, respectively. The first diffusion region is grounded, while the second diffusion region is applied with a higher voltage than before, for example, a power supply voltage of 5V. At this time, electrons generated by impact ionization near the end of the second diffusion region are pulled up toward the gate oxide film by the electric field applied by the control gate. However, since the end of the second diffusion region is laterally separated from the floating gate, the electrons are not injected into the floating gate. Therefore, at the time of reading, the threshold voltage does not change, and the stored contents do not change. in this way,
Even if the bit line voltage is increased to about the power supply voltage at the time of reading, the inconvenience of changing stored contents does not occur. Therefore, by increasing the bit line voltage as compared with the related art, the junction capacitance of the second diffusion region operating as the drain can be reduced, and the capacitance of the bit line can be reduced. Therefore, the data sense time can be shortened, and the access time of the entire memory is shortened.

<Example> Hereinafter, the EPROM of the present invention will be described in detail with reference to examples.

FIG. 2 shows the configuration of the entire EPROM system of one embodiment. This EPROM has a memory cell array 11, a bit line pull-up 12, a Y selector 13, and a B selector
14, an address buffer 15, an input buffer 16, an X decoder 17, a predecoder 18, a Y decoder 19, a B decoder 20, a write and input control circuit 21, a write circuit 22, a sense amplifier / output The circuit 23 is provided. The Y selector 13, B selector 14, Y decoder 19 and B decoder 20 constitute a bit line selection circuit.

The memory cell array 11 is configured by arranging a plurality of FAMOS type memory cells as shown in FIG. 1 in a matrix. As shown in FIG. 1, each memory cell includes a gate oxide film 2 covering a surface 1a of a semiconductor substrate 1, a floating gate 3 provided on the gate oxide film 2, and a substrate surface on both sides of the floating gate 3. It comprises a first diffusion region 5, a second diffusion region 4 provided in 1a, an interlayer insulating film 6 covering the floating gate 3, and a control gate 7. The end 5a of the first diffusion region 5 overlaps below the floating gate 3, while the end 4a of the second diffusion region 4 is
It is formed so as to be spaced apart from the side. Therefore, in the substrate surface 1a, the vicinity of the end 5a of the first diffusion region 5 faces the floating gate 3 via the gate oxide film 2, while the vicinity of the end 4a of the second diffusion region 4 is close to the gate oxide film 2. Is opposed to the control gate 7. In the memory cell array 11, the control gate 7 of each memory cell is connected to a word line WL, and the first and second diffusion regions 5, 4 are connected to adjacent bit lines, respectively. For example, as shown in FIG. 3, the control gates 7 of the memory cells C ₀ , C ₁ ,..., C ₇ ,.
Connected to one word line WL. Also, the memory cell C ₀
Of the first and second diffusion regions 5 and 4 are adjacent bit lines BL ₇ ′ and B
Connected to L ₀ . Note that the first adjacent memory cell, the second diffusion region, and for example, the first diffusion region 4 and the second diffusion region of the memory cell C ₁ in the memory cell C ₀ is connected to the same bit line BL ₀ ing. Note that the above word line WL
Are selected by the pre-decoder 18 and the X-decoder 17 based on the address inputs A ₀ , A ₁ ,..., A ₈ input from the outside via the address buffer 15.

As shown in FIG.
Consists of p-channel transistors PT arranged in the row direction,
Each of the Y selector 13 and the B selector 14 includes an n-channel transistor NT arranged in the row direction. Each P-channel transistor PT of bit line pull-up 13
Is connected between the power supply and the bit line, and functions as a resistor for lowering the power supply voltage. The gates of the respective n-channel transistors of the Y selector 13 receive selection signals YoT ', YiT (i = 0,..., 7) from the Y decoder 19, respectively. Then, based on the contents of these nine signals, the memory cell array
Eight bit lines to which a bias is to be applied and eight ground lines (bit lines to be grounded) adjacent to the eight bit lines are selected from the whole. Each of the n-channel transistors of the B selector 14 has a gate provided with a selection signal BSnT (n = 0,..., 7) or a selection signal from the B decoder 20.
BSnG (n = 0,..., 7) is received. Then, based on the contents of these eight signals, a pair of adjacent bit lines and ground lines are selected from the eight bit lines and ground lines selected by the Y selector 13.

As shown in FIG. 4, the B decoder 20 includes three address lines 200 connected to the address buffer 15 and an inverter 2.
01, a NAND circuit 202, an n-channel transistor NT,
It comprises a p-channel transistor PT and an inverter 203. The NAND circuit 202 decodes the address inputs A ₁₂ , A ₁₃ , and A ₁₄ input via the address line 200 and a signal obtained by inverting them by the inverter 201, and outputs the n-channel transistor NT and the inverter 203. Through eight selection signals BSiT (i = 0,..., 7) and selection signals BSiG (i = 0,
.., 7) are output to the B selector 14.

As shown in FIG. 5, the Y decoder 19 includes three address lines 190 connected to the address buffer 15 and an inverter 1.
91, a NAND circuit 192, an n-channel transistor NT,
It includes a p-channel transistor PT, an inverter 193, and an inverter 194. Then, the address inputs A ₉ , A ₁₀ , and A ₁₁ input via the address line 190 and a signal obtained by inverting them by the inverter 201 are decoded by the NAND circuit 192, and the state of either active or inactive is determined. the take selection signal _{0, 1,} ..., _{7 (selection} signal Y _0, Y _1, ..., Y ₇
)) Are generated. When each selection signal Yi (i = 0, 1,..., 7) becomes active, a corresponding pair of bits connected to the memory cell Ci (subscript i represents the same number) shown in FIG. Indicates that a line is to be selected. At the same time, the inverter 194 makes the PG active during writing and inactive during reading.
Upon receiving the M signal, it inverts the signal to generate an R signal that is inactive during writing and active during reading. The PGM signal or the R signal is applied to the gate of the n-channel transistor NT so that the selection signals YoT ', YiT
(I = 0, ..., 7) and selection signal YiG (i = 0, ..., 7), Y
₇ Create G '. The contents represented by each selection signal YoT ′, YiT, YiG, YiG ′ are the above-mentioned selection signals at the time of writing and at the time of reading.
By replacing ₀ ,..., ₇ as shown in FIG. FIG. 6 is, for example, when the selection signal YoT is read Yo, when writing represents that the Y _1.
These selection signals YoT ', YiT, YiG, Y 7 G' , as shown in FIG. 3, the n-channel transistor NT of the Y selectors 13
Is output to the gate. The PGM signal is a chip enable signal input through an input buffer,
Generated by the write and input / output control circuit 21 based on the output enable signal.

This EPROM operates as follows as a whole. In addition,
A description will be given of the case where all the address inputs A ₉ ,..., A ₁₄ are set to “0” and writing and reading are performed to the memory cell Co shown in FIG.

Operation at the time of writing First, the Y decoder shown in FIG.
The selection signal o is activated (Yo is inactive) based on A ₉ , A ₁₀ , A ₁₁ (all “0”). Furthermore, a PGM signal from the write and input / output control circuit 21 (active)
In response, the contents of the selection signal are set as shown in the right column of FIG. 6, YoT 'and Y ₁ G representing Yo are activated, and output to the Y selector 13 shown in FIG. Y selector
At 13, the n-channel transistors NT receiving the selection signals YoT 'and Y ₁ G at their gates are turned on. Also, the fourth
The B decoder 20 shown in the figure has address inputs A ₁₂ , A ₁₃ , A ₁₄
Based on (all “0”), select signals BSoT and BSoG are activated and output to B selector 14. B selector
14, the BSoT and BSoG (in this case, BSn shown in FIG. 3)
T, BSnG) corresponding to the respective gates are turned on. By the operation of the Y selector 13 and the B selector 14, the bit line BL ₇ ′ conducts to the write circuit 22 via the B terminal, while the bit line BLo is grounded as a ground line. While the Vpp level (12 to 13 V) is applied to the control gate 7 of the memory cell Co via the word line WL, 8 to 9 V is applied from the write circuit to the first diffusion region 5 as a drain. , The second diffusion region 4 is grounded by a ground line BLo as a source. As shown in FIG. 1, since the end 5a of the first diffusion region 5 is provided so as to overlap below the floating gate 3, electrons generated by impact ionization in the vicinity of the end 5a In the same manner as in the conventional case, the floating gate 3 is injected through the gate oxide film 2 into the floating gate 3. Therefore, writing can be performed as in the conventional case.

Operation at the time of reading The Y decoder 19 activates the selection signal Yo as at the time of writing. However, at the time of reading, the PGM signal becomes inactive and the R signal becomes active. Accordingly, the Y decoder 19 sets the content of the selection signal as shown in the left column of FIG. 6, and outputs YoT and YoG to the Y selector 13 as active. In the Y selector 13, the n-channel transistors NT receiving the selection signals YoT and YoG at their gates are turned on. On the other hand, the B decoder 20 and the B selector 14 operate in exactly the same manner as at the time of writing. Therefore, the bit line BLo shown in FIG. 3 conducts to the sense amplifier / output circuit 23 via the terminal B, while the bit line BL ₇ ′ is turned on.
Are grounded as ground lines. That is, bit lines,
This means that the ground line has been switched between writing and reading. Then, in a state where the Vcc level (5 V) is applied to the control gate 7 of the memory cell Co via the word line WL, the first diffusion region 5 serves as a ground line as a source.
It is grounded through the BL ₇ '. The second diffusion region 4 operates as a drain. That is, the Vcc level is applied to the bit line pull-up 12, and the Vcc level (VH) is output when the storage content of the memory cell Co is "0" (when being written). On the other hand, when the storage content of the memory cell Co is "1" (when data is not written), the potential VL divided by the on-resistance of the memory cell Co and the on-resistance of the bit line pull-up 12 is output. . Here, when the storage content of the memory cell Co is “1”, hot electrons are generated near the end 4 a of the second diffusion region (drain) 4. However, since this end 4a is laterally separated from floating gate 3, generated electrons are not injected into floating gate 3. Therefore, at the time of reading, the threshold voltage of the memory cell Co does not change, and the stored content does not change.

As described above, this EPROM does not cause any inconvenience that the stored contents change even when the bit line voltage is increased to the power supply voltage Vcc at the time of reading. Therefore, by increasing the bit line voltage compared to the conventional,
The junction capacitance of the second diffusion region 4 can be reduced, and the capacitance of the bit line can be reduced. Therefore, the data
The sense time can be shortened, and the access time of the entire memory can be shortened.

<Effects of the Invention> As is clear from the above, the EPROM of the present invention has a floating gate provided on an oxide film covering the surface of a semiconductor substrate;
A first diffusion region provided on one surface of the substrate of the floating gate so that an end thereof overlaps below the floating gate;
A memory cell comprising a FAMOS transistor having, on the substrate surface opposite to the first diffusion region with respect to the floating gate, a second diffusion region provided such that an end is laterally separated from the floating gate; A bit line selection circuit for selecting the bit line connected to the first diffusion region and the bit line connected to the second diffusion region by switching between a write operation and a read operation. Since the second diffusion region is operated as a drain and a source, respectively, while reading, the first and second diffusion regions are operated as a source and a drain, respectively. Without reading, the voltage between the drain and the source can be increased to about the power supply voltage at the time of reading. Therefore, the data sensing time can be shortened, and the access time of the entire memory can be shortened.

[Brief description of the drawings]

FIG. 1 is a structural diagram showing a cross section of a memory cell of an EPROM according to an embodiment of the present invention, FIG. 2 is a diagram showing a configuration of the entire EPROM system, and FIG. 3 is a circuit configuration of a main part of the EPROM. 4 and 5 are diagrams showing the circuit configurations of the B decoder and Y decoder of the EPROM, respectively. FIG. 6 is a diagram showing a method of exchanging the selection signal of the Y decoder, and FIG. FIG. 3 is a diagram showing a cross-sectional structure of a memory cell of an EPROM. DESCRIPTION OF SYMBOLS 1 ... Semiconductor substrate, 2 ... Gate oxide film, 3 ... Floating gate, 4 ... Second diffusion region, 5 ... First diffusion region, 6 ... Interlayer insulating film, 7 ... Control gate, 11: Memory cell array, 12: Bit line pull-up, 13: Y selector, 14: B selector, 15: Address buffer, 16: Input buffer, 17: X decoder, 18: Predecoder , 19 ... Y decoder, 20 ... B decoder, 21 ... writing and input / output control circuit, 22 ... writing circuit, 23 ... sense amplifier / output circuit.

Claims (1)

(57) [Claims] A floating gate provided on an oxide film covering a surface of the semiconductor substrate; and a floating gate provided on one side of the floating gate.
A first diffusion region provided so that an end thereof overlaps below the floating gate; and a substrate surface opposite to the first diffusion region with respect to the floating gate, the end of which is lateral to the floating gate. A memory cell including a FAMOS transistor having a second diffusion region provided so as to be spaced apart from a memory cell, and a bit line connected to the first diffusion region and a bit line connected to the second diffusion region are written and read out. A bit line selection circuit that selects the first and second diffusion regions at the time of writing, and operates the first and second diffusion regions as a drain and a source at the time of writing, while using the first and second diffusion regions at the time of reading. A nonvolatile semiconductor memory device operated as a source and a drain, respectively.