JPS62239496A - Data output buffer device - Google Patents

Abstract

PURPOSE:To execute the data output of a high electric potential at high speed by boosting the electric potential of the gate of a transistor to output the data with a periodical signal to occur in a semiconductor. CONSTITUTION:By the internal part of a semiconductor memory, data are read, a signal phiA1 comes to be a high level, a signal; the inverse of phiA1 comes to be a low level, a transistor Q11 is turned off, a transistor Q19 is turned on, a nodal point; the inverse of NA1 comes to be a GND and a transistor Q17 is turned off. On the other hand, a transistor Q12 is turned on, a transistor Q18 is turned off and the electric potential of a nodal point NA1 rises. Since a signal phiB is made into a high level and a transistor Q15 is turned on, the electric potential of the nodal point NA1 is boosted up to an electric power source VCC level by the charge of a nodal point NB2 quicker than when the potential is charged only by the transistor Q12. Continuously, when the signal phiA1 is made into a low level while the signal phiB is a high level, the transistor Q12 is turned off, and accompanying the amplitude of a signal phif, the level of the nodal point NA1 is boosted to an electric power source VCC or above by a transistor Q13, a transistor Q14 and the transistor Q15.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data output buffer device, and more particularly to a data output buffer device that outputs data from a semiconductor memory.

Note that the following explanation uses N-channel fi as a transistor.
A MOS transistor is used, and unless otherwise specified, the transistor is of an enhancement type.

[Conventional technology]

FIG. 3 is a circuit diagram showing an example of a conventional data output buffer device.

In FIG. 3, the drain of the transistor Q31 is connected to the power supply Vcc, the gate signal φ is connected, the source is connected to the gate of the transistor Q34, and the transistor Q3
The drain of 2 is connected to the power supply Vcc, the gate is connected to the signal φ, the source is connected to the gate of the transistor Q33, and the drain of the transistor Q33 is connected,
The source of transistor Q34 is connected to IdGND, the drain of transistor Q35 is connected to the source of transistor Q32 and the gate of transistor Q33, the gate is connected to signal 7A, the source is connected to GND, and the drain of transistor Q36 is connected to the source of transistor Q31 and transistor Q34. , the gate receives the signal φ,
The sources are each connected to GND.

Next, the operation of this circuit will be explained using the timing chart shown in FIG.

Until data is read from inside the semiconductor memory, the node Nλ3 and the node NA3 are set to GND by another circuit. Subsequently, the data is read out and the signals φ and φ are read out.
A person becomes high level or low level. At this time, the nodes N3 and NA3 are at a low level of 70-ting.

First, a case will be described in which the φ person is at a high level and the φ person is at a low level based on data read from the inside. When the φ person changes to a high level and the φ person remains at a low level,
Transistor Q31 is turned off and transistor Qsa is turned on. As a result, the node NA3 becomes a low level, and the transistor Q34 is turned off. On the other hand, transistor Q3t
turns on and transistor Qss turns off, so the node NA
3 becomes a high level, transistor QC3 is turned on, and the output D out outputs a high level. φ people are at a high level φ
Although the case where the person is at a low level has been described, conversely, when the φ person is at a low level and φA is at a high level, the same holds true: NA3 is at a low level, node NA3 is at a high level, and the output Dout is at a low level.

[Problem that the invention seeks to solve]

However, in the conventional example, when outputting a high level to the output D out, the node NA3 is charged by the signal φ using only the transistor Qst.
The level of person 3 is at most the level of the power supply VCC, and the output D
When the threshold voltage of transistor Q33 is VT, the level of out only rises to the level of (power supply Vcc - VT), the charging time is still long, and the output Dou
There was a drawback that the response of t was delayed.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data output buffer device that has a sufficiently high level of output and is still capable of outputting at high speed.

[Means for solving problems]

The data output buffer device of the present invention is a data output buffer device for a dynamic semiconductor memory, in which the gate potential of an output transistor that outputs a signal read from the inside of the semiconductor memory to the outside is controlled by a periodic signal generated inside the semiconductor memory. The special feature is that the signal is used to boost the voltage.

〔Example〕

Hereinafter, the present invention will be explained with reference to the drawings.

FIG. 1 is a circuit diagram showing an embodiment of the present invention.

The drain of the transistor Q11 is connected to the power supply VCC, the gate is connected to the signal φ, and the source is connected to the node N1, and the drain of the transistor Q+2 is connected to the power supply VCC, the gate is connected to the signal φ, and the source is connected to the node NAl. The drain and gate of the transistor Q+3 are connected to the power supply VCC, the source is connected to the node NB2, and
The drain and gate of transistor Q14 are connected to node NBI
, the source is connected to the node NB2, the drain of the transistor Q I M is connected to the node NB2, the gate is connected to the signal φB, and the source is connected to the node NAI, the drain of the transistor Q16 is connected to the power supply VCC, and the gate is connected to the node N The drain of transistor Q17 is connected to l) out, the gate is connected to node NAl, the source is connected to GND, the drain of transistor Q18 is connected to node N1,
The gate is connected to φ, the source is connected to GND, the drain of transistor Qls is connected to node NA1, the gate is connected to φ, and the source is connected to GND, and one of the capacitors C1 is connected to node NfHK. The two terminals are respectively connected to the signal φf.

Next, the operation of this embodiment will be explained with reference to the evening/f timing chart shown in FIG.

First, before data is read from inside the semiconductor memory, the signal φM and the signal φE□ are at a low level, and the signal φ8 is also at a low level. Node Nλ1 and node NA
I'm also at a low level. Here, when the signal φf is at a low level, the node NBI is also at a low level and the transistor Q! 3 turns on. On the other hand, transistor Q14 is off. This increases the potential at node NB1. Subsequently, when the signal φf becomes high level, the potential at the node N B 1 further increases. At this time, transistor Q13 is off.

On the other hand, transistor Q14'd is turned on, and node N8□
level becomes high level. Since this Tosa No. 100 φ8 is at a low level, the transistor Qls is off. By repeating the high and low levels of the signal φf, the potential at the node NB□ rises significantly. Thereafter, data is read out from inside the semiconductor memory, and the signal φA1 becomes high level and the signal φA1 becomes low level.

As a result, transistor Qu turns off, transistor Q
19 is turned on, node NA1 becomes GND, and transistor Q+7i is turned off. On the other hand, transistor Q12 is turned on and transistor Q1d is turned off. This allows the node Nλ
The potential of 1 increases. Furthermore, since the signal φB is at a high level, the transistor Qxs is turned on. As a result, the potential at the node NAI is boosted to the power supply Vcc level by the charge at the node NB2 faster than charging by the transistor Q12 alone.

Subsequently, when the signal φAl is set to a low level while keeping the signal φB at a high level, the transistor Q12 is turned off.

Then, as the amplitude of the signal φf increases, the transistor Q13
．． Transistor Q14. The level of the node NAl is boosted to a level higher than the power supply Vcc by the h transistor Q1s.

With this, the high level of the output Dout can be made sufficiently high.

According to this embodiment, by boosting the gate of the output transistor using the signal φf generated inside the semiconductor memory, an output signal of a sufficiently high level can be outputted at a higher speed! Able to assist and create.

〔Effect of the invention〕

As explained above, the present invention has the advantage of boosting the voltage by using the gate potential of the transistor that outputs data and a periodic signal generated inside the semiconductor, which enables faster gi constant potential data output. An output buffer device is obtained.

[Brief explanation of drawings]

Fig. 1 is a circuit diagram showing the one-step processor II of the present invention, Fig. 2 is a timing chart of the operation of the circuit 1A, Fig. 3 is a circuit diagram of a conventional data output 7777 circuit, and Fig. 4 is a circuit diagram of a conventional data output 7777 circuit. 4 is a timing chart of the operation of the circuit of FIG. 3. FIG. Dout−・−・Output node, NA”, iA□t N
A3, πA31NB1. NB2...Node, Q
lt～Q19. Q31~Q3G...Enhancement type N-channel MOS transistor・φAl・
φperson 1・φf・φB φperson 3・φA3°”°°°°Signal 0 number＾ Agent Patent attorney Uchihara Yo 1 ÷ Figure 3 Figure 4

Claims (1)

[Claims] In a data output buffer device for a dynamic semiconductor memory, the gate potential of an output transistor that outputs a signal read from inside the semiconductor memory to the outside is boosted by using a periodic signal generated inside the semiconductor memory. A data output buffer device characterized by: