JPS62237730A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS62237730A JPS62237730A JP61079316A JP7931686A JPS62237730A JP S62237730 A JPS62237730 A JP S62237730A JP 61079316 A JP61079316 A JP 61079316A JP 7931686 A JP7931686 A JP 7931686A JP S62237730 A JPS62237730 A JP S62237730A
- Authority
- JP
- Japan
- Prior art keywords
- film
- mesa
- etching
- protective film
- semiconductor substrate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 25
- 238000004519 manufacturing process Methods 0.000 title claims description 6
- 230000001681 protective effect Effects 0.000 claims abstract description 25
- 239000000758 substrate Substances 0.000 claims abstract description 23
- 238000005530 etching Methods 0.000 claims abstract description 20
- 238000001259 photo etching Methods 0.000 claims 2
- 229920002120 photoresistant polymer Polymers 0.000 abstract description 6
- NBIIXXVUZAFLBC-UHFFFAOYSA-N Phosphoric acid Chemical compound OP(O)(O)=O NBIIXXVUZAFLBC-UHFFFAOYSA-N 0.000 abstract description 4
- KRHYYFGTRYWZRS-UHFFFAOYSA-N Fluorane Chemical compound F KRHYYFGTRYWZRS-UHFFFAOYSA-N 0.000 abstract description 3
- 150000004767 nitrides Chemical class 0.000 abstract description 3
- 229910000147 aluminium phosphate Inorganic materials 0.000 abstract description 2
- 238000005229 chemical vapour deposition Methods 0.000 abstract description 2
- 229960002050 hydrofluoric acid Drugs 0.000 abstract 1
- 238000000034 method Methods 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000015556 catabolic process Effects 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 238000002955 isolation Methods 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 239000002184 metal Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 229910052710 silicon Inorganic materials 0.000 description 1
- 239000010703 silicon Substances 0.000 description 1
- 238000007740 vapor deposition Methods 0.000 description 1
Abstract
Description
【発明の詳細な説明】
(産業上の利用分野)
本発明は、メサ構造の頂上部周辺に発生する欠けやクラ
ック等を防止した半導体装置の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a method of manufacturing a semiconductor device that prevents chips, cracks, etc. that occur around the top of a mesa structure.
(従来の技術)
が多く用いられている。これはメサ構造によシ、浮遊容
量を減少させて高周波での有効な動作を可能にし、プレ
ーナ型に比べて素子表面のリーク電く
流を無要し、高耐圧化を実現している。また素子分離の
一手段として用いられることもある。(conventional technology) is often used. This mesa structure reduces stray capacitance, enables effective operation at high frequencies, eliminates the need for leakage current on the element surface compared to planar types, and achieves high breakdown voltage. It is also sometimes used as a means of element isolation.
従来、上記メサ構造の製造方法は、第2図(a)。A conventional method for manufacturing the mesa structure is shown in FIG. 2(a).
(b)に示す工程が一般に用いられている。The process shown in (b) is generally used.
まず、第2図(alに示すように半導体基板1の能動層
領域側(能動層領域は図示せず。以下も同様)に全面に
わたってケミカルペー/IP−デIジション(Chem
ical Vapor Deposition 、以下
CVDど称する。)法により保護膜2を形成する。つい
で保護膜2上にホトレジスト膜3を形成し、ホトリノグ
ラフィーによシ、エツチング除去すべき領域の半導体基
板1上のホトレジスト膜3と保護膜2を選択的に除去す
る。その後ホトレノスト膜3をすべで除去する。First, as shown in FIG.
ical vapor deposition, hereinafter referred to as CVD. ) method to form the protective film 2. Next, a photoresist film 3 is formed on the protective film 2, and the photoresist film 3 and the protective film 2 on the semiconductor substrate 1 in the area to be etched away are selectively removed by photolithography. After that, the photorenost film 3 is completely removed.
次に第2図(b)に示すようにメサエッチングを行なっ
て、メサ構造を形成する。このときメサエッチングのマ
スクとして用いられた保護膜2はそのまま残って庇4が
形成される。Next, as shown in FIG. 2(b), mesa etching is performed to form a mesa structure. At this time, the protective film 2 used as a mask for mesa etching remains as it is, and the eaves 4 are formed.
(発明が解決しようとする問題点)
従来のメサ構造の形成方法においては、第2図(b)に
示すように形成された庇4を除去する目的で半導体基板
1を液体中に入れて超音波振動を加え合が発生し、庇部
分4の絶縁保護膜が切片状に残留してしまう。この時同
時に半導体基板1のメサ頂上部周辺に欠けやクラックが
発生するという問題があった。(Problems to be Solved by the Invention) In the conventional method for forming a mesa structure, the semiconductor substrate 1 is immersed in a liquid and subjected to ultraviolet treatment in order to remove the eaves 4 formed as shown in FIG. 2(b). When sonic vibration is applied, a collision occurs, and the insulating protective film on the eaves portion 4 remains in the form of a piece. At the same time, there was a problem in that chips and cracks occurred around the top of the mesa of the semiconductor substrate 1.
この欠けやクラックは、半導体基板1の一部の損傷であ
り、リーク電流や特性劣化の原因となる。These chips and cracks are damage to a part of the semiconductor substrate 1, and cause leakage current and characteristic deterioration.
またその後の金属膜配線工程においても、正常な配線が
得られず歩留を低下させる要因でもあった。Further, in the subsequent metal film wiring process, normal wiring could not be obtained, which was a factor in reducing yield.
本発明は上記の問題を解決するためになされたもので、
メサエッチングによって形成される庇を、半導体基板に
損傷を与えることなく除去する方法を提供することを目
的とする。The present invention was made to solve the above problems,
An object of the present invention is to provide a method for removing an eave formed by mesa etching without damaging a semiconductor substrate.
(問題点を解決するための手段)
上記目的を達成するために、本発明は半導体基板上に選
択エツチングが可能な絶縁保護膜を2層形成する。ここ
で下層保護膜は半導体基板と同一エツチング性を有して
もよく、上層保護膜は下層保護膜および半導体基板と異
なったエツチング性を有する材質で形成する。この2層
構造の保護膜をメサエッチングのマスクに用いる事によ
シ、最終的に庇のないメサ構造を得る方法である。(Means for Solving the Problems) In order to achieve the above object, the present invention forms two layers of insulating protective films that can be selectively etched on a semiconductor substrate. Here, the lower protective film may have the same etching properties as the semiconductor substrate, and the upper protective film is formed of a material having different etching properties from those of the lower protective film and the semiconductor substrate. By using this two-layer protective film as a mask for mesa etching, a mesa structure without eaves is finally obtained.
(実施例)
第1図(,1〜(d)にこの発明の一実施例を示す。図
において1,3.4は第2図の同一符号と同一または相
当する部分を示し、21は半導体基板1(例えば、シリ
コン)とエツチング性が同じでも良い絶縁保護膜(例え
ば、酸化膜)、22は半導体基板1および絶縁保護膜2
1とエツチング性が異なる絶縁保護膜(例えば、窒化膜
)である。(Embodiment) An embodiment of the present invention is shown in FIG. An insulating protective film (e.g., oxide film) that may have the same etching properties as the substrate 1 (e.g., silicon); 22 denotes the semiconductor substrate 1 and the insulating protective film 2;
This is an insulating protective film (for example, a nitride film) having a different etching property from No. 1.
第1図(a)は半導体基板1の能動層領域側(能動層領
域は図示せず。以下も同様)にCVD法により、全面に
渡って酸化膜21を形成し、ついで酸化膜チング除去す
べき半導体基板1上のホトレジスト膜3と保護膜21.
22を選択的に除去した状態を示す。その後ホトレ・シ
スト膜3をすべて除去する。In FIG. 1(a), an oxide film 21 is formed over the entire surface of the semiconductor substrate 1 on the active layer region side (the active layer region is not shown; the same applies hereafter) by the CVD method, and then the oxide film is removed by chipping. A photoresist film 3 and a protective film 21 on the semiconductor substrate 1.
22 is selectively removed. After that, the entire photoresist film 3 is removed.
第1図(b)は上記保護膜の選択的除去を行なった半導
体基板1にメサエッチングを行い、この時形成される庇
4が窒化膜22とメサエッチングにおいて半導体基板1
よりエツチングレートが小さい酸化膜21の一部とで構
成されている事を示す。In FIG. 1(b), mesa etching is performed on the semiconductor substrate 1 from which the protective film has been selectively removed.
This shows that it is composed of a part of the oxide film 21 having a lower etching rate.
(第1図(c)は)弗酸系のエツチング液により庇4の
酸化膜部分のみを選択的にエツチング除去した状態を示
す。(FIG. 1(c)) shows a state in which only the oxide film portion of the eaves 4 has been selectively etched away using a hydrofluoric acid-based etching solution.
第1図(dlはメサの頂上部の窒化膜22をリン酸で選
択的にエツチング除去した状態を示す。FIG. 1 (dl shows the state in which the nitride film 22 at the top of the mesa has been selectively etched away with phosphoric acid.
(発明の効果)
以上説明したとおり、本発明によれば、メサエッチング
において形成された庇を、機械的振動に:・
よちないで除去するので、半導体基板は損傷を受けるこ
となく、以後のプロセス後完成する半導体素子に於て歩
留りが向上するとともに信頼性が向上するという効果が
ある。(Effects of the Invention) As explained above, according to the present invention, the eaves formed in mesa etching are removed without being subjected to mechanical vibration, so that the semiconductor substrate is not damaged and can be used for subsequent processing. This has the effect of improving the yield and reliability of semiconductor devices completed after the process.
第1図は本発明の一実施例で、半導体装置の製造方法を
工程順に示した断面図、第2図は従来の製造方法を工程
順に示した断面図である。
1・・・半導体基板、2,21.22・・・絶縁保護膜
、3・・・ホトレジスト膜、4・・・庇。FIG. 1 shows an embodiment of the present invention, and is a sectional view showing a method for manufacturing a semiconductor device in order of steps, and FIG. 2 is a sectional view showing a conventional manufacturing method in order of steps. DESCRIPTION OF SYMBOLS 1... Semiconductor substrate, 2, 21. 22... Insulating protective film, 3... Photoresist film, 4... Eaves.
Claims (1)
1の保護膜上に別の第2の保護膜を形成する工程と、上
記半導体基板上に形成された第1の保護膜と第2の保護
膜を選択的に除去して、メサ構造を形成するための被エ
ッチング領域を形成する工程と、上記ホトエッチ工程で
露出した領域の半導体基板をエッチング除去してメサ構
造を形成する工程と、上記メサエッチングによつて露出
した、メサ頂上部周辺の第1の保護膜を除去する工程と
、上記ホトエッチ工程で形成されたメサ型パターンの第
2の保護膜をすべて除去する工程とを含むことを特徴と
する半導体装置の製造方法。a step of forming a first protective film on the semiconductor substrate; a step of forming another second protective film on the first protective film; a first protective film formed on the semiconductor substrate; A step of selectively removing the second protective film to form an etched region for forming a mesa structure, and a step of etching away the semiconductor substrate in the region exposed in the photoetching step to form a mesa structure. a step of removing the first protective film around the top of the mesa exposed by the mesa etching; and a step of removing all the second protective film of the mesa pattern formed in the photoetching step. A method of manufacturing a semiconductor device, comprising:
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61079316A JPS62237730A (en) | 1986-04-08 | 1986-04-08 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP61079316A JPS62237730A (en) | 1986-04-08 | 1986-04-08 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS62237730A true JPS62237730A (en) | 1987-10-17 |
Family
ID=13686461
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP61079316A Pending JPS62237730A (en) | 1986-04-08 | 1986-04-08 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS62237730A (en) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012231157A (en) * | 2005-11-30 | 2012-11-22 | Lam Research Corporation | Method of determining target mesa configuration of electrostatic chuck |
-
1986
- 1986-04-08 JP JP61079316A patent/JPS62237730A/en active Pending
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2012231157A (en) * | 2005-11-30 | 2012-11-22 | Lam Research Corporation | Method of determining target mesa configuration of electrostatic chuck |
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