JPS6223608A - Digital signal mixing device - Google Patents

Abstract

PURPOSE:To prevent generation of distortion and mixing of noise to an output by providing a digital signal input terminal of S channel, a matrix element deciding circuit having a coefficient data output circuit, a digital signal mixing arithmetic circuit applying matrix operation to each coefficient data and a digital signal output terminal of T channel and applying the mixing without converting the digital signal itself. CONSTITUTION:Each input digital signal from the each input terminal 1 and a digital signal from each sample holding circuit and an A-D converter 16 are fed to each digital tone control circuit 18, whose output is fed to a digital signal mixing arithmetic circuit 19, where the S channel input digital signal is mixed to obtain the T channel output digital signal. The coefficient data is changed depending on the operation of the operating means and the matrix element of a storage device is rewritten, then the mixing ratio is selected freely. Further, the digital signal mixing device to which no various noise is mixed is obtained.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a digital signal mixing device suitable for mixing audio signals.

A conventional digital signal mixing device that mixes digitized multi-channel audio signals at a desired mixing ratio to obtain a new digitized multi-channel audio signal is shown in FIG. It is configured as follows. Below, first, a conventional mixing device will be explained with reference to FIG. 1.

That is, a plurality of channels of input digital signals are supplied from each input terminal +11 to each DA converter (2) to obtain a plurality of channels of input analog signals. A plurality of other analog signals, such as microphone signals, are supplied from each input terminal (3) to each amplifier (4). Each output of each DA converter (2) and each amplifier (4) is selected by each changeover switch (5) and supplied to each analog tone control circuit (6). The output of each analog tone control circuit (6) is supplied to an analog signal mixing circuit (7). A part of the mixed output of the analog signal mixing circuit (7) is supplied to the analog reverberation adding device (11), and its output is supplied to the tone control circuit (6) via the on/off switch (5'), and each of its outputs is is again supplied to the analog signal mixing circuit (7). A portion of the output analog signal of the mixing circuit (7) is supplied to each A-D converter (8) to obtain a plurality of output digital signals from each output terminal (9). In addition, the output terminal (10)
The output analog signal can be obtained as is.

However, such conventional digital signal mixing devices have the following drawbacks. That is, the D-A converter and the A
Since a -D converter is used, quantization noise is mixed into the output of the A-D converter. Since mixing is performed in the state of analog signals, distortion occurs due to the nonlinearity of the human output characteristics of the analog signal mixing circuit, and since analog signal mixing circuits are easily influenced by external noise, noise due to this also occurs. mixed into its output.

In view of this, the present invention proposes a digital signal mixing device that eliminates the above-mentioned drawbacks by performing mixing on digital signals as they are.

Embodiments of the present invention will be described in detail below with reference to FIG. 2 and FIGS. 4 and 8, which partially illustrate the invention in detail. In FIGS. 2 and 4, parts corresponding to those in FIG. 1 are designated by the same reference numerals and will be explained. First, FIG. 2 will be explained.

(3a) and (3b) are input terminals for a plurality of input analog signals, the former being a microphone signal input terminal and the latter being an auxiliary input terminal. (4) is an amplifier that amplifies the microphone signal. Each input terminal (3a).

Each input analog signal from (3b) is connected to each selector switch (
15) and is supplied to each sample hold circuit and A-D converter (16). Each input terminal +1)
The input digital signals from the sample and hold circuits and the digital signals from the A-D converter'a (16) are switched by the changeover switches (17) and supplied to the digital tone control circuits (18). , each input digital signal that is the output is sent to the digital signal mixing operation circuit (1
9).

Then, each output digital signal is outputted to each output terminal (9). In addition, a part of the output terminal (9) is shown by a broken line.
It is also possible to connect a D'-A converter (21) to obtain an output analog signal at the output terminal (10).
Also, a part of the output digital signal of the digital signal mixing operation circuit (19) is supplied to the digital reverberation adding device (22), and each output is sent to each tone control circuit (18) through each on/off switch (17'). and its output is supplied to the digital signal mixing operation circuit (19).

The digital signal mixing calculation circuit (19) mixes the input digital signals of the S channel to obtain the output digital signal of the T channel, and as will be described in detail with reference to FIG. It is equipped with a digital storage device (27) for storing signals. (
20) determines the S×T matrix element according to the desired mixing ratio of the S channel input digital signal and stores it in the storage device (27).
) is a matrix element determination circuit that stores the matrix elements in Furthermore, the digital signal mixing operation circuit (19) includes a matrix operation circuit (67) that performs matrix operation on the S channel input digital signal and the matrix elements sequentially read out from the digital storage device (27).

The digital tone control circuit (18) can obtain various frequency-output level characteristics as shown in FIG. 3 by specifying values such as low cut, high cut, bass, treble, and presence. is now possible.

Next, regarding Figure 4, the digital signal mixing operation circuit (19)
and the details of the matrix element determination circuit (20). (49) is an analog signal mixing circuit provided in the 1r column element determination circuit (20), and input terminals (4941) to (4
The input analog signal of the S channel is supplied to the output terminals (49-01) to (49-18), and the output analog signal of the T channel with the desired mixing ratio is obtained from the output terminals (49-01) to (49-C). is illustrated in FIG. 9, which will be described later.

In the present invention, this analog signal mixing circuit (49)
Considering as a black box, input analog signal Vb
The relationship between ~Vls and the output analog signal ν01~VOT is expressed by a determinant as shown in the following equation, and the characteristics of the mixing circuit (49) are as follows when all input analog signals Vh~Vls are set to O (volt). Set the output analog voltage 1 to v01'.

Here, to know the S×T elements of matrix (A), one of the input analog signals ν11 to Vls is set to 1 (volt) and the others are set to 0 (volt) and the output analog voltage VO
It turns out that it is sufficient to set 1 to VOT as ill.

Then, the voltage (analog voltage) of each element of this matrix (A) is converted into a digital signal, and this is stored in a digital storage device (2
7) and store it.

Now, the matrix element determination circuit (20) will be explained in detail. (48) is a drive circuit for the analog signal mixing circuit (49). In this drive circuit (4B), drive circuits as shown are provided between each of its input terminals (4B-II) to (48-Is) and output terminals (4B-Of) to (48-O5). This drive circuit is, for example, MO
Type 3 field effect transistor Ql, O2.

Consists of an inverter (66), input terminal (4B-11)
Input signals rlJ, rO supplied to ~(4B-IS)
Output terminal (48-01) to (4B-OS) according to J
Either a voltage of 1 volt is output from the power supply element B or a ground potential, that is, O volt is obtained. That is, if the input signal is rlJ, the transistor Q
1 is on, transistor Q2 is off and a voltage of 1 volt is output, and if the input signal is "0", transistor Q
1 is turned off, transistor Q2 is turned on, and the voltage at the O port is output.

(47) is a scanning pulse generation circuit (decoder), which is driven by the clock signal supplied thereto and outputs rlJ sequentially and cyclically to its output terminals (47-01'') to (47-OS). It is done like this.

direction, scanning pulse, output terminal (47-) of the generation circuit (47)
The output obtained at any output terminal (47-QC) except OS > and
f) and the output terminal (48-1(C+1)), respectively.

(50) is, for example, a 12-bit A-D converter to which the output of the analog signal mixing circuit (49) is supplied;
) to each output terminal of +f? It consists of one unified A-D converter (50-1) to (50-T).

(51) is a latch circuit to which the output of the A-D converter (50) is supplied, and the A-D converter (50-1) to (50-T)
One launch circuit (51-1) to (51-T
). (52-1) to (52-T) are respective output terminals of the latch circuits (51-1) to (51-T), which simultaneously serve as output terminals of the matrix element determination circuit (20).

Next, the clock circuit (68) will be explained. The clock signal from this is partially used not only by the matrix element determination circuit (20) but also by the digital signal mixing operation circuit (19). Reference numeral (40) denotes a clock generating circuit, which generates a rectangular wave clock pulse (first clock pulse) of -50% duty as shown in FIG. 5A at, for example, 2 MHz. This ml
The clock pulses are supplied to an S-base (for example, 5=40) counter (41). At the counter (41), Figure 5B
As shown in FIG. 5, the clock pulses are counted as 1°2, . . . This second figure in the fifth figure
The clock pulse is shortened and the time axis is changed again. This second
The clock pulses are fed to a U-adic (eg U = 50) counter (42). In the counter (42), the fifth
As shown in Figure E<1.2. . . . is counted as U, and U
Every time , a third clock pulse (frequency: 1 kHz) as shown in FIG. At the counter (43), as shown in Figure 5H...C-1, C, C
+1. . . ., a fourth clock pulse (frequency: 2511z) is output from this, and is supplied to the scanning pulse generation circuit (47).

Figure 5 ■ and J are the input terminals (49-(C+1)) and (49-() of the analog signal mixing circuit (49), respectively).
The waveform of the input terminal to C+2) is shown. Figure 5 shows the output terminal (49-0) of the analog signal mixing circuit (49).
The waveform of the output voltage of C+1)) reaches a constant voltage after a predetermined settling time after the rise of the input voltage supplied to the input terminals (49 to I(C+1)). The fifth diagram shows the output waveform of the AD converter (50-(C+1)). In this case, the output of the counter (42) is transmitted to the decoder (
44), and when the counter (42) counts from 1 to U (1<V<U), a start pulse as shown in FIG. 5F is obtained from the decoder (44). is supplied to the AD converter (50), thereby performing AD conversion. Further, the third clock pulse (FIG. 5G) from the counter (42) is supplied to the latch circuit (51), so that the A-D converter (50) (for example, (50-(C+1
) ) ) is the latch circuit (51) (therefore, (
51-(C+1) ) ) (as shown in Figure 5M)
Latched.

Thus, the input terminal (
If a voltage of 1 volt is sequentially supplied to 49-11) to (49-Is), the A-D conversion of each element of matrix (A) will be applied to latches 1iilvpI(51-1) to (51-Is).
T) You will be nilatched. The processing time for this 1 cycle is as short as 50+wsec after manual adjustment of the analog signal mixing circuit (49).

The contents of the latch circuit (51) are then supplied to and stored in the digital storage device (27) of the digital signal mixing operation circuit (19). Next, the digital signal mixing operation circuit (19
) will be explained. The digital storage device W (27) is T
S-stage shift registers (2'?-1) to (27
-T), and input terminals (27-11') to (
27-IT) and output terminal (27-01)~<z7-
'or >. For example, one stage shift register is 1
It is 2 bits. This digital storage device (27) is controlled by a first clock pulse from a clock generation circuit (40).

Each latch circuit (5) of the matrix element determination circuit (20)
The outputs of 1-1) to (51-T) are respectively output from the write logic circuit (
53-1) to (53-T) through digital storage devices (
27) each input terminal (27-11) to (27-IT)
supplied to Write logic circuit (53-1) to (53-
T) have the same configuration, so the write logic circuit (53-1) will be described as a representative.

In subtraction a (54), the shift register (27-) of the digital storage bag W (27) is calculated from the output of the latch circuit (51-1).
1) is subtracted, and the subtracted output is supplied to decoders (55) and (56). Deco i-da (5)
5) and (56), the output of the subtracter (54) is +
1. This is a circuit that outputs an output when the value is -1.

The outputs of the decoders (55) and (56) are connected to the AND circuit II (
59). Further, in the matrix element determination circuit (20), each clock pulse from the counters (41) and (43) is supplied to an exclusive OR circuit (45),
The output is passed through an inverter (46) to an AND circuit (5
9). The output of the latch circuit (51-1) and the output of the AND circuit (59) are connected to the output of the AND circuit (60).
). Also, the output of the output terminal (27-01) of the digital storage device (27) and the output of the AND circuit (59) passed through the inverter (61) are connected to the AND circuit 173.
(62). And the AND circuit (60)
, (62) passes through the OR circuit (63) to the shift register (27-1) of the digital storage device i (27).
) is supplied to the input terminal (27-11).

This write logic circuit (53-1), . . .
(53-T) operates as follows. Counter (41)
, <43), "1" is obtained at the output side of the inverter (46), and the input terminals (27-If) to (27-IT) of the digital storage device (27) match.
), the output of the latch circuits (51-1) to (51-T) or the output terminal (27-01) of the digital storage device (27)
An output of ~(27-OT) is provided. Then, each output of the latch circuits (51-1) to (51-T) and the output terminal (27-01) of the digital storage device Fft,' (27)
If the output difference with ~(27-OT) is either +1 or -1 times the LSB, the latch circuit (51-1) ~(
The output terminals (27-01) to (27) of the digital storage device (27) are assumed to contain noise.
-OT) input terminal (27-It) as is.
~ (27-IT), and if the output difference is neither +1 nor -1 times the LSB, the latch circuit (51-1
) to (51-T) are assumed to contain no noise, and the outputs of the latch circuits (51-1) to (51-T) are input to the input Tsuruko (27-11) of the digital storage device (27). )~
(27-IT).

Such write logic circuits (53-1) to (53-T)
By providing the matrix ``JJ! element determination circuit (20)
In the A-D converter 1!8 (50), as shown in Figure 6 (when the analog input terminal is near the quantization boundary voltage value, the digital output may change due to a slight input noise, for example, the code m This prevents noise from being mixed into the digital output by fluctuating between and m+1.

Note that even if the output of the latch circuit (51) does not contain noise, the output may be obtained from the decoder (55) or (56), and even in this case, the digital storage device (2
The outputs of the output terminals (27-01) to (27-OT) of 7) are supplied to the input terminals (2741) to (27-IT), but the latch circuits (51-1) to (51-T) Since the difference between the output of and the output of the output terminals (27-01) to (27-OT) is at most ±1 times the LSB, this difference can be ignored, and is rather a difference between the digital input to the digital storage device (27). This is preferable because it is possible to avoid deterioration in sound quality due to variation noise caused by the change of .

(26) input terminals (25-1) to (25-3
) is a 16-bit load and shift register that performs parallel-to-serial conversion.
26-3). This register (26) is supplied with the following signals. First, the clock ordering circuit (40)
The first clock pulse from (to Figure 7) is applied to the register (
26). Code contents of counter (41) (
B) in FIG. 7 is supplied to the decoder (36), and when the code S is obtained by the counter (41), the detection signal (D in FIG. 7) is obtained from the decoder (36) and the load pulse is sent to the register (26). (FIG. 7F), and this detection signal is phase-inverted by an inverter (37) and is supplied to the register (26) as a shift pulse (FIG. 7G).

Incidentally, FIG. 7C shows the second clock pulse from the counter (41).

(28) consists of seven 16-bit multipliers (2B-1) to (
28-T), which respectively have output terminals (27-01) to (27-O) of the digital storage device (27).
The outputs (I in Figure 7) from T) are sequentially supplied to the outputs CH1 to CHs (7th [g
He was accused of being IF(). Count @ (21 (-1) ~ (
The output of each adder (29-T) is 16 bits.
((29-1) to (29-T)). The outputs of adders a (29-1) to (29-T) are respectively stored in 16-bit accumulators (33) ((33-1) to
(33-T) ). Accumulator (33
-1) to (33-T) are controlled by the first clock pulse. Also, accumulators (33-1) to (33-
The outputs of T) are connected to AND circuits (32) ((32-1
) to (32-T) ). Counter (41)
The code content of is fed to the decoder (30) and the code l
is obtained by the counter (41), a detection signal (Fig. 7E) is obtained from the decoder (30), which is output from the inverter (3).
1) through the AND circuit (32) ((32-1)~
(32-T) ). The outputs of the AND circuits (32-1) to (32-T) are supplied to adders (29-1) to (29-2), respectively.

The outputs of the accumulators (33-1) to (33-T) (Fig. 7 J) are respectively 16-bit latch circuits (34) ((3
4-1) to (34-T)), and the output terminal (3
Output digital signals (K in Figure '1) are obtained at 5-1) to (35-T). Latch times 1/J (34-1) ~ (3
4-T) is the first clock pulse and decoder (30)
is controlled by the output of

In addition, a multiplier (28), an adder (29), an AND circuit (3
2) and the accumulator (33) constitute a matrix calculation circuit (67).

Next, referring to FIG. 8, a specific example of the analog signal mixing circuit (49) shown in FIG. 4 will be described. Incidentally, since the analog signal mixing circuit shown in FIG. 8 is a known circuit, the fourth
This will be briefly explained in relation to the embodiment shown in the figure.

(70) and (71) are faders and level adjusters, (72) is a pan pot (panoramic potentiometer), (73) is an inverter, and (74) is a synthesizer, each as shown in the legend. The circuit configuration is adopted. (7
5) and (76) are input terminals for input analog signals, each of which has K (=32) line signal input terminals (7
5) and L (=8) (lld echo return signal (which is an output signal from an analog reverberation addition device (not shown) provided corresponding to the digital reverberation addition device (22) in FIG. 2). It consists of an input terminal (76). (77
) to (81) are output terminals for output analog signals,
M (=24) (multi-channel signal output terminal of flit, N (=4) (4-channel signal output terminal of I&l), Q (=4) echo send signals (becomes input signal to the above-mentioned analog reverberation adding device) ) output terminal, R (=4
)(lld cue send signal output terminal and P(-2)
It consists of solo signal output terminals. Note that cue send means sending a signal to headphones, and solo means, for example, a signal of an anallancer's voice. (82) input circuits connected to input terminals (75), (83);
) are L (15 input circuits connected to the input terminals (76) of llil, respectively, (84) are M output circuits. S!A1 to S-1] are changeover switches. SWs are Phase inversion switch, SWl, SWl is front/rear switch, S'A< is channel odd/even and channel muting switch, S corner is bus selection switch, SWs
is a solo selection switch, SW7 is a 4-channel selection switch, SWe is a solo selection switch, SWs is a front/rear switch, SW+θ is a phase inversion switch, SWx+ is a channel muting switch, SWu is a channel selection switch, 5-13 is a 1/ This is a D selection switch.

According to the present invention described above, the coefficient data is changed in accordance with the operation of the operating means and the matrix elements of the storage device are rewritten, so that the operation can be performed in the same way as a conventional analog mixing device, and the mixing ratio can be changed freely. can be selected.

Further, since the digital signals are directly mixed as they are, it is possible to obtain a digital signal mixing apparatus free from the various noises mentioned at the beginning. In addition, even though the digital signals are directly mixed, the mixing is performed by performing matrix calculations on the input digital signals, which simplifies the configuration and makes it easy to vary the mixing state.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing a conventional digital signal mixing device, Fig. 2 is a block diagram showing an embodiment of the present invention, Fig. 3 is a characteristic curve diagram, and Fig. 4 is a diagram similar to Fig. 2. Fig. 5 is a waveform diagram, Fig. 6 is a characteristic curve diagram, Fig. 7 is a waveform diagram, and Fig. 8 is a block diagram showing the specific configuration of a part of Fig. 2. It is. (19) is a digital signal mixing operation circuit, (20) is a matrix element determination circuit, (27) is a digital storage device, (67)
is a matrix calculation circuit. Same Hidemori Matsukuma Figure 1 Figure 2' 1g 3o and death 18 3h□ 17 3,' 15 16. Jb
930, Go, ;O- 3b, 7113 q - ζ r + Fig. 3 - N + - 5 laps 8 and 11 [Fig.
I2 Figure 8 Procedure Nerti Official Book July 7, 1985 1. Display of the case Patent II filed on June 13, 1986 (5) 3. Person making the amendment Relationship with the case Patent applicant jJI. - Name (218) Sony Corporation Representative Director Noriyoshi Ohga 4, Agent 6, Number of inventions increased by amendment Patent claims In a digital signal mixing device configured to obtain a digital output signal, an operating means for determining the desired mixing coefficient, and an S channel analog input signal corresponding to the S channel digital input signal are provided on the operating means. An analog signal mixing circuit that is mixed with the desired mixing coefficient to obtain a T-channel analog output signal according to the position or change, and an input/output relationship of this analog signal mixing circuit is measured to determine the position or change of the operating means. a matrix element determination circuit that determines the mixing coefficient according to the change and outputs it as a digital signal of the S×T matrix element; a digital storage device that stores the digital signal of the S×T matrix element; The present invention is characterized by being provided with a matrix calculation circuit for performing matrix calculations on the digital input signal and the digital signals of the S×T matrix elements sequentially read out from the digital storage device to obtain the output digital signal of the T channel. Digital signal mixing device.

Claims (1)

[Claims] A digital signal mixing device configured to mix S-channel input digital signals to obtain a T-channel output digital signal, comprising: a digital signal input terminal into which the S-channel input digital signal is input; and an operating means for determining a desired mixing ratio of each input digital signal of the S channel to each output digital signal of the T channel, and corresponding to the mixing ratio and changing according to the operation of the operating means. a matrix element determining circuit having a coefficient data output circuit that outputs coefficient data; a matrix element storage device that stores the coefficient data as an S×T matrix element and rewrites the coefficient data according to changes thereof; and the S channel. a multiplication circuit for multiplying each input digital signal by each coefficient data of the S×T matrix element sequentially read from the matrix element storage device; an accumulator for storing the product output of the multiplication circuit; a digital signal mixing operation circuit that has an addition circuit that adds a digital value and a product output from a multiplication circuit, and performs a matrix operation on each coefficient data of the S×T matrix element with respect to the input digital signal of the S channel; A digital signal mixing device characterized in that the accumulator is provided with a digital signal output terminal for outputting the output digital signal of the T channel obtained.