JPS62235782A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS62235782A
JPS62235782A JP7941986A JP7941986A JPS62235782A JP S62235782 A JPS62235782 A JP S62235782A JP 7941986 A JP7941986 A JP 7941986A JP 7941986 A JP7941986 A JP 7941986A JP S62235782 A JPS62235782 A JP S62235782A
Authority
JP
Japan
Prior art keywords
region
gate
impurity density
semiconductor device
cathode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP7941986A
Other languages
Japanese (ja)
Other versions
JPH0553073B2 (en
Inventor
Tomoyoshi Kushida
知義 櫛田
Hiroshi Tadano
博 只野
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toyota Central R&D Labs Inc
Original Assignee
Toyota Central R&D Labs Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toyota Central R&D Labs Inc filed Critical Toyota Central R&D Labs Inc
Priority to JP7941986A priority Critical patent/JPS62235782A/en
Priority to US06/912,578 priority patent/US4752818A/en
Publication of JPS62235782A publication Critical patent/JPS62235782A/en
Publication of JPH0553073B2 publication Critical patent/JPH0553073B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391Gated diode structures
    • H01L29/7392Gated diode structures with PN junction gate, e.g. field controlled thyristors (FCTh), static induction thyristors (SITh)
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/30Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface
    • H01L29/32Semiconductor bodies ; Multistep manufacturing processes therefor characterised by physical imperfections; having polished or roughened surface the imperfections being within the semiconductor body
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/72Transistor-type devices, i.e. able to continuously respond to applied control signals
    • H01L29/739Transistor-type devices, i.e. able to continuously respond to applied control signals controlled by field-effect, e.g. bipolar static induction transistors [BSIT]
    • H01L29/7391Gated diode structures
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/70Bipolar devices
    • H01L29/74Thyristor-type devices, e.g. having four-zone regenerative action
    • H01L29/744Gate-turn-off devices

Abstract

PURPOSE:To simultaneously satisfy three conditions of a high speed switching, a low forward voltage drop and a high main electrode blocking voltage by forming local regions having relatively short charge carrier life on the vicinity of a gate region and a region depleted eventually in a main current interrupting step to an eventually depleted region. CONSTITUTION:A cathode region 11 and an anode region 12 made of opposite conductivity type high impurity density regions, a low impurity density region 14 formed at part between the regions 11 and 12, and a gate region 13 formed near the region 11 for controlling a main current are formed. in such a semicon ductor device, local regions 16, 15 having relatively short charge carrier life are formed on a region near the region 11, a region eventually depleted in a main current interrupting step and an eventually depleted region of the region 14. For example, after a P<+> type anode region 12, a P<+> type gate region 13 and an N<+> type cathode region 11 are respectively formed on an N-type silicon substrate, a photon beam is emitted from both side surfaces of an element to form regions 15, 16, thereby forming a static induction thyristor.

Description

【発明の詳細な説明】 (産業上の利用分野) 本発明は、大電力を扱うことのできる静電誘導型サイリ
スタやゲートターンオフ・サイリスタ等の半導体装置の
改良に関する。特に、本発明は、大電流の高速のスイッ
チングが可能で、かつ低い順方向電圧降下および高い主
電極間阻止電圧有するスイッチング用の半導体装置に間
する。
DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to improvements in semiconductor devices such as electrostatic induction thyristors and gate turn-off thyristors that can handle large amounts of power. In particular, the present invention provides a semiconductor device for switching that is capable of high-speed switching of large currents, and has a low forward voltage drop and a high blocking voltage between main electrodes.

(従来の技術) パルス幅変調方式による電動機の制御やスイッチング電
源等の応用に於て、スイッチング速度があまり速くない
と制御周波数を高くした場合、スイッチング損失が大き
くなり、装置の放熱設計が複雑になり、大型化を招くこ
とになる。制御周波数を低くして人間の可聴周波数(2
0k)lz以下)になると、装置の出す騒音が作業者に
不快感を与える。それを避けるため防音を施そうとすれ
ば結局は大型化を招くという矛盾を生じることになる。
(Prior art) In applications such as motor control and switching power supplies using pulse width modulation, if the switching speed is not very fast and the control frequency is increased, switching loss will increase and the heat dissipation design of the equipment will become complicated. This will lead to an increase in size. The control frequency is lowered to the human audible frequency (2
0k)lz), the noise emitted by the equipment causes discomfort to the operator. If you try to implement soundproofing to avoid this, you will end up with a contradiction in terms of increasing the size.

更に、トランス等インダクタンス機器はその重量が周波
数の1/2乗に反比例するといわれており、この点から
も制御周波数を低くすることは装置の大型化を招くこと
になる。
Furthermore, it is said that the weight of an inductance device such as a transformer is inversely proportional to the 1/2 power of the frequency, and from this point of view as well, lowering the control frequency will lead to an increase in the size of the device.

従って、このパルス幅変調方式による電動機の制御やス
イッチング電源の応用においては、制御周波数を高くす
る必要があり、そのためにも高速のスイッチングが要求
されている。また、損失においては前記スイッチング損
失の他にオン損失を少なくすることも重要であり、この
オン損失の低減には低い順方向電圧降下の実現が必要で
ある。
Therefore, in the application of electric motor control and switching power supplies using this pulse width modulation method, it is necessary to increase the control frequency, and for this reason, high-speed switching is also required. In addition to the switching loss, it is also important to reduce on-loss, and to reduce this on-loss, it is necessary to realize a low forward voltage drop.

更に、高電圧ライン系統への応用には数キロボルトとい
う高い主電極間阻止電圧が要求されている。
Furthermore, applications in high-voltage line systems require a high interelectrode blocking voltage of several kilovolts.

静電誘導型サイリスタおよびゲート・ターンオフ・サイ
リスタで代表される半導体装置は、互いに反対導電型高
不純物密度領域よりなるカソード領域およびアノード領
域の2つの主電極領域を備え、これらの2領域の間の一
部に低不純物密度領域を有し、カソード領域の近傍に主
電流を制御するゲート領域を持っている。
Semiconductor devices, typified by static induction thyristors and gate turn-off thyristors, have two main electrode regions, a cathode region and an anode region, each consisting of a high impurity density region of opposite conductivity type. It has a low impurity density region in part, and a gate region for controlling the main current near the cathode region.

この種の従来の半導体装置においては、一般に、前記低
不純物密度領域を厚くすることによって高い主電極間阻
止電圧を実現できることが知られている。また、そのよ
うな半導体装置において高速のスイッチングを実現する
ため、最も一般的には金拡散等によって前記低不純物密
度領域の全域にわたって一様に荷電担体の寿命を短くす
る方法が試みられている。しかしながら、この方法では
十分な高速化を実現できる程度に荷電担体寿命を短くす
ると、順方向の電圧降下が著しく高くなってしまい、高
速のスイッチングと低い順方向電圧降下を両立させるこ
とができなかった。
In this type of conventional semiconductor device, it is generally known that a high blocking voltage between main electrodes can be achieved by increasing the thickness of the low impurity density region. Furthermore, in order to achieve high-speed switching in such semiconductor devices, attempts have been made to uniformly shorten the lifetime of charge carriers over the entire region of the low impurity density region, most commonly by gold diffusion. However, with this method, if the charge carrier lifetime is shortened enough to achieve sufficient speedup, the forward voltage drop becomes significantly high, making it impossible to achieve both high-speed switching and low forward voltage drop. .

このような問題点を解決し、高速のスイッチングと低い
順方向電圧降下を両立させるため、静電誘導型サイリス
タにおいて前記低不純物領域中に主電流方向に対して局
所的に荷電担体寿命の比較的短い領域を設けた構造が提
案された。
In order to solve these problems and achieve both high-speed switching and low forward voltage drop, in the electrostatic induction thyristor, the charge carrier lifetime is reduced locally in the low impurity region with respect to the main current direction. A structure with a short region was proposed.

しかし、この構造では、荷電担体寿命の比較的短い領域
をただl箇所設けただけてあり、高い主電極間阻止電圧
を実現しようとして前記低不純物密度領域を厚くした場
合、十分な高速スイッチングと十分な低順方向電圧降下
とを両立することができなかった。
However, in this structure, only one region with a relatively short charge carrier life is provided, and when the low impurity density region is made thick in order to achieve a high main electrode blocking voltage, it is difficult to achieve sufficient high-speed switching and sufficient However, it was not possible to achieve both a low forward voltage drop and a low forward voltage drop.

(発明が解決しようとする問題点) 本発明の目的は、互いに反対導電型高不純物密度領域よ
りなるカソード領域とアノード領域との2つの主電極領
域領域を備え、それらの2つの主電極領域の間の一部に
低不純物密度領域を有し、前記カソード領域の近傍に主
電流を制御する制御するゲート領域を有する従来の半導
体装置における前述の問題点を解決することにある。
(Problems to be Solved by the Invention) An object of the present invention is to provide two main electrode regions, a cathode region and an anode region, each consisting of a high impurity density region of opposite conductivity type, The object of the present invention is to solve the above-mentioned problems in a conventional semiconductor device having a low impurity density region in a part thereof and a gate region for controlling the main current in the vicinity of the cathode region.

即ち、本発明は半導体装置において、高速のスイッチン
グ、低い順方向電圧降下および高い主電極間阻止電圧の
3つの条件を共に満足せしめる構造を提供することを目
的とするものである。
That is, an object of the present invention is to provide a structure in a semiconductor device that satisfies three conditions: high-speed switching, low forward voltage drop, and high blocking voltage between main electrodes.

(問題点を解決するための手段) 本発明は、前記目的を達成するため、互いに反対導電型
高不純物密度領域よりなるカソード領域とアノード領域
との2つの主電極領域を備え、前記2つの主電極領域の
間の一部に低不純物密度領域を有し、前記カソード領域
近傍に主電流を制御するゲート領域を有する半導体装置
において、前記低不純物密度領域の中の、ゲート領域の
近傍と、主電流の遮断過程の最後に空乏化する領域ない
し最後まで空乏化しない領域とに、荷電担体寿命の比較
的短い局所的領域を設けたことを特徴とする半導体装置
である。
(Means for Solving the Problems) In order to achieve the above object, the present invention includes two main electrode regions, a cathode region and an anode region, each consisting of a high impurity density region of opposite conductivity type. In a semiconductor device having a low impurity density region in a part between electrode regions and a gate region for controlling a main current near the cathode region, a region near the gate region and a main current in the low impurity density region This semiconductor device is characterized in that a local region with a relatively short charge carrier life is provided in a region that is depleted at the end of a current cutoff process or a region that is not depleted until the end.

(作用) 説明をわかりやすくするため、まず、互いに反対導電型
高不純物密度領域よりなるカソード領域とアノード領域
の2領域を備え、それらの2領域の間の一部に低不純物
密度領域を有し、前記カソード領域の近傍に主電流を制
御するゲート領域を有する半導体装置において、本発明
を実施する前の基本的動作を説明する。説明の便宜上方
ソード領域としてn+領領域アノード領域としてp+領
領域仮定する。
(Function) To make the explanation easier to understand, first, a cathode region and an anode region are provided, each having a high impurity density region of opposite conductivity type, and a low impurity density region is provided between these two regions. , a basic operation before implementing the present invention in a semiconductor device having a gate region for controlling a main current near the cathode region will be explained. For convenience of explanation, it is assumed that the upper sword region is an n+ region and the anode region is a p+ region.

上記構成の半導体装置は遮断状態では、低不純物密度領
域中に厚く空乏層が拡がるので、その半導体装置中の最
大電界強度は小さく押さえられ、高い主電極間阻止電圧
が実現できる。
In the semiconductor device having the above structure, in the cut-off state, a thick depletion layer spreads in the low impurity density region, so the maximum electric field strength in the semiconductor device is kept small, and a high blocking voltage between the main electrodes can be realized.

導通状態では、低不純物密度領域中にn+カソード領域
およびp”アノード領域から電子および正孔がそれぞれ
注入されるので、低不純物密度領域の抵抗は下がり低い
順方向電圧降下を実現できる。この際に、低不純物密度
領域の荷電担体寿命が長いと、導通状態における低不純
物密度領域の荷電担体密度がより高くなるので、順方向
電圧降下はより低くなる。
In the conductive state, electrons and holes are injected into the low impurity density region from the n+ cathode region and the p'' anode region, so the resistance of the low impurity density region decreases and a low forward voltage drop can be realized. , the longer the charge carrier lifetime in the low impurity density region, the higher the charge carrier density in the low impurity density region in the conductive state, and therefore the lower the forward voltage drop.

遮断状態から導通状態へのスイッチングはn+カソード
領域に対してゲート領域を正電圧にバイアスすることに
よって行う。ゲート領域を正電圧にバイアスすると、n
゛カソード領域ら低不純物密度領域へ電子が注入される
。注入された電子は、空乏層中の電界によって高速にp
+アノード領域の近傍に達し、p+アノード領域からの
正孔の注入を誘起する。注入された正孔は、空乏層中の
電界によって高速にn+カソード領域の近傍に達し、n
+カソード領域からの電子の注入を促進する。このよう
な繰り返しが正帰還作用となり、低不純物密度領域は電
子と正孔によって充満し、その領域は低抵抗となって半
導体装置は導通状態となる。従って、上述の導通過程は
高速である。
Switching from a blocked state to a conductive state is achieved by biasing the gate region to a positive voltage with respect to the n+ cathode region. Biasing the gate region to a positive voltage results in n
Electrons are injected from the cathode region to the low impurity density region. The injected electrons rapidly change to p due to the electric field in the depletion layer.
It reaches the vicinity of the + anode region and induces hole injection from the p+ anode region. The injected holes quickly reach the vicinity of the n+ cathode region due to the electric field in the depletion layer, and the
+ Promotes injection of electrons from the cathode region. Such repetition results in a positive feedback effect, and the low impurity density region is filled with electrons and holes, resulting in low resistance in the region and the semiconductor device becoming conductive. Therefore, the conduction process described above is fast.

導通状態から遮断状態へのスイッチングはn+カソード
領域に対してゲート領域を負電圧にバイアスすることに
よって行われる。ゲート領域が負電圧にバイアスされる
とn+カソード領域からの電子の注入が止まり、前述の
正帰還が止まる。その後は、低不純物密度領域中の電子
および正孔が再結合し消滅するのに従フて、ゲート領域
近傍から低不純物密度領域中に空乏層が拡がって行き、
半導体装置は遮断状態となる。つまり、この遮断   
  □過程は、低不純物密度領域中の荷電担体寿命に強
く依存する。その荷電担体寿命は、低い順方向電圧降下
を実現するため長いので、遮断過程はおそい。
Switching from a conductive state to a blocked state is accomplished by biasing the gate region to a negative voltage with respect to the n+ cathode region. When the gate region is biased to a negative voltage, injection of electrons from the n+ cathode region is stopped, and the positive feedback described above is stopped. Thereafter, as the electrons and holes in the low impurity density region recombine and disappear, the depletion layer spreads from the vicinity of the gate region into the low impurity density region.
The semiconductor device enters a cut-off state. In other words, this interruption
□The process strongly depends on the charge carrier lifetime in the low impurity density region. The charge carrier lifetime is long to achieve a low forward voltage drop, so the shutoff process is slow.

以上は本発明の特徴とする構成を含まない半導体装置に
ついて、その基本動作を説明したが、次に改良された本
発明による半導体装置の動作について説明する。即ち、
上記半導体装置に対して本発明を実施し、低不純物密度
領域の中の、カソード領域の近傍と、主電流遮断過程の
最後に空乏化する領域ないし最後まで空乏化しない領域
とに、荷電担体寿命の比較的短い局所的領域を設けた場
合の動作について説明する。
The basic operation of the semiconductor device that does not include the features of the present invention has been described above. Next, the operation of the improved semiconductor device according to the present invention will be described. That is,
The present invention is applied to the semiconductor device described above, and the charge carrier life span is increased in the vicinity of the cathode region in the low impurity density region and in the region that is depleted at the end of the main current cutoff process or the region that is not depleted until the end. The operation when a relatively short local area is provided will be explained.

主電極間阻止電圧は、低不純物密度領域の不純物密度に
主に依存するが、本発明の特徴とする前述の局所的領域
を設けることによって不純物密度は変化しないので、局
所的領域を設けない場合と同様に高い。
The main interelectrode blocking voltage mainly depends on the impurity density in the low impurity density region, but since the impurity density does not change by providing the above-mentioned local region, which is a feature of the present invention, when no local region is provided. as well as high.

順方向電圧降下は、導通状態における低不純物密度領域
の荷電担体密度分布に主に依存するが、本発明の前記局
所的領域を設けることによって、荷電担体密度分布は局
所的影響しか受けないので、順方向電圧降下の上昇は小
さい。
The forward voltage drop mainly depends on the charge carrier density distribution in the low impurity density region in the conductive state, but by providing the local region of the present invention, the charge carrier density distribution is only locally influenced. The increase in forward voltage drop is small.

遮断状態から導通状態へのスイッチングは、低不純物密
度領域への荷電担体の注入量が、再結合量に比較して非
常に大きな場合再結合量に依存しない。従って、本発明
の特徴とする局所的領域を設けても、その導通過程は高
速のままである。
Switching from the blocking state to the conducting state does not depend on the amount of recombination if the amount of charge carriers implanted into the low impurity density region is very large compared to the amount of recombination. Therefore, even if a local region, which is a feature of the present invention, is provided, the conduction process remains fast.

導通状態から遮断状態へのスイッチングは、低不純物密
度領域の荷電担体寿命に主に依存し、本発明の構成によ
って非常に高速となる。その理由を以下に詳しく説明す
る。
The switching from the conducting state to the blocking state mainly depends on the charge carrier lifetime of the low impurity density region and is very fast with the configuration of the present invention. The reason for this will be explained in detail below.

ゲート近傍に設けた荷電担体寿命の比較的短い局所的領
域は、n+カソード領域前面の正孔密度を下げてn4″
カソード領域からの電子の注入を止めるのを助けると共
に、低不純物密度領域中の荷電担体密度を下げることに
よって、遮断過程の前半の高速化に有効である。しかし
ながら、遮断過程において、ゲート領域近傍から低不純
物密度領域の空乏化が進み、その局所的領域が空乏化す
ると、もはや荷電担体の消滅にとって有効でなくなり、
遮断過程の高速化に寄与しない。一方、主電流の遮断過
程において最後に空乏化する領域ないし最後まで空乏化
しない領域に設けた荷電担体寿命の比較的短い局所的領
域は、主電流遮断過程前半で低不純物密度領域中の荷電
担体を再結合させ消滅させるが、前記定義から遮断過程
の後半でより有効に作用することは明かである。従って
、その局所的領域は主に遮断過程の後半の高速化に有効
である。即ち、荷電担体寿命の比較的短い本発明による
局所的な2領域を共に設けることによってのみ、主電流
遮断過程の著しい高速化が達成される。どちらか一方の
みでは遮断過程の前半あるいは後半が高速化されるだけ
であり、しかも高速化の程度は低い。
A local region with a relatively short charge carrier lifetime provided near the gate reduces the hole density in front of the n+ cathode region and
This is effective in speeding up the first half of the blocking process by helping to stop the injection of electrons from the cathode region and by lowering the charge carrier density in the low impurity density region. However, during the blocking process, depletion of the low impurity density region from the vicinity of the gate region progresses, and when that local region becomes depleted, it is no longer effective for the disappearance of charge carriers.
Does not contribute to speeding up the shutoff process. On the other hand, a local region with a relatively short charge carrier life that is created in a region that is the last to be depleted in the main current cutoff process or a region that is not depleted to the end is a localized region that has a relatively short charge carrier life. It is clear from the above definition that it acts more effectively in the latter half of the blocking process. Therefore, the local area is mainly effective for speeding up the latter half of the blocking process. That is, only by jointly providing two local regions according to the invention with relatively short charge carrier lifetimes can a significant speed-up of the main current interruption process be achieved. If only one of them is used, only the first half or the second half of the shutoff process will be sped up, and the degree of speeding up will be low.

以上に説明したように、本発明は、主電極間阻止電圧を
得るための低不純物密度領域の中の、カソード領域の近
傍の領域と、主電流遮断過程の最後に空乏化する領域な
いし最後まで空乏化しない領域とに、荷電担体寿命の比
較的短い局所的領域を共に設けることによって、高い主
電極間阻止電圧、低い順方向電圧降下、および高速のス
イッチングを同時に実現することができる。
As explained above, the present invention applies to the region near the cathode region in the low impurity density region for obtaining the main interelectrode blocking voltage, and the region to be depleted at the end of the main current cutoff process. By providing a non-depleted region together with a localized region with a relatively short charge carrier lifetime, it is possible to simultaneously achieve a high inter-electrode blocking voltage, a low forward voltage drop, and high-speed switching.

(実施例) 順11丸1 本発明を表面ゲート型nチャネル静電誘導型サイリスタ
に対して適用した第1実施例について説明する。nチャ
ネル型の場合、基本的にはp4″n−nlあるいはp”
nn−n+ダイオードのカソードとなるn+領域近傍に
p+のゲート領域をメックユ状或いはストライプ状に設
けた構造を有する。
(Example) Order 11 Circle 1 A first example in which the present invention is applied to a surface-gate n-channel static induction thyristor will be described. In the case of n-channel type, basically p4″n-nl or p”
It has a structure in which a p+ gate region is provided in a mekyu shape or a stripe shape near an n+ region which becomes a cathode of an nn-n+ diode.

第1図は第1実施例の静電誘導型サイリスタの断面構造
を1ユニット分だけ示すものである。
FIG. 1 shows the cross-sectional structure of one unit of the electrostatic induction thyristor of the first embodiment.

不純物密度が約I X 10”cm ”、厚さが約26
0μmのn型シリコン基板に対して、一方の表面からボ
ロンを全面に拡散し、拡散深さ10μmのp+アノード
領域12を形成する。次にもう一方の表面からボロンお
よびヒ素を順次選択拡散して拡散深さ4μmのp+ゲー
ト領域13および拡散深さ0.5μmのn+カソード領
域11をそれぞれ形成する。その後、カソード領域11
、アノード領域12、ゲート領域13にそれぞれ結合し
た厚さ6μmのアルミニウム電極配線11′、を12’
、13’施す。lOは絶縁膜である。最後に、素子の両
表面から陽子線を1.1MeVのエネルギーで約lXl
0”陽子粒/cm2の照射量だけ照射し、領域15.1
6を形成して第1図に示した本発明の構造の静電誘導型
サイリスタを制作した。1.1MeVのエネルギーを持
つ陽子線は素子表面から約20μmの深さまで透過する
。陽子線の照射による結晶格子への損傷の度合いは、陽
子線の透過する深度の限界の位置付近にある領域が陽子
線の通過経路に属する領域より甚だしく大きい。従って
、荷電担体寿命を減少させた局所的領域15.16は本
実施例の場合、素子表面より約20μmの深さの近傍に
局在していることになる。
Impurity density is about I x 10"cm", thickness is about 26
Boron is diffused over the entire surface of a 0 μm n-type silicon substrate from one surface to form a p + anode region 12 with a diffusion depth of 10 μm. Next, boron and arsenic are sequentially selectively diffused from the other surface to form a p + gate region 13 with a diffusion depth of 4 μm and an n + cathode region 11 with a diffusion depth of 0.5 μm. After that, the cathode region 11
, 6 μm thick aluminum electrode wirings 11' and 12' connected to the anode region 12 and gate region 13, respectively.
, 13' is applied. IO is an insulating film. Finally, a proton beam is emitted from both surfaces of the device at an energy of 1.1 MeV to approximately 1Xl.
Irradiated with a dose of 0" proton particle/cm2, area 15.1
6 to produce an electrostatic induction thyristor having the structure of the present invention shown in FIG. A proton beam with an energy of 1.1 MeV penetrates to a depth of about 20 μm from the element surface. The degree of damage to the crystal lattice due to proton beam irradiation is significantly greater in the region near the limit of the depth through which the proton beam can penetrate than in the region belonging to the proton beam passage path. Therefore, in this example, the local regions 15 and 16 in which the charge carrier lifetime is reduced are localized at a depth of approximately 20 μm from the element surface.

主電極間阻止電圧は、順方向および逆方向共に約IKV
であり、この値は局所的領域15.16の有無に依存し
ない。
The main interelectrode blocking voltage is approximately IKV in both forward and reverse directions.
, and this value does not depend on the presence or absence of the local region 15.16.

順方向電圧降下は、アノード電流■A(主電流)が50
Aのとき、局所的領域15.16を共に持たない静電誘
導型サイリスタで1.3V、局所的領域15.16を共
に持つ本実施例の静電誘導型サイリスタで2.95Vと
、本発明を採用してもわずか2倍程度の増加にとどまる
The forward voltage drop is when the anode current ■A (main current) is 50
In the case of A, the voltage is 1.3V for the static induction thyristor that does not have local regions 15 and 16, and 2.95 V for the static induction thyristor of this embodiment that has both local regions 15 and 16, and the present invention. Even if this is adopted, the increase will only be about double.

この第1実施例によるスイッチング特性を調べるため、
導通させたいタイミングにゲートに正電圧をパルス的に
加え、遮断させたいタイミングにゲートに負電圧をパル
ス的に加えて、種々の静電誘導型サイリスタのスイッチ
ング波形を測定した。
In order to investigate the switching characteristics of this first embodiment,
The switching waveforms of various electrostatic induction thyristors were measured by applying a positive voltage in pulses to the gate at the timing when conduction was desired, and by applying a negative voltage in pulses to the gate at the timing when the gate was desired to be cut off.

なお、アノードに印加した電圧は100Vである。Note that the voltage applied to the anode was 100V.

第2図はその結果を示すもので、アノード電流I^(主
電流)のスイッチング波形として、低不純物密度領域1
4の中に、荷電担体寿命の比較的短い局所的領域15.
16を共に持たない静電誘導型サイリスタの波形(a)
、局所的領域15のみを持つものの波形(b)、局所的
領域16のみを持つものの波形(C)、局所的領域15
.16を共に持つ本発明によるものの波形(d)が示さ
れている。
Figure 2 shows the results, and shows the switching waveform of the anode current I^ (main current) in the low impurity density region 1.
4, local regions of relatively short charge carrier lifetimes 15.
Waveform of a static induction thyristor that does not have 16 (a)
, Waveform (b) of one with only local area 15, Waveform (C) of one with only local area 16, Local area 15
.. The waveform (d) according to the invention with both 16 and 16 is shown.

第2図から判るように、ターンオン時間(導通過程に要
する時間で、ゲートにオン信号が入ってからアノード電
流■8が90%に達するまでの時間)は、上記4種類の
どの静電誘導型サイリスタも同じで、約0.2μsec
と高速であった。ターンオフ時間(遮断過程に要する時
間であり、蓄積時間t stgと立ち下がり時間1.の
合計)は、局所的領域15.16によって著しい影響を
受ける。
As can be seen from Fig. 2, the turn-on time (the time required for the conduction process, the time from when the ON signal is input to the gate until the anode current 8 reaches 90%) is different for which of the above four types of electrostatic induction type. The same goes for the thyristor, about 0.2 μsec.
And it was fast. The turn-off time (the time required for the switching off process, the sum of the accumulation time t stg and the fall time 1.) is significantly influenced by the local area 15.16.

なお、蓄積時間t stgはゲートにオフ信号が入って
からアノード電流!8が90%に下がるまでの時間、立
ち下がり時間t、はアノード電流I^が90%から10
%まで下がる時間である。
Note that the accumulation time t stg is the anode current after the off signal is input to the gate! The falling time t, which is the time it takes for the anode current I^ to drop from 90% to 10
This is the time it takes to drop to %.

荷電担体寿命の比較的短い局所的領域15゜16を共に
持たない静電誘導型サイリスタでは、蓄積時間t st
gは0.85μsecと比較的高速であるが、立ち下が
り時間tfは6μsecとあまり高速ではない。
In a static induction thyristor that does not have local regions 15°16 with relatively short charge carrier lifetimes, the accumulation time t st
g is relatively fast at 0.85 μsec, but the fall time tf is not very fast at 6 μsec.

それに対して、局所的領域15のみを付加した静電誘導
型サイリスタでは、その蓄積時間t stgは0.7μ
secでありあまり変わらないが、立ち下がり時間tr
は1.35μsecとなり若干高速になフている。
In contrast, in the electrostatic induction thyristor with only the local region 15 added, the accumulation time t stg is 0.7μ
sec and does not change much, but the fall time tr
is 1.35 μsec, which is slightly faster.

一方、局所的領域16のみを付加した静電誘導型サイリ
スタでは蓄積時間t stgは0.2μsecと若干高
速になるが、立ち下がり時間tfは4.7μSecとあ
まり高速にはならない。
On the other hand, in the electrostatic induction thyristor to which only the local region 16 is added, the accumulation time t stg is slightly faster at 0.2 μsec, but the fall time tf is not so fast at 4.7 μsec.

以上に対して、領域15.18を共に持つ本発明の静電
誘導型サイリスタでは、t stgは0.17と若干高
速になり、しかもtrは0.05μSecと非常に高速
になる。つまり、本発明の採用によりスイッチング時間
(ターンオン時間とターンオフ時間の合計)は、約7μ
secからやく0.4μsecと非常に短くなる。言い
換えると、スイッチング速度は本発明を実施しない静電
誘導型サイリスタに比べ約18倍高速になった。
On the other hand, in the electrostatic induction thyristor of the present invention having both regions 15 and 18, t stg is slightly faster at 0.17, and tr is extremely faster at 0.05 μSec. In other words, by adopting the present invention, the switching time (total of turn-on time and turn-off time) is approximately 7μ.
sec to 0.4 μsec, which is very short. In other words, the switching speed was approximately 18 times faster than that of a static induction thyristor not implementing the present invention.

以上の結果を次の表に示す。The above results are shown in the table below.

以上を総括すれば、本発明の実施例により約IKVとい
う高い順逆阻止電圧と、約3vというひくい順方向電圧
降下と、約0.4Vという高速のスイッチングを同時に
実現した。なお、領域15゜160形成法は陽子線照射
に限らず荷電担体寿命の局所的な低減法であればよいこ
とは明かであり、また半導体としてはシリコンに限らず
ゲルマニウム、ガリウム争ヒ素、等の他の半導体を用い
てもよいこともまた明かである。さらに、p型とn型を
すべて入れ替えた構造にしてもよいこともまた明かであ
る。また、アルミニウム配線はこれに限らず他の金属配
線(Ti、W)ないし金属シリサイド配線でもよい。
To summarize the above, the embodiment of the present invention simultaneously achieved a high forward and reverse blocking voltage of about IKV, a low forward voltage drop of about 3V, and high-speed switching of about 0.4V. It should be noted that the method for forming the 15° 160 region is not limited to proton beam irradiation; it is obvious that any method for locally reducing the charge carrier lifetime can be used, and the semiconductors can be used not only for silicon but also for germanium, gallium, arsenic, etc. It is also clear that other semiconductors may be used. Furthermore, it is also clear that a structure in which p-type and n-type are completely replaced is also possible. Further, the aluminum wiring is not limited to this, and other metal wiring (Ti, W) or metal silicide wiring may be used.

以上に、本発明を静電誘導型サイリスタに適用した第1
実施例について説明したが基本的動作機構を同じくする
他の半導体装置においても同様の作用をすることができ
る。以下、その数例について説明する。
The above describes the first example in which the present invention is applied to a static induction thyristor.
Although the embodiment has been described, other semiconductor devices having the same basic operating mechanism can also have similar effects. A few examples will be explained below.

第」と実」1例− 第3図は、本発明をゲートターンオフ・サイリスタに適
用した第2実施例を示すものである。
FIG. 3 shows a second embodiment in which the present invention is applied to a gate turn-off thyristor.

この第2実施例は、高不純物密度領域よりなるカソード
領域31と、そのカソード領域31とは反対の導電型の
高不純物密度領域よりなるアノード領域32と、カソー
ド領域31の近傍に設けた主電流を制御するゲート領域
33と、カソード領域31とアノード領域32との間に
ある低不純物密度領域34においてゲート領域近傍にあ
る荷電担体寿命の比較的短い局所的領域36と、カソー
ド領域31とアノード領域32との間にある低不純物密
度領域34において主電流遮断過程の最後に空乏化する
領域ないし最後まで空乏化しない領域にある荷電担体寿
命の比較的短い局所的領域36とを備えており、この基
本的構造は第1実施例と同様のものである。なお、30
は絶縁膜、31’ 、32’、33’はそれぞれカソー
ド領域31、アノード領域32、ゲート領域33に結合
された金属ないし金属シリサイド配線である。
This second embodiment has a cathode region 31 made of a high impurity density region, an anode region 32 made of a high impurity density region of the conductivity type opposite to that of the cathode region 31, and a main current provided near the cathode region 31. a local region 36 with a relatively short charge carrier lifetime near the gate region in the low impurity density region 34 between the cathode region 31 and the anode region 32; In the low impurity density region 34 between the main current cutoff process and the main current cut-off process, there is a local region 36 with a relatively short charge carrier life, which is a region that is depleted at the end of the main current interruption process or a region that is not depleted until the end. The basic structure is the same as the first embodiment. In addition, 30
is an insulating film, and 31', 32', and 33' are metal or metal silicide wirings coupled to the cathode region 31, anode region 32, and gate region 33, respectively.

ただ、本第2実施例は、ゲートターンオフ・サイリスタ
であり方ソード領域31の前面にもゲート領域33を有
するため、高い主電極間阻止電圧を実現するのに静電誘
導型サイリスタ程微細なパターンを必要としない。従っ
て、大面積化即ち大電流化が容易である。しかし、該構
造ではゲート抵抗を下げるためゲート領域33の不純物
密度を高くすると、静電誘導型サイリスタの場合とは異
なり順方向電圧降下が上昇する。従って、静電誘導型サ
イリスタよりスイッチングは低速である。
However, since the second embodiment is a gate turn-off thyristor and has a gate region 33 on the front surface of the sword region 31, a pattern as fine as that of an electrostatic induction thyristor is required to achieve a high blocking voltage between the main electrodes. do not need. Therefore, it is easy to increase the area, that is, increase the current. However, in this structure, when the impurity density of the gate region 33 is increased in order to lower the gate resistance, the forward voltage drop increases unlike in the case of a static induction thyristor. Therefore, the switching speed is slower than that of a static induction thyristor.

これらの点を除けば、第1実施例と基本的動作は同じで
あり、同様の作用、効果を奏することができる。
Other than these points, the basic operation is the same as that of the first embodiment, and similar actions and effects can be achieved.

篤」L実」1例− 第4図は、本発明を埋込みゲート型サイリスタに適用し
た第3実施例を示すものである。
Figure 4 shows a third embodiment in which the present invention is applied to a buried gate thyristor.

第3実施例は、高不純物密度領域よりなるカソード領域
41と、そのカソード領域41とは反対の導電型の高不
純物密度領域よりなるアノード領域42と、カソード領
域41の近傍に設けた主電流を制御するゲート領域43
と、カソード領域41とアノード領域42との間にある
低不純物布20一 度領域44においてゲート領域近傍にある荷重体寿命の
比較的短い局所的領域46と、カソード領域41とアノ
ード領域42との間にある低不純物密度領域44におい
て主電流遮断過程の最後に空乏化する領域ないし最後ま
で空乏化しない領域にある荷電担体寿命の比較的短い局
所的領域45とを備えており、この基本的構造は第1実
施例と同様のものである。また、その基本的作用効果も
同じものである。なお、40は絶縁膜、41′。
The third embodiment includes a cathode region 41 made of a high impurity density region, an anode region 42 made of a high impurity density region of a conductivity type opposite to that of the cathode region 41, and a main current provided near the cathode region 41. Gate region 43 to control
, the low impurity cloth 20 between the cathode region 41 and the anode region 42 , the local region 46 with a relatively short load body life near the gate region in the region 44 , and the region 46 between the cathode region 41 and the anode region 42 . A low impurity density region 44 in the main current cutoff process is depleted at the end of the main current cutoff process, and a local region 45 in which the charge carrier life is relatively short is located in a region that is not depleted to the end.This basic structure is as follows. This is similar to the first embodiment. Moreover, their basic functions and effects are also the same. Note that 40 is an insulating film and 41'.

42′はそれぞれカソード領域41、アノード領域42
に結合された金属ないし金属シリサイド配線である。
42' are a cathode region 41 and an anode region 42, respectively.
It is a metal or metal silicide interconnect connected to the

しかし、本実施例は、埋込みゲート型静電誘導型サイリ
スタであり、埋込みというその名の通りゲート領域43
を低不純物密度領域44内に埋込んだ構造を有する点で
、第1実施例の表面ゲート型静電誘導型サイリスタとは
異なる。
However, this embodiment is a buried gate type static induction type thyristor, and as the name suggests, the gate region 43 is buried.
This embodiment differs from the surface-gate electrostatic induction thyristor of the first embodiment in that it has a structure in which the thyristor is embedded in a low impurity density region 44.

本第3実施例は、第1実施例の表面ゲート型のものに比
べ、より高いゲート・カソード間耐圧を実現できる。従
って、高い主電極間阻止電圧の実現が容易である。また
、ゲーどの駆動電源用コンデンサが小さくて済むという
利点もある。
The third embodiment can achieve a higher gate-cathode breakdown voltage than the surface gate type of the first embodiment. Therefore, it is easy to realize a high blocking voltage between the main electrodes. Another advantage is that the drive power supply capacitor for each gate can be small.

ところで、ゲート、カソード間の耐圧を重視してゲート
、カソード間距離を大きくとると、その間に存在する荷
電担体が有効に消滅しなくなるので、この場合は、ゲー
トとカソードの間に荷電担体寿命の短い局所的領域を入
れることも可能である。
By the way, if the distance between the gate and the cathode is made large with emphasis on the withstand voltage between the gate and the cathode, the charge carriers existing between the gate and cathode will not be effectively eliminated. It is also possible to include short local regions.

第」L実」1例− 第5図は、本発明を絶縁ゲート型サイリスタに適用した
第4実施例を示すものである。
"L Practical" 1st Example - FIG. 5 shows a fourth embodiment in which the present invention is applied to an insulated gate thyristor.

第4実施例は、高不純物密度領域よりなるカソード領域
51と、そのカソード領域51とは反対の導電型の高不
純物密度領域よりなるアノード領域52と、カソード領
域51の近傍に設けた主電流を制御するゲート領域53
と、カソード領域51とアノード領域52との間にある
低不純物密度領域54においてゲート領域近傍にある荷
重体寿命の比較的短い局所的領域56と、カソード領域
51とアノード領域52との間にある低不純物密度領域
54中において主電流遮断過程の最後に空乏化する領域
ないし最後まで空乏化しない領域にある荷電担体寿命の
比較的短い局所的領域55とを備えており、この荷電担
体寿命の比較的短い局所的領域55.56を設ける基本
的構造は第1実施例と同様のものである。また、その基
本的作用効果も同じものである。
The fourth embodiment includes a cathode region 51 made of a high impurity density region, an anode region 52 made of a high impurity density region of a conductivity type opposite to that of the cathode region 51, and a main current provided near the cathode region 51. Gate region 53 to control
, a local region 56 with a relatively short load body life near the gate region in the low impurity density region 54 between the cathode region 51 and the anode region 52 , and a local region 56 between the cathode region 51 and the anode region 52 . The low impurity density region 54 includes a local region 55 with a relatively short charge carrier life, which is a region that is depleted at the end of the main current cutoff process or a region that is not depleted until the end, and the charge carrier life is compared. The basic structure of providing short local areas 55 and 56 is similar to that of the first embodiment. Moreover, their basic functions and effects are also the same.

ただ、この第4実施例は、絶縁ゲート型静電誘導型サイ
リスタであり、絶縁ゲート型というその名の通り第1実
施例のような通常の接合型ではなく、ゲート領域53を
絶縁膜50により分離した構造を有する点で、第1実施
例のような接合型の表面ゲート型静電誘導型サイリスタ
とは異なる。
However, this fourth embodiment is an insulated gate type electrostatic induction thyristor, and as the name suggests, it is not a normal junction type thyristor like the first embodiment, but the gate region 53 is formed by an insulating film 50. This embodiment differs from the junction type surface gate type static induction thyristor like the first embodiment in that it has a separate structure.

なお、51’ 、52’は金属ないし金属シリサイド電
極配線である。
Note that 51' and 52' are metal or metal silicide electrode wirings.

第4実施例の静電誘導型サイリスタは、第1実施例の接
合型静電誘導型サイリスタのような低入力インピーダン
スではなく、高入力インピーダンスである。従って、ゲ
ートの駆動回路が簡単になる利点がある。
The electrostatic induction thyristor of the fourth embodiment does not have a low input impedance like the junction type electrostatic induction thyristor of the first embodiment, but has a high input impedance. Therefore, there is an advantage that the gate drive circuit becomes simple.

なお、この第4実施例は表面ゲート型であるが、第3実
施例のような埋込みゲート型として構成することができ
ることは明かである。
Although this fourth embodiment is of the surface gate type, it is obvious that it can be configured as a buried gate type like the third embodiment.

第」L実」1例− 第6図は、第1実施例において、そのアノード領域前面
に比較的不純物密度の高い薄層領域67を設けた構造を
有する第5実施例を示すものである。
Example 1 of "L Practical Example" FIG. 6 shows a fifth example having a structure in which a thin layer region 67 having a relatively high impurity density is provided in front of the anode region in the first example.

即ち、第5実施例は、高不純物密度領域よりなるカッニ
ド領域61と、そのカソード領域61とは反対の導電型
の高不純物密度領域よりなるアノード領域62と、カソ
ード領域61の近傍に設けた主電流を制御するゲート領
域63と、カソード領域61とアノード領域62との間
にある低不純物密度領域64中においてゲート領域近傍
に位置する荷重体寿命の比較的短い局所的領域66と、
比較的不純物密度の高い薄層領域67において主電流遮
断過程の最後に空乏化する領域ないし最後まで空乏化し
ない領域にある荷電担体寿命の比較的短い局所的領域 
65とを備えており、この基24一 本釣構造は第1実施例と同様のものである。また、その
基本的作用効果も同じものである。
That is, the fifth embodiment has a cannide region 61 made of a high impurity density region, an anode region 62 made of a high impurity density region of a conductivity type opposite to that of the cathode region 61, and a main region provided near the cathode region 61. a gate region 63 for controlling current; a local region 66 with a relatively short load body life located near the gate region in a low impurity density region 64 between the cathode region 61 and the anode region 62;
A local region with a relatively short charge carrier life in a region that is depleted at the end of the main current interruption process or a region that is not depleted until the end in the thin layer region 67 with a relatively high impurity density.
65, and the pole-and-line fishing structure of this base 24 is similar to that of the first embodiment. Moreover, their basic functions and effects are also the same.

第1実施例とは異なる特徴は、前述のようにアノード領
域62の前面に比較的不純物密度の高い薄層領域67を
設け、その中に局所的領域65を配置したことにあり、
この構造により主電流遮断状態においてアノード領域6
2に印加されている最大阻止電圧によってゲート領域6
1とアノード領域62との間の電界分布が四辺形状をな
し、比較的不純物密度の高い薄層領域67が空乏化しな
い領域として残るようにしたものである。
The feature different from the first embodiment is that, as described above, a thin layer region 67 with a relatively high impurity density is provided on the front surface of the anode region 62, and a local region 65 is arranged within the thin layer region 67.
With this structure, the anode region 6
The maximum blocking voltage applied to gate region 6
The electric field distribution between the anode region 1 and the anode region 62 has a quadrilateral shape, and the thin layer region 67 having a relatively high impurity density remains as a region that will not be depleted.

従って、この第5実施例の静電誘導型サイリスタは第1
実施例の静電誘導型サイリスタに比べ、同じ厚さの低不
純物密度領域によって、より高い主電極間阻止電圧を実
現できる利点がある。
Therefore, the electrostatic induction thyristor of this fifth embodiment is
Compared to the electrostatic induction thyristor of the embodiment, there is an advantage that a higher blocking voltage between the main electrodes can be realized by using a low impurity density region of the same thickness.

なお、この第5実施例の薄層領域67を設ける構造は第
2、第3、第4の各実施例に対しても適用可能である。
The structure in which the thin layer region 67 of the fifth embodiment is provided is also applicable to the second, third, and fourth embodiments.

第JJL血り一 第7図は、第1実施例において、そのアノード領域の一
部にカソード領・域と同じ導電型の不純物密度領域79
を設け、アノード領域と同電位とした構造を有する第6
実施例を示すものである。
7 shows an impurity density region 79 of the same conductivity type as the cathode region in a part of the anode region in the first embodiment.
The sixth region has a structure in which the anode region is provided with the same potential as the anode region.
This is an example.

即ち、第6実施例は、高不純物密度領域よりなるカソー
ド領域71と、そのカソード領域71とは反対の導電型
の高不純物密度領域よりなるアノード領域72と、カソ
ード領域71の近傍に設けた主電流を制御するゲート領
域73と、カソード領域71とアノード領域72との間
にある低不純物密度領域74においてゲート領域73の
近傍にある荷電体寿命の比較的短い局所的領域76と、
カソード領域71とアノード領域72との間にある低不
純物密度領域74において主電流遮断過程の最後に空乏
化する領域ないし最後まで空乏化しない領域にある荷電
担体寿命の比較的短い局所的領域76とを備えている。
That is, the sixth embodiment has a cathode region 71 made of a high impurity density region, an anode region 72 made of a high impurity density region of a conductivity type opposite to that of the cathode region 71, and a main region provided near the cathode region 71. a gate region 73 for controlling current; a local region 76 with a relatively short charged body life near the gate region 73 in a low impurity density region 74 between the cathode region 71 and the anode region 72;
In the low impurity density region 74 between the cathode region 71 and the anode region 72, there is a local region 76 with a relatively short charge carrier life, which is a region that is depleted at the end of the main current cutoff process or a region that is not depleted until the end. It is equipped with

なお、70は絶縁膜、71’、?2’、73’は金属な
いし金属シリサイド電極配線である。この基本的構造は
第1実施例と同様のものである。また、その基本的作用
効果も同じものである。
In addition, 70 is an insulating film, 71', ? 2' and 73' are metal or metal silicide electrode wirings. This basic structure is similar to the first embodiment. Moreover, their basic functions and effects are also the same.

第1実施例とは異なる特徴は、前記基本的構造において
、アノード領域72の一部にカソード領域と同じ導電型
の不純物密度領域79を設け、これをアノード領域72
と同電位として用いるようにしたことにある。この構造
により領域79はカソード領域 71と同じ導電型であ
るので、低不純物密度領域74にカソード領域71から
注入された荷電担体が掃き出されやすく、従って、ター
ンオフ時間がより短くなる利点がある。
A feature different from the first embodiment is that in the basic structure, an impurity density region 79 of the same conductivity type as the cathode region is provided in a part of the anode region 72, and this
The reason is that it is used at the same potential as the With this structure, since the region 79 has the same conductivity type as the cathode region 71, charge carriers injected from the cathode region 71 into the low impurity density region 74 can be easily swept away, which has the advantage of shortening the turn-off time.

なお、この第6実施例のアノード領域72の一部にカソ
ード領域71と同じ導電型の不純物密度領域79を設け
る構造は、第2、第3、第4、および第5の各実施例に
対しても適用可能である。
Note that the structure in which the impurity density region 79 of the same conductivity type as the cathode region 71 is provided in a part of the anode region 72 of the sixth embodiment is different from that of the second, third, fourth, and fifth embodiments. It is also applicable.

IL影糺1 第8図は、本発明を両面ゲート型静電誘導型サイリスタ
に適用した第7実施例を示すものである。
IL Imaging 1 FIG. 8 shows a seventh embodiment in which the present invention is applied to a double-sided gate type static induction thyristor.

この両面ゲート型静電誘導型サイリスタは、主電流を制
御するゲートをカソード領域近傍と、アノード領域近傍
の両方に設けたことを特徴とする。
This double-sided gate type electrostatic induction thyristor is characterized in that gates for controlling the main current are provided both near the cathode region and near the anode region.

即ち、この第7の実施例は、高不純物密度領域よりなる
カソード領域81と、そのカソード領域81とは反対の
導電型の高不純物密度領域よりなるアノード領域82と
、カソード領域81の近傍に設けた主電流を制御する第
1のゲート領域83と、アノード領域82の近傍に設け
た主電流を制御する第2のゲート領域88と、カソード
領域81とアノード領域82との間の低不純物密度領域
84中においてそれぞれ第1および第2のゲート領域8
3および88の近傍に位置する荷電体寿命の比較的短い
第1および第3の局所的領@86および89と、カソー
ド領域81とアノード領域82との間の中央付近に位置
する主電流遮断過程の最後に空乏化する領域ないし最後
まで空乏化しない領域にある荷電担体寿命の比較的短い
第2の局所的領域85とを備えている。なお、80は絶
縁膜、81’ 、82’ 、83’は金属ないし金属シ
リサイド電極配線である。このような構造の第7実施例
は、第1実施例に第2ゲート領域88および第3の局所
的領域89を追加した構成と作用効果に特徴を有するが
、基本的作用効果は第1実−列一 施例と同じである。
That is, this seventh embodiment has a cathode region 81 made of a high impurity density region, an anode region 82 made of a high impurity density region of the opposite conductivity type to that of the cathode region 81, and a cathode region 82 provided near the cathode region 81. a first gate region 83 for controlling the main current, a second gate region 88 for controlling the main current provided near the anode region 82, and a low impurity density region between the cathode region 81 and the anode region 82. first and second gate regions 8 in 84 respectively;
The main current interruption process is located near the first and third local regions @ 86 and 89 with relatively short charged body lifetimes located near 3 and 88 and the center between the cathode region 81 and the anode region 82. A second local region 85 having a relatively short charge carrier lifetime is provided in a region that is depleted at the end or a region that is not depleted until the end. Note that 80 is an insulating film, and 81', 82', and 83' are metal or metal silicide electrode wirings. The seventh embodiment with such a structure is characterized by the structure and effect of adding the second gate region 88 and third local region 89 to the first embodiment, but the basic function and effect are the same as those of the first embodiment. - Column 1 is the same as the example.

第7実施例において、カソード領域81近傍の第1ゲー
ト領域83はカソード領域81からの荷電担体の注入を
制御し、アノード領域82近傍の第2ゲート領域88は
アノード領域82からの荷電担体の注入を制御する。従
って、カソード領域81からの荷電担体の注入のみを制
御する第1実施例の静電誘導型サイリスタに比べより高
速のスイッチングが実現できる利点がある。
In the seventh embodiment, a first gate region 83 near the cathode region 81 controls the injection of charge carriers from the cathode region 81, and a second gate region 88 near the anode region 82 controls the injection of charge carriers from the anode region 82. control. Therefore, compared to the electrostatic induction thyristor of the first embodiment, which controls only the injection of charge carriers from the cathode region 81, there is an advantage that faster switching can be realized.

なお、この実施例の両面ゲート型静電誘導型サイリスタ
のゲート構造は、前述の各実施例において示した表面ゲ
ート型、埋込みゲート型、接合ゲート型、あるいは絶縁
ゲート型等と任意に組み合わせて実施することができる
Note that the gate structure of the double-sided gate type static induction thyristor of this example can be implemented in any combination with the surface gate type, buried gate type, junction gate type, or insulated gate type shown in each of the above-mentioned examples. can do.

以上に示した種々の実施例においては、荷電担体寿命の
比較的短い局所的な2ないし3領域はそれらの間隔が低
不純物密度領域における荷電担体の拡散長以内である場
合の例を示したが、局所的な2ないし3領域の間隔が該
拡散長以上となった場合には、荷電担体の再結合の効果
が低くなるので、前記局所的な2ないし3領域の間に更
に1箇所以上の荷電担体寿命の比較的短い局所的な領域
を追加して設けることが有効である。
In the various embodiments shown above, the distance between the two or three local regions where the charge carrier lifetime is relatively short is within the diffusion length of the charge carrier in the low impurity density region. If the interval between two or three local regions is equal to or greater than the diffusion length, the effect of recombination of charge carriers will be reduced, so one or more additional locations will be added between the two or three local regions. It is advantageous to provide additional local regions with relatively short charge carrier lifetimes.

また、これと同じ理由により、ゲート領域とカソード領
域の間隙が低不純物密度領域における荷電担体の拡散長
以上になった場合には、カソード領域近傍の低不純物密
度領域に荷電担体寿命の比較的短い局所的領域を追加し
て設けることも有効である。
Also, for the same reason, when the gap between the gate region and the cathode region is longer than the diffusion length of charge carriers in the low impurity density region, the charge carrier life is relatively short in the low impurity density region near the cathode region. It is also effective to provide additional local areas.

(発明の効果) 以上に説明したように、本発明によれば、主電極間阻止
電圧を得るための低不純物密度領域領域中の、カソード
領域の近傍の領域と、主電流遮断過程の最後に空乏化す
る領域ないし最後まで空乏化しない領域とに、荷電担体
寿命の比較的短い局所的領域を共に設けることによって
、高い主電極間阻止電圧、低い順方向電圧降下、および
高速のスイッチングを共に備えた優れた特性の半導体装
置を実現することができる。
(Effects of the Invention) As explained above, according to the present invention, the region near the cathode region in the low impurity density region for obtaining the main inter-electrode blocking voltage and the end of the main current cutoff process. By providing a depleted region or a region that is not fully depleted together with a localized region with a relatively short charge carrier lifetime, a high main electrode blocking voltage, low forward voltage drop, and high speed switching can be achieved. A semiconductor device with excellent characteristics can be realized.

従って、本発明によれば制御周波数を高くして可聴周波
数外となる領域で使用することができるので、装置の出
す騒音を著しく減少させることができる。
Therefore, according to the present invention, the control frequency can be raised to allow use in a region outside of the audible frequency range, so that the noise generated by the device can be significantly reduced.

また、高い周波数で用いてもスイッチング損失が小さい
ので、放熱設計が楽になるとともに、装置を小型軽量化
することができる。
Further, since switching loss is small even when used at high frequencies, heat dissipation design becomes easier and the device can be made smaller and lighter.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は、本発明を表面ゲート型静電誘導型サイリスタ
に適用した第1実施例を示す断面図である。 第2図は、第1実施例のスイッチング波形および従来例
のスイッチング波形を示すものである。 第3図は、本発明をゲートターンオフサイリスタに適用
した第2実施例を示す断面図である。 第4図は、本発明を埋込みゲート型サイリスタに適用し
た第3実施例を示す断面図である。 第5図は、本発明を絶縁ゲート型静電誘導型サイリスタ
に適用した第4実施例を示す断面図である。 第6図は、本発明を第1実施例において、そのアノード
領域前面に比較的不純物密度の高い薄層領域を設けた構
造を有する第5実施例を示す断面図である。 第7図は、本発明を第1実施例において、そのアノード
領域の一部にカソード領域と同じ導電型の不純物密度領
域を設け、アノード領域と同電位としたことを特徴とす
る第6実施例を示す断面図である。 第8図は、本発明を両面ゲート型静電誘導型サイリスタ
に適用した第7実施例を示す断面図である。 10.30,40,50,60.To、80・・・絶縁
膜、11.31,41,51,61,71.81−11
0カソード領域、12.32,42,52,62,72
.82・・・アノード領域、13.33,43,53,
63,73,83φ・・ゲート領域、14.34,44
,54,64,74.84・・・低不純物密度領域、+
5.35,45.55,65,75.85・・・主電流
遮断過程において最後°に空乏化する領域ないし最後ま
で空乏化しない領域にある荷電担体寿命の比較的短い局
所的領域、 +6.36,46,56,66.76.866・Φゲー
ト領域の近傍にある荷電担体寿命の比較的短い局所的領
域、67・・・比較的不純物密度の高い領域、79・・
拳カソード領域と同し導電型でありアノード領域と同電
位である領域、 88・・・第2ゲート領域、 89φ・・第2ゲート領域近傍にある荷電担体寿命の比
較的短い局所的領域。 特許出願人  株式会社豊田中央研究所第3図 第4図 第5図 第6図 第7図 72′ 第8図
FIG. 1 is a sectional view showing a first embodiment in which the present invention is applied to a surface gate type electrostatic induction thyristor. FIG. 2 shows the switching waveforms of the first embodiment and the conventional example. FIG. 3 is a sectional view showing a second embodiment in which the present invention is applied to a gate turn-off thyristor. FIG. 4 is a sectional view showing a third embodiment in which the present invention is applied to a buried gate thyristor. FIG. 5 is a sectional view showing a fourth embodiment in which the present invention is applied to an insulated gate electrostatic induction thyristor. FIG. 6 is a sectional view showing a fifth embodiment of the present invention having a structure in which a thin layer region with relatively high impurity density is provided in front of the anode region in the first embodiment of the present invention. FIG. 7 shows a sixth embodiment of the present invention in which, in the first embodiment, an impurity density region of the same conductivity type as the cathode region is provided in a part of the anode region, and the potential is the same as that of the anode region. FIG. FIG. 8 is a sectional view showing a seventh embodiment in which the present invention is applied to a double-sided gate type electrostatic induction thyristor. 10.30,40,50,60. To, 80... Insulating film, 11.31, 41, 51, 61, 71.81-11
0 cathode area, 12.32, 42, 52, 62, 72
.. 82... Anode region, 13.33, 43, 53,
63, 73, 83φ...gate region, 14.34, 44
, 54, 64, 74.84...low impurity density region, +
5.35, 45.55, 65, 75.85... A local region with a relatively short charge carrier life in a region that is the last to be depleted or a region that is not depleted to the end in the main current interruption process, +6. 36, 46, 56, 66. 76. 866 Φ Local region with relatively short charge carrier lifetime near gate region, 67... Region with relatively high impurity density, 79...
A region having the same conductivity type as the fist cathode region and the same potential as the anode region, 88...Second gate region, 89φ...A local region with a relatively short charge carrier life in the vicinity of the second gate region. Patent applicant Toyota Central Research Institute Co., Ltd. Figure 3 Figure 4 Figure 5 Figure 6 Figure 7 Figure 72' Figure 8

Claims (9)

【特許請求の範囲】[Claims] (1)互いに反対導電型の高不純物密度領域よりなるカ
ソード領域およびアノード領域と、この2つの領域の間
の一部にある低不純物密度領域と、前記カソード領域近
傍に設けた主電流を制御するゲート領域を有する半導体
装置において、前記低不純物密度領域の中の、ゲート領
域の近傍の領域と、主電流の遮断過程の最後に空乏化す
る領域ないしは最後まで空乏化しない領域とに、荷電担
体寿命の比較的短い局所的領域を設けたことを特徴とす
る半導体装置。
(1) A cathode region and an anode region consisting of high impurity density regions of mutually opposite conductivity types, a low impurity density region located in a part between these two regions, and a main current provided near the cathode region are controlled. In a semiconductor device having a gate region, a charge carrier life span exists in a region near the gate region in the low impurity density region and a region that is depleted at the end of the main current cutoff process or a region that is not depleted until the end. A semiconductor device characterized in that a relatively short local region is provided.
(2)ゲート領域をカソード領域近傍にメッシュ状ある
いはストライプ状に設けた表面ゲート型静電誘導型サイ
リスタとして構成したことを特徴とする特許請求の範囲
第(1)項記載の半導体装置。
(2) The semiconductor device according to claim (1), characterized in that the semiconductor device is configured as a surface-gate electrostatic induction thyristor in which the gate region is provided in the vicinity of the cathode region in the form of a mesh or stripe.
(3)カソード領域の前面にもゲート領域を有し、ゲー
トターンオフ・サイリスタとして構成したことを特徴と
する特許請求の範囲第(1)項記載の半導体装置。
(3) The semiconductor device according to claim (1), further comprising a gate region in front of the cathode region, and configured as a gate turn-off thyristor.
(4)ゲート領域を低不純物密度領域内に埋込んだ構造
の埋込み型静電誘導型サイリスタとして構成したことを
特徴とする特許請求の範囲第(1)項記載の半導体装置
(4) The semiconductor device according to claim (1), wherein the semiconductor device is configured as a buried electrostatic induction thyristor in which the gate region is buried in a low impurity density region.
(5)ゲート領域を絶縁膜で囲み絶縁ゲート型静電誘導
型サイリスタとして構成したことを特徴とする特許請求
の範囲第(1)項、第(2)項または第(4)項のいず
れか1項に記載の半導体装置。
(5) Any one of claims (1), (2), or (4), characterized in that the gate region is surrounded by an insulating film to constitute an insulated gate electrostatic induction thyristor. The semiconductor device according to item 1.
(6)アノード領域前面に不純物密度の比較的高い薄層
領域を設け、その薄層領域中に荷電担体寿命の比較的短
い局所的領域の1つを設けたことを特徴とする特許請求
の範囲第(1)項から第(5)項までのいずれか1項に
記載の半導体装置。
(6) Claims characterized in that a thin layer region with relatively high impurity density is provided in front of the anode region, and one local region with a relatively short charge carrier life is provided in the thin layer region. The semiconductor device according to any one of items (1) to (5).
(7)アノード領域の一部にカソード領域と同じ導電型
の不純物密度領域を設け、これをアノード領域と同電位
として用いることを特徴とする特許請求の範囲第(1)
項から第(6)項までのいずれか1項に記載の半導体装
置。
(7) Claim (1) characterized in that an impurity density region of the same conductivity type as the cathode region is provided in a part of the anode region, and this region is used at the same potential as the anode region.
The semiconductor device according to any one of paragraphs to (6).
(8)ゲート領域が、カソード領域の近傍に設けた第1
ゲート領域とアノード領域の近傍に設けた第2ゲート領
域との2つの領域からなり、これらの2つのゲート領域
の近傍およびこれらの2つのゲート領域の中間に位置す
るところの主電流遮断過程において最後に空乏化する領
域ないし最後まで空乏化しない領域に、荷電担体寿命の
比較的短い領域を設けたことを特徴とする特許請求の範
囲第(1)項から第(7)項までのいずれか1項に記載
の半導体装置。
(8) The gate region is located near the cathode region.
It consists of two regions: a gate region and a second gate region provided near the anode region. Any one of claims (1) to (7), characterized in that a region with a relatively short charge carrier life is provided in a region that is depleted until the end or a region that is not depleted to the end. The semiconductor device described in .
(9)荷電担体寿命の比較的短い局所的領域の間の間隔
が前記低不純物密度領域における荷電担体の拡散長以上
とならないように、前記局所的領域を3個以上設けたこ
とを特徴とする特許請求の範囲第(1)項から第(8)
項までのいずれか1項に記載の半導体装置。
(9) Three or more of the local regions are provided so that the distance between the local regions having relatively short charge carrier lifetimes is no longer than the diffusion length of the charge carriers in the low impurity density region. Claims (1) to (8)
The semiconductor device according to any one of the preceding items.
JP7941986A 1985-09-28 1986-04-07 Semiconductor device Granted JPS62235782A (en)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP7941986A JPS62235782A (en) 1986-04-07 1986-04-07 Semiconductor device
US06/912,578 US4752818A (en) 1985-09-28 1986-09-26 Semiconductor device with multiple recombination center layers

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP7941986A JPS62235782A (en) 1986-04-07 1986-04-07 Semiconductor device

Publications (2)

Publication Number Publication Date
JPS62235782A true JPS62235782A (en) 1987-10-15
JPH0553073B2 JPH0553073B2 (en) 1993-08-09

Family

ID=13689346

Family Applications (1)

Application Number Title Priority Date Filing Date
JP7941986A Granted JPS62235782A (en) 1985-09-28 1986-04-07 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS62235782A (en)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01272157A (en) * 1988-04-23 1989-10-31 Matsushita Electric Works Ltd Semiconductor device
JPH02110971A (en) * 1988-10-19 1990-04-24 Matsushita Electric Works Ltd Semiconductor device
US5025293A (en) * 1989-01-25 1991-06-18 Fuji Electric Co., Ltd. Conductivity modulation type MOSFET
US5075751A (en) * 1987-12-18 1991-12-24 Matsushita Electric Works, Ltd. Semiconductor device
JP2004510353A (en) * 2000-09-29 2004-04-02 オイペク オイロペーシェ ゲゼルシャフト フューア ライストゥングスハルプライター エムベーハー Straight body of semiconductor material with reduced mean free path length
EP2172976A2 (en) 1998-09-10 2010-04-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor Device

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53108387A (en) * 1977-02-07 1978-09-21 Gen Electric Junction semiconductor and method of producing same
JPS5739577A (en) * 1980-06-27 1982-03-04 Westinghouse Electric Corp Method of reducing reverse recovery charge for thyristor
JPS6074443A (en) * 1983-07-01 1985-04-26 ブラウン・ボバリ・ウント・シ−・アクチエンゲゼルシヤフト P-n junction semiconductor element and method of producing same

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS53108387A (en) * 1977-02-07 1978-09-21 Gen Electric Junction semiconductor and method of producing same
JPS5739577A (en) * 1980-06-27 1982-03-04 Westinghouse Electric Corp Method of reducing reverse recovery charge for thyristor
JPS6074443A (en) * 1983-07-01 1985-04-26 ブラウン・ボバリ・ウント・シ−・アクチエンゲゼルシヤフト P-n junction semiconductor element and method of producing same

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5075751A (en) * 1987-12-18 1991-12-24 Matsushita Electric Works, Ltd. Semiconductor device
JPH01272157A (en) * 1988-04-23 1989-10-31 Matsushita Electric Works Ltd Semiconductor device
JPH02110971A (en) * 1988-10-19 1990-04-24 Matsushita Electric Works Ltd Semiconductor device
US5025293A (en) * 1989-01-25 1991-06-18 Fuji Electric Co., Ltd. Conductivity modulation type MOSFET
EP2172976A2 (en) 1998-09-10 2010-04-07 Mitsubishi Denki Kabushiki Kaisha Semiconductor Device
JP2004510353A (en) * 2000-09-29 2004-04-02 オイペク オイロペーシェ ゲゼルシャフト フューア ライストゥングスハルプライター エムベーハー Straight body of semiconductor material with reduced mean free path length
JP4725877B2 (en) * 2000-09-29 2011-07-13 インフィネオン テクノロジーズ アーゲー Straight body of a semiconductor material having a reduced mean free path length

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